CSP1093C - Agere Systems, Inc.

Product Brief

February 2001

Lucent CSP1093C GSM 2+ Conversion Signal Processor

for Cellular Handset and Modem Applications

Lucent Technologies - Proprietary

Use pursuant to Compan

instr u cti ons

Features

■Supports the pre vious features of GSM phase 2+ and mul-

tislotting (GPRS). All multislotting classes (1 to 18) are

supported (inclu ding type 1 and type 2 MS).

■Supports both heterodyne and direct conversion RF trans-

ceivers and provides hardware dc offset correction.

■Seamless interface to the DSP16000 family of processors

and a variety of RF chips (transceiver and frequency syn-

thesizer).

■Complete ADC (analog-to-digital conversion) and D AC

(digital-to-analog conv ers ion) functions f or baseband and

voice band, including DAI (digital audio interface).

■Integrated event timing and control state machine that

monitors the internal quarter-bit counter and internal frame

counter until a programmed time is reached, and then exe-

cutes the control portion of the register and may issue an

interrupt to the DSP.

■GMSK modulator that accepts 88 bits, 148 bits, or several

slots (multislot) of burst data from an internal register and

modulates the data into GSM standards. Phase informa-

tion is converted into I and Q output voltages that can be

connected directly to an RF transceiver or RF modulator.

■Power ramping control with the capability of dipping and/or

changing power levels between consecutive bursts.

■Received baseband I and Q signals are ADC converted at

two user selectable rates (270 Ksamples/s and

540 Ksamples/s) and the samples are then stored in a

double buff er that holds 32 I and 32 Q samples bef ore issu-

ing an interrupt to the DSP to read the sample informat ion.

■Twelve output control lines that can be used to control

e xternal circuits f or such functions as pow er on/off or digital

gain control.

■Serial port that can be used to program external RF chips

such as transceivers and frequency synthesizers.

■Hardware support for A5.1 and A5.2 ciphering.

■Interrupt handling capabilit ies for voice band samples,

received baseband data, A5 ciphering, timing and control,

and end of transmission notification.

■Low-power sleep mode and wake-up. Capability of switch-

ing to slow clock during s leep mode.

■Innov ativ e offset cancellation scheme f or both Tx and Rx to

support continuous Tx and Rx.

■Voice band input connects directly to electrect microphone

and output connects directly to speaker.

■

IEEE

* 1149.1 JTA G controller and boundary-scan register.

■32 kHz slow clock on-chip oscillator (direct connection to a

32 kHz cry s tal or external oscillator).

Description

The Lucent CSP1093C integrates the timing and control

functions for GSM phase 2+ mobile application with the ADC

and D A C functions. The CSP1093C interf aces to an e xternal

controlling de v ice , t ypically a DSP or a microcontroller, via a

16-bit parallel interface. It serves as the interface that con-

nects a DSP to the RF circuitry in a GSM phase 2+ mobile

telephone. All multislotting classes of GSM phase 2+ are

fully supported by the Lucent CSP1093C.

F or example, when transmitting data, a DSP can load

148 bits of burst data into the Lucent CSP1093C’s internal

and control register with the ex ac t time to send the burst.

When the timing portion of the event timing and control reg-

ister matches the internal quarter-bit counter and internal

frame counter, the 148 bits in the internal register are GMSK

modulated according to GSM phase 2+ standards. The

resulting phase information is translated into I and Q differ-

ential output voltages that can be connected directly to an

RF modulator. The DSP is notified when the transmission is

completed.

F or receiving baseband data, a DSP can program the

Lucent CSP1093C’s event timing and control register with

the e xact time to start receiving I and Q samples. When that

time is reached, the control portion of the event timing and

control register will start the baseband receiv e section con-

vert ing I and Q sample pairs. The samples are stored in a

double-buffered register until the register contains 32 sam-

ple pairs. The Lucent CSP1093C then notifies the DSP,

which has ample time to read the inf ormation out before the

next 32 sample pairs are stored.

The voice band ADC converter issues an interrupt to the

DSP whene ver it f inishes con verting a 16-bit PCM word. The

DSP then reads the new input sample and simultaneously

loads the voice band output DAC conv erter with a new PCM

output word. The voice band output can be connected

directly to a speaker.

IEEE

is a registered trademark of The Institute of Electrical and Elec-

tronics Engineers, Inc.

Lucent CSP1093C GSM 2+ Conversion Signal Processor Product Brief

for Cellular Handset and Modem Applications February 2001

Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No

rights under any patent accompany the sale of any such product(s) or information.

February 2001

PB01-042WTEC

For additional information, contact your Microelectronics Group Account Manager or the following:

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Description (continued)

The Lucent CSP1093C is designed to interface a digital signal processor with analog audio and baseband signals,

programmable events, power timers, and filters. The device provides analog interfacing and timing for a GSM

phase 2+ mobile cellular telecommunications terminal requiring low power consumption. Figure 1 contains a block

diagram of the Lucent CSP1093C.

Figure 1. Lucent CSP1093C Block Diagram

5-9254 (F)

DIGITAL AUDIO

INTERFACE

AUXIN

16-bit ADC

AOUTAN

AOUTAP 16-bit DAC GAIN

CONTROL

INTERFACE

AB[8:0] ADDRESS

DB[15:0] DATA

R/W

I/O

CINTR, DINTR

GSM STANDARD

GMSK MODULATOR

PGA

1/4-bit

COUNTER FRAME

COUNTER

TIMING AND CONTROL

REGISTERS EXTERNAL

CONTROL LINES

TxP

TxI

TxQ

RxI

RxQ

RF CHIPS

MASTER CLOCK

TRAMSMIT

BUFFER

160 bits

64-word

BUFFER

CLOCK

10-bit ADC

10- bi t DAC

9-bit DAC

MUX

JTAG

A5.1/A5.2

POW ER RAMP

AAF

SERIAL

OUTPUT

XOENA

AOUTBP

AOUTBN

OCTL

XTALA

AND PGA

9-bit DAC

AND PGA

MICIN

32 kHz

XTALB

SLEEP

MODE LOGIC

RFOVL

AFC

12-bit DAC

AFC REGISTER

A5 BUFFER

(x2)

XOENAQ

OSCILLATOR

CIRCUITRY

RATE

SELECT