This document is a general product description and is subject t o change without notice. Hynix Semiconductor do es not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3 / Oct. 2008 1
240pin Registered DDR2 SDRAM DIMMs based on 1Gb version E
This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb version E DDR2
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb
version E based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" wid th
form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
ORDERING INFORMATION
Part Name Density Organization # of
DRAMs # of
ranks Materials Parity
Support
HMP112P7EFR8C-C4/Y5/S6/S5 1GB 128Mx72 9 1 Halogen Free O
HMP125P7EFR8C-C4/Y5/S6/S5 2GB 256Mx72 18 2 Halogen Free O
HMP125P7EFR4C-C4/Y5/S6/S5 2GB 256Mx72 18 1 Halogen Free O
HMP151P7EFR8C-C4/Y5/S6/S5 4GB 512Mx72 36 4 Halogen Free O
HMP151P7EFR4C-C4/Y5/S6/S5 4GB 512Mx72 36 2 Halogen Free O
HMP31GP7EMR4C-C4/Y5 8GB 512Mx72 72 4 Halogen Free O
• JEDEC standard Double Data Rate2 Synchro-
nous DRAMs (DDR2 SDRAMs) with 1.8V +/-
0.1V Power Supply
• All inputs and outputs are compatible with
SSTL_1.8 interface
•8 Bank architecture
•Posted CAS
• Programmable CAS Latency 3, 4, 5, 6
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both
sequential and interleave mode
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60 ball(x4/x8)
• 133.35 x 30.00 mm form factor
• Halogen free & RoHS compliant
Rev. 0.3 / Oct. 2008 2
1
240pin Registered DDR2 SDRAM DIMMs
SPEED GRADE & KEY PARAMETERS
ADDRESS TABLE
C4
(DDR2-533) Y5
(DDR2-667) S6
(DDR2-800) S5
(DDR2-800) Unit
Speed@CL3 400 400 - 400 Mbps
Speed@CL4 533 533 533 533 Mbps
Speed@CL5 - 667 667 800 Mbps
Speed@CL6 - - 800 - Mbps
CL-tRCD-tRP 4-4-4 5-5-5 6-6-6 5-5-5 tCK
Density Organization Ranks SDRAMs # of
DRAMs # of row/bank/column Address Refresh
Method
1GB 128M x 72 1 128Mb x 8 9 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms
2GB 256M x 72 2 128Mb x 8 18 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms
2GB 256M x 72 1 256Mb x 4 18 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms
4GB 512M x 72 4 128Mb x 8 36 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms
4GB 512M x 72 2 256Mb x 4 36 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms
8GB 1G x 72 4 256Mb x 4 72 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms
Rev. 0.3 / Oct. 2008 3
1
240pin Registered DDR2 SDRAM DIMMs
Input/Output Functional Description
Symbol Type Polarity Pin Description
CK0 IN Positive
Edge Positive line of the differential p air of system clock inputs that drives input to the on-DIMM PLL.
CK0IN
Negative
Edge Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CKE[1:0] IN Active High Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivat-
ing the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
S[1:0] IN Active Low Enables the associated DDR2 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ign ored but previous
operations continue. Rank 0 is selected by S0; Rank 1 i s s ele cted by S1
ODT[1:0] IN Active High On-Die Termination signals.
RAS, CAS, WE IN Active Low When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the
command being entered.
Vref Supply Reference voltage for SSTL18 inputs
VDDQ Supply Power supplies f or the DDR2 SDRAM output buffers to provide improved noise immunity. For all current
DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
BA[2:0] IN - Selects which DDR2 SDRAM internal bank of Eight is activated.
A[9:0],A10/AP
A[13:11] IN -
During a Bank Activate command cycle, Address input difines the row address(RA0~RA13)
During a Read or Write command cycle, Address input defines the column address when sampled at the
cross point of the rising edge of CK and falling edge of CK. In addition to the colu mn address, AP is used
to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autopre-
charge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is dis-
abled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which
bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn
inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
DQ[63:0],
CB[7:0] IN - Data and Check Bit Input/Output pins.
DM[8:0] IN Active High DM is an input mask signa l for write dat a. Input dat a is masked when DM is sampled High coincident with
that input data during a write access. DM is sampled on both edg es of DQS. Al tho ugh DM p ins are input
only, th e DM loading matches the DQ and DQS loading.
VDD,VSS Supply Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to
VDD/VDDQ planes on these modules.
DQS[17:0] I/OPositive
Edge Positive li ne of the differential data strobe for input and output data
DQS[17:0] I/ONegative
Edge Negative line of the differential dat a strobe for input and output data
SA[2:0] IN - These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD
EEPROM address range.
SDA I/O - This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may be con-
nected from the SDA bus line to VDDSPD on the system planar to act as a pull up.
SCL IN - This signal is used to clock data into and out of the SPD EEPROM. A resi stor may be connected from
SCL to VDDSPD to act as a pull up on the system board.
VDDSPD Supply Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM
supply is operable from 1.7V to 3.6V.
RESET IN The RESET pin is co nnected to the RST pin on the register and to the OE pin on the PLL. Whe n low, all
register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low
level (the PLL will remain synchronized with the input clock)
Par_In IN Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)
Err_Out OUT Parity error found in the Address and Control bus
TEST Used by memory bus analysis tools (unused on memor y DIMMs)
Rev. 0.3 / Oct. 2008 4
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240pin Registered DDR2 SDRAM DIMMs
PIN DESCRIPTION
PIN LOCATION
Pin Pin Description Pin Pin Description
CK0 Clock Input, positive line ODT[1:0] O n Die Termination Inputs
CK0 Clock input, negative line VDDQ DQs Power Supply
CKE0~CKE1 Clock Enable Input DQ0~DQ63 Data Input/Output
RAS Row Address Strobe CB0~CB7 Data check bits Input/Output
CAS Column Address Strobe DQS(0~8) Data strobes
WE Write Enable DQS(0~8) Data strobes, negative line
S0,S1 Chip Select Input DM(0~8),DQS(9~17) Data Maskes/Data strobes
A0~A9,A11~A13 Address input DQS(9~17) Data strobes, negative line
A10/AP Add ress input/Autoprecharge RFU Reserved for Future Use
BA0, BA1, BA2 SDRAM Bank Address NC No Connect
SCL Serial Presence Detect (SPD) Clock Input TEST Memory bus test tool (Not Connect ed and Not
Usable on DIMMs)
SDA SPD Data Input/Output VDD Core Power
SA0~SA2 E2PROM Address Inputs VDDQ I/O Power Supply
Par_In Parity bit for the Address and Control bus VSS Ground
Err_Out Parity error found on the Address VREF Reference Power Supply
RESET Reset Enable VDDSPD Power Supply for SPD
CB0~CB7 Data Strobe Inputs/Outputs
pin #1 Front Side Pin #64 Pin #65 Pin #120
Pin #121 Back Side Pin #184 Pin #185 pin #240
Rev. 0.3 / Oct. 2008 5
1
240pin Registered DDR2 SDRAM DIMMs
PIN ASSIGNMENT
NC= No Connect, RFU= Reserved for Future Use.
Note:
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity.
3. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on norma l memory modules (DIMMs)
Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name
1 VREF 41 VSS 81 DQ33 121 VSS 161 CB4 201 VSS
2 VSS 42 CB0 82 VSS 122 DQ4 162 CB5 202 DM4/DQS13
3 DQ0 43 CB1 83 DQS4 123 DQ5 163 VSS 203 DQS13
4 DQ1 44 VSS 84 DQS4 124 VSS 164 DM8,DQS17 204 VSS
5 VSS 45 DQS8 85 VSS 125 DM0/DQS9 165 DQS17 205 DQ38
6DQS
046DQS886DQ34126DQS9 166 VSS 206 DQ39
7 DQS0 47 VSS 87 DQ35 127 VSS 167 CB6 207 VSS
8 VSS 48 CB2 88 VSS 128 DQ6 168 CB7 208 DQ44
9 DQ2 49 CB3 89 DQ40 129 DQ7 169 VSS 209 DQ45
10 DQ3 50 VSS 90 DQ41 130 VSS 170 VDDQ 210 VSS
11 VSS 51 VDDQ 91 VSS 131 DQ12 171 NC,CKE1 211 DM5/DQS14
12 DQ8 52 CKE0 92 DQS5 132 DQ13 172 VDD 212 DQS14
13 DQ9 53 VDD 93 DQS5 133 VSS 173 A15,NC 213 VSS
14 VSS 54 BA2,NC 94 VSS 134 DM1/DQS10 174 A14,NC 214 DQ46
15 DQS1 55 NC, Err_Out 95 DQ42 135 DQS10 175 VDDQ 215 DQ47
16 DQS1 56 VDDQ 96 DQ43 136 VSS 176 A12 216 VSS
17 VSS 57 A11 97 VSS 137 RFU 177 A9 217 DQ52
18 RESET 58 A7 98 DQ48 138 RFU 178 VDD 218 DQ53
19 NC 59 VDD 99 DQ49 139 VSS 179 A8 219 VSS
20 VSS 60 A5 100 VSS 140 DQ14 180 A6 220 RFU
21 DQ10 61 A4 101 SA2 141 DQ15 181 VDDQ 221 RFU
22 DQ11 62 VDDQ 102 NC(TEST) 142 VSS 182 A3 222 VSS
23 VSS 63 A2 103 VSS 143 DQ20 183 A1 223 DM6/DQS15
24 DQ16 64 VDD 104 DQS6 144 DQ21 184 VDD 224 NC,DQS15
25 DQ17 Key 105 DQS6 145 VSS Key 225 VSS
26 VSS 65 VSS 106 VSS 146 DM2/DQS11 185 CK0 226 DQ54
27 DQS2 66 VSS 107 DQ50 147 DQS11 186 CK0 227 DQ55
28 DQS2 67 VDD 108 DQ51 148 VSS 187 VDD 228 VSS
29 VSS 68 NC, Err_Out 109 VSS 149 DQ22 188 A0 229 DQ60
30 DQ18 69 VDD 110 DQ56 150 DQ23 189 VDD 230 DQ61
31 DQ19 70 A10/AP 111 DQ57 151 VSS 190 BA1 231 VSS
32 VSS 71 BA0 112 VSS 152 DQ28 191 VDDQ 232 DM7/DQS16
33 DQ24 72 VDDQ 113 DQS7 153 DQ29 192 RAS 233 NC,DQS16
34 DQ25 73 WE 114 DQS7 154 VSS 193 S0 234 VSS
35 VSS 74 CAS 115 VSS 155 DM3/DQS12 194 VDDQ 235 DQ62
36 DQS3 75 VDDQ 116 DQ58 156 DQS12 195 ODT0 236 DQ63
37 DQS3 76 NC, S1 117 DQ59 157 VSS 196 A13,NC 237 VSS
38 VSS 77 NC, ODT1 118 VSS 158 DQ30 197 VDD 238 VDDSPD
39 DQ26 78 VDDQ 119 SDA 159 DQ31 198 VSS 239 SA0
40 DQ27 79 VSS 120 SCL 160 VSS 199 DQ36 240 SA1
80 DQ32 200 DQ37
Rev. 0.3 / Oct. 2008 6
1
240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx72): HMP112P7EFR8C
RS0 -> CS: SDRAMs D0-D8S0*
BA0-BA2**
A0-A15**
RAS
CAS
WE
CKE0
ODT1
RESET PCK7
PCK7
RBA-RBA2 -> BA0-BA2: SDRAMs D0-D8
RA0-RA15 -> A0-A15: SDRAMs D0-D8
RRAS -> RAS: SDRAMs D0-D8
RCAS -> CAS: SDRAMs D0-D8
RWE -> WE: SDRAMs D0-D8
RCKE0 -> CKE0: SDRAMs D0-D8
RODT0 -> ODT0: SDRAMs D0-D8
1:2
R
E
G
I
S
T
E
R
RST
Serial PD
WP A0 A1 A2
SA0 SA1 SA2
SCL SDA
RS0
DQS0
DQ0
DQ1
DQ2
I/O 0
I/O 1
I/O 2
I/O 3
CS
D0
DM/ DQS DQS
DQS0
DQ3
Register
PAR_IN QERR
PAR_IN
Err_Out
100KΩ
C1
C0
PPO
VSS
Vss
Signals for Address and Comman d Parity F unction
The resistors on Par_In,A13,A14,A15,BA2 and the
signal line of Err_Out refer to the section:
“Register Options for Unused Address inputs”
D0–D8
D0–D8
VREF
SPD
VDD/VDDQ
V
SS
D0–D8
VDDSPD
Note:
1. DQ-to-I/O wiring may be changed wi th in a nibble.
2. Unless otherwise noted, resistor values are 22 Ohms ±5%.
* S0 connects to DCS of VDD connects to CSR on the register. S1, CKE1 and ODT1 are NC.
** A13-15, BA2 have the optional pull down resistors (100K ohms), which is not indicated here.
DQ4
DQ5
DQ6
I/O 4
I/O 5
I/O 6
I/O 7
DQ7
RDQS NU/
RDQS
DM0/DQS9
DQS9
DQS4
DQ32
DQ33
DQ33
I/O 0
I/O 1
I/O 2
I/O 3
CS
D4
DM/ DQS DQS
DQS4
DQ34
DQ35
DQ36
DQ37
I/O 4
I/O 5
I/O 6
I/O 7
DQ38
RDQS NU/
RDQS
DM4/DQS13
DQS13
DQS1
DQ8
DQ9
DQ10
I/O 0
I/O 1
I/O 2
I/O 3
CS
D1
DM/ DQS DQS
DQS1
DQ11
DQ12
DQ13
DQ14
I/O 4
I/O 5
I/O 6
I/O 7
DQ15
RDQS NU/
RDQS
DM1/DQS10
DQS10
DQS5
DQ40
DQ41
DQ42
I/O 0
I/O 1
I/O 2
I/O 3
CS
D5
DM/ DQS DQS
DQS5
DQ43
DQ44
DQ45
DQ46
I/O 4
I/O 5
I/O 6
I/O 7
DQ47
RDQS NU/
RDQS
DM5/DQS14
DQS14
PCK7 -> CK: Register
PCK7 -> CK: Register
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D8
P
L
L
CK0
CK0
RESET OE
DQS2
DQ16
DQ17
DQ18
I/O 0
I/O 1
I/O 2
I/O 3
CS
D2
DM/ DQS DQS
DQS2
DQ19
DQ20
DQ21
DQ22
I/O 4
I/O 5
I/O 6
I/O 7
DQ23
RDQS NU/
RDQS
DM2/DQS11
DQS11
DQS6
DQ48
DQ49
DQ50
I/O 0
I/O 1
I/O 2
I/O 3
CS
D6
DM/ DQS DQS
DQS6
DQ51
DQ52
DQ53
DQ54
I/O 4
I/O 5
I/O 6
I/O 7
DQ55
RDQS NU/
RDQS
DM6/DQS15
DQS15
DQS3
DQ24
DQ25
DQ26
I/O 0
I/O 1
I/O 2
I/O 3
CS
D3
DM/ DQS DQS
DQS3
DQ27
DQ28
DQ29
DQ30
I/O 4
I/O 5
I/O 6
I/O 7
DQ31
RDQS NU/
RDQS
DM3DQS12
DQS12
DQS7
DQ56
DQ57
DQ58
I/O 0
I/O 1
I/O 2
I/O 3
CS
D7
DM/ DQS DQS
DQS7
DQ59
DQ60
DQ61
DQ62
I/O 4
I/O 5
I/O 6
I/O 7
DQ63
RDQS NU/
RDQS
DM7/DQS16
DQS16
DQS8
CB0
CB1
CB2
I/O 0
I/O 1
I/O 2
I/O 3
CS
D8
DM/ DQS DQS
DQS8
CB3
CB4
CB5
CB6
I/O 4
I/O 5
I/O 6
I/O 7
CB7
RDQS NU/
RDQS
DM8/DQS17
DQS17
Rev. 0.3 / Oct. 2008 7
1
240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
2GB(256Mbx72) : HMP125P7EFR8C
RS1 -> CS: SDRAMs D9-D17S1* RS0 -> CS: SDRAMs D0-D8S0*
BA0-BA2***
A0-A15***
RAS
CAS
WE
CKE0
ODT1
RESET** PCK7**
PCK7**
RBA0-RBA2 -> BA0- BA 2: SD R AM s D0- D17
RA0-RA15 -> A0-A15: SDRAMs D0-D17
RRAS -> RAS: SDRAMs D0-D17
RCAS -> CAS: SDRAMs D0-D17
RWE -> WE: SDRAMs D0-D17
RCKE0 -> CKE0: SDRAMs D0-D8
RODT1 -> ODT0: SDRAMs D9-D17
1:2
R
E
G
I
S
T
E
R
RST
Serial PD
WP A0 A1 A2
SA0 SA1 SA2
SCL SDA
RS0
DQS0
DQ0
DQ1
DQ2
I/O 0
I/O 1
I/O 2
I/O 3
CS
D0
DM/ DQS DQS
DQS0
DQ3
The resistors on Par_In,A13,A14,A15,BA2 and the signal line of Err_Ou t refer to
the section: “Register Options for Unused Address inputs”
D0–D17
D0–D17
VREF
SPD
VDD/VDDQ
V
SS
D0–D17
VDDSPD
* S0 connects to DCS and S1 connects to CSR on Registers. S1 connects to DCS and S0 connects to CSR on another Register.
** RESET, PCK7 and PCK7 connect to both Registers. Other signals connect to one of two Registers.
*** A13-15, BA2 have the optional pull down resistors (100K ohms), which is not indicated here.
DQ4
DQ5
DQ6
I/O 4
I/O 5
I/O 6
I/O 7
DQ7
RDQS NU/
RDQS
DM0/DQS9
DQS9
I/O 0
I/O 1
I/O 2
I/O 3
CS
D9
DM/ DQS DQS
I/O 4
I/O 5
I/O 6
I/O 7
RDQS NU/
RDQS
PCK7 -> CK: Register
PCK7 -> CK: Register
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D17
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D17
P
L
L
CK0
CK0
RESET OE
RS1
Register A
PAR_IN QERR
PAR_IN
Err_Out
100KΩ
C1
C0
PPO
VDD
Vss
Signals for Address and Command Parity Function
Register B
PAR_IN QERR
C1
C0
PPO
VDD
VDD
DQS1
DQ8
DQ9
DQ10
I/O 0
I/O 1
I/O 2
I/O 3
CS
D1
DM/ DQS DQS
DQS1
DQ11
DQ12
DQ13
DQ14
I/O 4
I/O 5
I/O 6
I/O 7
DQ15
RDQS NU/
RDQS
DM1/DQS10
DQS10
I/O 0
I/O 1
I/O 2
I/O 3
CS
D10
DM/ DQS DQS
I/O 4
I/O 5
I/O 6
I/O 7
RDQS NU/
RDQS
DQS2
DQ16
DQ17
DQ18
I/O 0
I/O 1
I/O 2
I/O 3
CS
D2
DM/ DQS DQS
DQS2
DQ19
DQ20
DQ21
DQ22
I/O 4
I/O 5
I/O 6
I/O 7
DQ23
RDQS NU/
RDQS
DM2/DQS11
DQS11
I/O 0
I/O 1
I/O 2
I/O 3
CS
D11
DM/ DQS DQS
I/O 4
I/O 5
I/O 6
I/O 7
RDQS NU/
RDQS
DQS3
DQ24
DQ25
DQ26
I/O 0
I/O 1
I/O 2
I/O 3
CS
D3
DM/ DQS DQS
DQS3
DQ27
DQ28
DQ29
DQ30
I/O 4
I/O 5
I/O 6
I/O 7
DQ31
RDQS NU/
RDQS
DM3/DQS12
DQS12
I/O 0
I/O 1
I/O 2
I/O 3
CS
D12
DM/ DQS DQS
I/O 4
I/O 5
I/O 6
I/O 7
RDQS NU/
RDQS
DQS8
CB0
CB1
CB2
I/O 0
I/O 1
I/O 2
I/O 3
CS
D8
DM/ DQS DQS
DQS8
CB3
CB4
CB5
CB6
I/O 4
I/O 5
I/O 6
I/O 7
CB7
RDQS NU/
RDQS
DM8DQS17
DQS17
I/O 0
I/O 1
I/O 2
I/O 3
CS
D17
DM/ DQS DQS
I/O 4
I/O 5
I/O 6
I/O 7
RDQS NU/
RDQS
DQS4
DQ32
DQ33
DQ34
I/O 0
I/O 1
I/O 2
I/O 3
CS
D4
DM/ DQS DQS
DQS4
DQ35
DQ36
DQ37
DQ38
I/O 4
I/O 5
I/O 6
I/O 7
DQ39
RDQS NU/
RDQS
DM4/DQS13
DQS13
I/O 0
I/O 1
I/O 2
I/O 3
CS
D13
DM/ DQS DQS
I/O 4
I/O 5
I/O 6
I/O 7
RDQS NU/
RDQS
DQS5
DQ40
DQ41
DQ42
I/O 0
I/O 1
I/O 2
I/O 3
CS
D5
DM/ DQS DQS
DQS5
DQ43
DQ40
DQ41
DQ42
I/O 4
I/O 5
I/O 6
I/O 7
DQ43
RDQS NU/
RDQS
DM5/DQS14
DQS14
I/O 0
I/O 1
I/O 2
I/O 3
CS
D14
DM/ DQS DQS
I/O 4
I/O 5
I/O 6
I/O 7
RDQS NU/
RDQS
DQS6
DQ48
DQ49
DQ50
I/O 0
I/O 1
I/O 2
I/O 3
CS
D6
DM/ DQS DQS
DQS6
DQ51
DQ52
DQ53
DQ54
I/O 4
I/O 5
I/O 6
I/O 7
DQ55
RDQS NU/
RDQS
DM6/DQS15
DQS15
I/O 0
I/O 1
I/O 2
I/O 3
CS
D15
DM/ DQS DQS
I/O 4
I/O 5
I/O 6
I/O 7
RDQS NU/
RDQS
DQS7
DQ56
DQ57
DQ58
I/O 0
I/O 1
I/O 2
I/O 3
CS
D7
DM/ DQS DQS
DQS7
DQ59
DQ60
DQ61
DQ62
I/O 4
I/O 5
I/O 6
I/O 7
DQ63
RDQS NU/
RDQS
DM7/DQS16
DQS16
I/O 0
I/O 1
I/O 2
I/O 3
CS
D16
DM/ DQS DQS
I/O 4
I/O 5
I/O 6
I/O 7
RDQS NU/
RDQS
CKE1 RCKE1 -> CKE0: SDRAMs D9-D17
R
ODT0 RODT0 -> ODT0: SDRAMs D0-D8 Note:
1. DQ-to-I/O wiring may be changed within a byte.
2. Unless otherwise noted, resistor values are 22 Ohms ±5%.
3. RS0 and RS1 alternate between the back and front sides of th e DIMM.
Rev. 0.3 / Oct. 2008 8
1
240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
2GB(256Mbx72): HMP125P7EFR4C
RS0 -> CS: SDRAMs D0-D17S0*
BA0-BA2***
A0-A15***
RAS
CAS
WE
CKE0
ODT1
RESET** PCK7**
PCK7**
RBA-RBA2 -> BA0-BA2: SDRAMs D0-D17
RA0-RA15 -> A0-A15: SDRAMs D0-D17
RRAS -> RAS: SDRAMs D0-D17
RCAS -> CAS: SDRAMs D0-D17
RWE -> WE: SDRAMs D0-D17
RCKE0 -> CKE0: SDRAMs D0-D17
RODT0 -> ODT0: SDRAMs D0-D17
1:2
R
E
G
I
S
T
E
R
RST
Serial PD
WP A0 A1 A2
SA0 SA1SA2
SCL SDA
RS0
DQS0
DQ0
DQ1
DQ2
I/O 0
I/O 1
I/O 2
I/O 3
CS
D0
DM DQS DQS
DQS0
I/O 0
I/O 1
I/O 2
I/O 3
CS
D9
DM DQS DQS
DQ3
DQS9
DQS9
DQ4
DQ5
DQ6
DQ7
VSS
DQS1
DQ8
DQ9
DQ10
I/O 0
I/O 1
I/O 2
I/O 3
CS
D1
DM DQS DQS
DQS1
I/O 0
I/O 1
I/O 2
I/O 3
CS
D10
DM DQS DQS
DQ11
DQS9
DQS9
DQ12
DQ13
DQ14
DQ15
DQS2
DQ16
DQ17
DQ18
I/O 0
I/O 1
I/O 2
I/O 3
CS
D2
DM DQS DQS
DQS2
I/O 0
I/O 1
I/O 2
I/O 3
CS
D11
DM DQS DQS
DQ19
DQS11
DQS11
DQ20
DQ21
DQ22
DQ23
DQS3
DQ24
DQ25
DQ26
I/O 0
I/O 1
I/O 2
I/O 3
CS
D3
DM DQS DQS
DQS3
I/O 0
I/O 1
I/O 2
I/O 3
CS
D12
DM DQS DQS
DQ27
DQS12
DQS12
DQ28
DQ29
DQ30
DQ31
DQS4
DQ32
DQ33
DQ34
I/O 0
I/O 1
I/O 2
I/O 3
CS
D4
DM DQS DQS
DQS4
I/O 0
I/O 1
I/O 2
I/O 3
CS
D13
DM DQS DQS
DQ35
DQS13
DQS13
DQ36
DQ37
DQ38
DQ39
DQS5
DQ40
DQ41
DQ42
I/O 0
I/O 1
I/O 2
I/O 3
CS
D5
DM DQS DQS
DQS5
I/O 0
I/O 1
I/O 2
I/O 3
CS
D14
DM DQS DQS
DQ43
DQS14
DQS14
DQ44
DQ45
DQ46
DQ47
DQS6
DQ48
DQ49
DQ50
I/O 0
I/O 1
I/O 2
I/O 3
CS
D6
DM DQS DQS
DQS6
I/O 0
I/O 1
I/O 2
I/O 3
CS
D15
DM DQS DQS
DQ51
DQS15
DQS15
DQ52
DQ53
DQ54
DQ55
DQS7
DQ56
DQ57
DQ58
I/O 0
I/O 1
I/O 2
I/O 3
CS
D7
DM DQS DQS
DQS7
I/O 0
I/O 1
I/O 2
I/O 3
CS
D16
DM DQS DQS
DQ59
DQS16
DQS16
DQ60
DQ61
DQ62
DQ63
DQS8
CB0
CB1
CB2
I/O 0
I/O 1
I/O 2
I/O 3
CS
D8
DM DQS DQS
DQS8
I/O 0
I/O 1
I/O 2
I/O 3
CS
D17
DM DQS DQS
CB3
DQS17
DQS17
CB4
CB5
CB6
CB7
Register A
PAR_IN QERR
PAR_IN
Err_Out
100KΩ
C1
C0
PPO
VDD
Vss
Signals for Address and Command Parity Function
Register B
PAR_IN QERR
C1
C0
PPO
VDD
VDD
The resistors on Par_In,A13,A14,A15,BA2 and the signal line of Err_Out refer to
the section:
“Register Options for Unused Address inputs”
D0–D17
D0–D17
VREF
SPD
VDD/VDDQ
V
SS
D0–D17
VDDSPD
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resistor values are 22 Ohms ±5%.
* S0 connects to DCS of Register A and CSR of Register B.
CSR of Register A and DCS of Register B connects to VDD.
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect
to one of two Registers.
*** A13-15, BA2 have the optional pull down resistors (100K ohms), which is
not indicated here.
PCK7 -> CK: Register
PCK7 -> CK: Register
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D17
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D1 7
P
L
L
CK0
CK0
RESET OE
Rev. 0.3 / Oct. 2008 9
1
240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
4GB(512Mbx72) : HMP151P7EFR8C
RDOT0
RCKE0
RS0
DQS0
DQS0
DQ7-0
DM0
DQS
DQS
DQ7-0
DM
CS
D0
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D9
CKE
ODT
RS1
DQS1
DQS1
DQ15-8
DM1
DQS
DQS
DQ7-0
DM
CS
D1
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D10
CKE
ODT
DQS2
DQS2
DQ23-16
DM2
DQS
DQS
DQ7-0
DM
CS
D2
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D11
CKE
ODT
DQS3
DQS3
DQ31-24
DM3
DQS
DQS
DQ7-0
DM
CS
D3
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D12
CKE
ODT
DQS4
DQS4
CB7-0
DM8
DQS
DQS
DQ7-0
DM
CS
D4
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D13
CKE
ODT
DQS4
DQS4
DQ39-32
DM4
DQS
DQS
DQ7-0
DM
CS
D5
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D14
CKE
ODT
DQS5
DQS5
DQ47-40
DM5
DQS
DQS
DQ7-0
DM
CS
D6
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D15
CKE
ODT
DQS6
DQS6
DQ55-48
DM6
DQS
DQS
DQ7-0
DM
CS
D7
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D16
CKE
ODT
DQS7
DQS7
DQ63-56
DM7
DQS
DQS
DQ7-0
DM
CS
D8
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D17
CKE
ODT
RDOT1
RCKE1
RS2
DQS
DQS
DQ7-0
DM
CS
D18
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D27
CKE
ODT
RS3
DQS
DQS
DQ7-0
DM
CS
D19
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D28
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D20
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D29
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D21
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D30
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D22
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D31
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D23
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D32
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D24
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D33
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D25
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D34
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D26
CKE
ODT
DQS
DQS
DQ7-0
DM
CS
D35
CKE
ODT
Serial PD
WP A0 A1 A2
SA0 SA1SA2
SCL SDA
D0–D35
D0–D35
VREF
SPD
VDD/VDDQ
V
SS
D0–D35
VDDSPD
PCK7 -> CK: Register
PCK7 -> CK: Register
PCK0-PCK6, PCK8,PCK9
PCK0-PCK6, PCK8, PCK9
P
L
L
CK0
CK0
RESET OE
-> CK: SDRAMs D0-D35
-> CK: SDRAMs D0-D35
RS0 -> CS: SDRAMs D0-D8, RS2 -> CS: SDRAMs D18-D26S0,S2*
S1,S3*
BA0-BA2***
A0-A15***
RAS
CAS
WE
CKE0
CKE1
ODT1
ODT0
RESET** PCK7**
PCK7**
RS1 -> CS: SDRAMs D9-D17,RS3 -> CS: SDRAMs D27-D35
RBA0-RBA2 -> BA0-BA2: SDRAMs D0-D35****
RA0-RA15 -> A0-A15: SDRAMs D0-D35****
RRAS -> RAS: SDRAMs D0-D3 5
RCAS -> CAS: SDRAMs D0-D3 5
RWE -> WE: SDRAMs D0-D35
RCKE0 -> CKE: SDRAMs D0-D17
RCKE1 -> CKE: SDRAMs D18-D35
RODT0 -> ODT0: SDRAMs D0-D8
RODT1 -> ODT1: SDRAMs D18-D26
1:2
R
E
G
I
S
T
E
R
RST
Register A2
PAR_IN QERR
Err_Out
C1
C0
PPO
VDD
Vss
Signals for Address and Command
Register B2
PAR_IN QERR
C1
C0
PPO
VDD
VDD
Register A1
PAR_IN QERR
C1
C0
PPO
VDD
Vss
Register B1
PAR_IN QERR
C1
C0
PPO
VDD
VDD
Parity Function
Register A1 and A2 share the a part of
Addr/Cmd input signal set.
Register B1 and B2 ch are the rest part of
Addr/Cmd input signal set.
The resistors on Par_In, A13, A14. A15,B A2 and
the signal line of Err_Out refer to the section:
The egister Options for Unused Address inputs?
* S0 (S2) connects to DCS0, S1 (S 3) to DCS1 on a Regi ster A. S1 (S3) connects to DCS and S0 (S2) connects to CSR on another pair of Register.
* S2 and S3 have required upll up resistors (100k ohms), not indicated here.
** RESET, PCK7 and PCK7 connect to all Registers. Other signals connect to two of four Registers.
*** A13-15, BA2 have the optional pull down resistors(100K ohms), which is not indicated here.
**** For Raw Card N2, DQ stub resistor value is TBD.
And for Raw Card N2, post register A14 and A15 are not connected to the SDRAMs.
Rev. 0.3 / Oct. 2008 10
1
240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
4GB(512Mbx72): HMP151P7EFR4C
VSS
RS0
RS1
DQS0
DQ0
DQ1
DQ2
I/O 0
I/O 1
I/O 2
I/O 3
CS
D18
RS0 -> CS: SDRAMs D0-D17S0*
S1*
BA0-BA2***
A0-A15***
RAS
CAS
WE
CKE0
CKE1
ODT1
ODT0
RESET** PCK7**
PCK7**
RS1 -> CS: SDRAMs D18-D35
RBA0-RBA2 -> BA0- BA 2: SD R AM s D0- D35
RA0-RA15 -> A0-A15: SDRAMs D0-D35
RRAS -> RAS: SDRAMs D0-D35
RCAS -> CAS: SDRAMs D0-D35
RWE -> WE: SDRAMs D0-D35
RCKE0 -> CKE0-1: SDRAMs D0-D17
RCKE1 -> CKE0-1: SDRAMs D18-D35
RODT0 -> ODT1: SDRAMs D0-D17
RODT1 -> ODT1: SDRAMs D18-D35
*S0 connects to DCS and S1 command to CRS on a pair of Register, S2 connects to DCS and S0 connect to CRS on another pair of Register.
** RESET, PCK7 an d PCK7 connect to all Registers. Other signals connect to one pair of four Registers.
*** A14-15, BA2 have the optional pull down resistors (100K ohms), which is not indicated here.
1:2
R
E
G
I
S
T
E
R
PCK7 -> CK: Register
PCK7 -> CK: Register
PCK0-PCK6, PCK8, PCK9 -> CK : SDRAMs D0-D35
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D35
P
L
L
RST
CK0
CK0
RESET OE
Register
Register
PARIN PTYERR
PARIN PTYERR
Par_In
Err_Out
Serial PD
WP A0 A1 A2
SA0 SA1SA2
SCL SDA
100KΩ
0Ω
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D0
DM DQS DQS
DQS0
I/O 0
I/O 1
I/O 2
I/O 3
CS
D27
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D9
DM DQS DQS
DQ3
DQS9
DQS9
DQ4
DQ5
DQ6
DQ7
DQS1
DQ8
DQ9
DQ10
I/O 0
I/O 1
I/O 2
I/O 3
CS
D19
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D1
DM DQS DQS
DQS1
I/O 0
I/O 1
I/O 2
I/O 3
CS
D28
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D10
DM DQS DQS
DQ11
DQS10
DQS10
DQ12
DQ13
DQ14
DQ15
DQS2
DQ16
DQ17
DQ18
I/O 0
I/O 1
I/O 2
I/O 3
CS
D20
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D2
DM DQS DQS
DQS2
I/O 0
I/O 1
I/O 2
I/O 3
CS
D29
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D11
DM DQS DQS
DQ19
DQS11
DQS11
DQ20
DQ21
DQ22
DQ23
DQS3
DQ24
DQ25
DQ26
I/O 0
I/O 1
I/O 2
I/O 3
CS
D21
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D3
DM DQS DQS
DQS3
I/O 0
I/O 1
I/O 2
I/O 3
CS
D30
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D12
DM DQS DQS
DQ27
DQS12
DQS12
DQ28
DQ29
DQ30
DQ30
DQS8 DQS17
RS0
RS1
DQS4
DQ32
DQ33
DQ34
I/O 0
I/O 1
I/O 2
I/O 3
CS
D22
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D4
DM DQS DQS
DQS4
I/O 0
I/O 1
I/O 2
I/O 3
CS
D31
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D13
DM DQS DQS
DQ35
DQS13
DQS13
DQ36
DQ37
DQ38
DQ39
DQS5
DQ40
DQ41
DQ42
I/O 0
I/O 1
I/O 2
I/O 3
CS
D23
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D5
DM DQS DQS
DQS5
I/O 0
I/O 1
I/O 2
I/O 3
CS
D32
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D14
DM DQS DQS
DQ43
DQS14
DQS14
DQ44
DQ45
DQ46
DQ47
DQS6
DQ48
DQ49
DQ50
I/O 0
I/O 1
I/O 2
I/O 3
CS
D24
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D6
DM DQS DQS
DQS6
I/O 0
I/O 1
I/O 2
I/O 3
CS
D33
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D15
DM DQS DQS
DQ51
DQS15
DQS15
DQ52
DQ53
DQ54
DQ55
DQS7
DQ56
DQ57
DQ58
I/O 0
I/O 1
I/O 2
I/O 3
CS
D25
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D7
DM DQS DQS
DQS7
I/O 0
I/O 1
I/O 2
I/O 3
CS
D34
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D16
DM DQS DQS
DQ59
DQS16
DQS16
DQ60
DQ61
DQ62
DQ63
Note:
1. DQ-to-I/O wiring may be c hanged within a nibble.
2. Unless otherwise noted, resistor values are 22 Ohms ±5%.
3. RS0 and RS1 alternate between the bottom and surface sides of the DIMM.
CB0
CB1
CB2
I/O 0
I/O 1
I/O 2
I/O 3
CS
D26
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D8
DM DQS DQS
DQS8
I/O 0
I/O 1
I/O 2
I/O 3
CS
D35
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D17
DM DQS DQS
CB3
DQS17
CB4
CB5
CB6
CB7
Signals for Address and Command
Parity Function
o ohm resis tor on E rr_Out is not populated
for non-parity card.
The resistors on Par_In ,A13,A14, A15,BA 2
and the signal line of Err_Out refer to the
section:
“Register Options fo r Unused Address
input”
D0–D35
D0–D35
VREF
SPD
VDD/VDDQ
V
SS
D0–D35
VDDSPD
Rev. 0.3 / Oct. 2008 11
1
240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
8GB(1Gbx72): HMP31GP7EFR4C
RODT0
RCKE0
RS1
RS0
RODT1
RCKE1
RS3
RS2
RODT0
RCKE0
RS1
RS0
RODT1
RCKE1
RS3
RS2
RODT0
RCKE0
RS1
RS0
RODT1
RCKE1
RS3
RS2
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D0
DQS0
DQS0
DQ3~0
RODT0
RCKE0
RS1
RS0
RODT1
RCKE1
RS3
RS2
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D1
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D2
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D3
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D8
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D18
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D19
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D20
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D21
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D26
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D9
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D10
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D11
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D12
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D17
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D27
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D28
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D29
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D35
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D30
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D4
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D7
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D22
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D23
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D24
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D25
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D13
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D14
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D15
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D16
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D31
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D32
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D33
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D34
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D5
DQS
DQS
DQ3~0
DM
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D6
DQS1
DQS1
DQ11~8
DQS2
DQS2
DQ19~26
DQS3
DQS3
DQ27~24
DQS8
DQS8
CB3~0
DQS9
DQS9
DQ7~4
DQS10
DQS10
DQ15~12
DQS11
DQS11
DQ23~20
DQS12
DQS12
DQ31~28
DQS17
DQS17
CB7~4
DQS4
DQS4
DQ35~32
DQS5
DQS5
DQ43~40
DQS
DQS6
DQ51~48
DQS7
DQS7
DQ59~56
DQS13
DQS13
DQ39~36
DQS14
DQS14
DQ47~44
DQS15
DQS15
DQ55~52
DQS16
DQS16
DQ63~60
DQS
DQS
DQ3~0
CS0
CS1
CKE0
CKE1
ODT0
ODT1
D0
DM
RS0 -> CS0: SDRAMs D0-D17, RS2 -> CS0: SDRAMs D18-D35S0,2*
S1,3**
BA0-BA2***
A0-A15***
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
RESET PCK7
PCK7
RS1 -> CS1: SDRAMs D0-D17, RS3 -> CS1: SDRAMs D18-D35
RBA-RBA2 -> BA0-BA1: SDRAMs D0-D35
RA0-RA13 -> A0-A13: SDRAMs D0-D35
RRAS -> RAS: SDRAMs D0-D35
RCAS -> CAS: SDRAMs D0-D35
RWE -> WE: SDRAMs D0-D35
RCKE0 -> CKE0-1: SDRAMs D0-D17
RCKE1 -> CKE0-1: SDRAMs D18-D35
RODT0 -> ODT1: SDRAMs D0-D17
RODT1 -> ODT1: SDRAMs D18-D35
*S0 connects to DCS0, S1 to DCS1 on the first register, S2 connects to DCS0, S3 to DCS1 on the second register.
** S2 and S3 have required pull up resistors (100K ohms), not indicated here.
*** A13-15, BA2 have optional pull down resistors (100K ohms), not indicated here.
1:2
R
E
G
I
S
T
E
R
PCK7 -> CK: Register
PCK7 -> CK: Register
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D35
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D35
P
L
L
RST
CK0
CK0
RESET OE
Register
Register
PARIN PTYERR
PARIN PTYERR
PAR_IN ERR_OUT
Serial PD
WP A0 A1 A2
SA0 SA1 SA2
SCL SDA
100KΩ
0Ω 0Ω
22Ω
22Ω
22Ω
Rev. 0.3 / Oct. 2008 12
1
240pin Registered DDR2 SDRAM DIMMs
ABSOLUTE MAXIMUM DC RATINGS
Operating Conditions and Environmental Parameters
Note:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con
ditions for extended periods may affect reliablility.
2. Up to 9850 ft.
3. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to
tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
DC OPERATING CONDITIONS (SSTL_1.8)
Note:
1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option.
2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD .
3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is
expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).
5. VTT of transmitting device must track VREF of receiving device.
Parameter Symbol Value Unit Note
Voltage on VDD pin relative to Vss VDD - 1.0 ~ 2.3 V 1
Voltage on VDDQ pin relative to Vss VDDQ - 0.5 ~ 2.3 V 1
Voltage on VDDL pin relative to Vss VDDL - 0.5 ~ 2.3 V 1
Voltage on any pin relative to Vss VIN, VOUT - 0.5 ~ 2.3 V 1
Parameter Symbol Rating Units Notes
DIMM Ope r a ti n g te m p erature (a m bi e nt ) TOPR 0 ~ +55 oC
Storage Temperature TSTG -50 ~ +100 oC1
Storage Humidity (without condensation) HSTG 5 to 95 % 1
DIMM Barometric Pressure (operating & storage) PBAR 105 to 69 K Pascal 2
DRAM Component Case Temperature Range TCASE 0 ~+95 oC3
Symbol Parameter Rating Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.7 1.8 1.9 V 1
VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 1,2
VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 1,2
VREF Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 3,4
VTT Termination Voltage VREF-0.04 VREF VREF+0.04 V 5
VDDSPD EEPROM Supply Voltage 1.7 - 3.6 V
Rev. 0.3 / Oct. 2008 13
1
240pin Registered DDR2 SDRAM DIMMs
INPUT DC LOGIC LEVEL
INPUT AC LOGIC LEVEL
AC INPUT TEST CONDITIONS
Note:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF max to VIH(ac) min for rising edges and the
range from VREF min to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL (ac) to VIH (ac) on the positive transitions and VIH (ac) to
VIL (ac) on the negative transitions.
Parameter Symbol Min Max Unit Note
dc Input logic HIGH VIH(DC) VREF + 0.125 VDDQ + 0.3 V
dc Input logic LOW VIL(DC) -0.30 VREF - 0.125 V
Parameter Symbol DDR2 400/533 DDR2 667/800 Unit Notes
Min Max Min Max
ac Input logic HIGH VIH(AC) VREF + 0.250 - VREF + 0.200 - V
ac Input logic LOW VIL(AC) -V
REF - 0.250 - VREF - 0.200 V
Symbol Condition Value Units Notes
VREF Input reference voltage 0.5 * VDDQ V1
VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1
SLEW Input signa l mini mu m slew r ate 1.0 V/ns 2, 3
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
< Figure: AC Input Test Signal Waveform >
V
SWING(MAX)
∆
TR
∆
TF
Start of Falling Edge Input Timing Start of Rising Edge Input Timing
V
REF
-
VIL
(ac)
max
∆
TF
Falling Slew = Rising Slew = V
IH(ac)
min - V
REF
∆
TR
Rev. 0.3 / Oct. 2008 14
1
240pin Registered DDR2 SDRAM DIMMs
Differential Input AC logic Level
Note:
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,
LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS
or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to
VIH(DC) - VIL(DC).
Note:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).
The minimum value is equal to V IH(AC) - VIL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in
VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross.
DIFFERENTIAL AC OUTPUT PARAMETERS
Note:
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations
in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross.
Symbol Parameter Min. Max. Units Note
VID (ac) ac differential input voltage 0.5 VDDQ + 0.6 V 1
VIX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2
Symbol Parameter Min. Max. Units Note
VOX (ac) ac differential crosspoint voltage 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1
VDDQ
Crossing point
VSSQ
VTR
VCP
VID VIX or VOX
< Differential signal levels >
Rev. 0.3 / Oct. 2008 15
1
240pin Registered DDR2 SDRAM DIMMs
OUTPUT BUFFER LEVELS
OUTPUT AC TEST CONDITIONS
Note:
1. The VDDQ of the device under test is referenced.
OUTPUT DC CURRENT DRIVE
Note:
1.VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capa-
bility to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual cur-
rent values are derived by shifting the desired driver operating point along a 21 ohm l oad line to define a convenient driver current for
measurement.
Symbol Parameter SSTL_18 Units Notes
VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V1
Symbol Parameter SSTl_18 Units Notes
IOH(dc) Output Minimum Source DC Current - 13.4 mA 1, 3, 4
IOL(dc) Output Minimum Sink DC Current 13.4 mA 2, 3, 4
Rev. 0.3 / Oct. 2008 16
1
240pin Registered DDR2 SDRAM DIMMs
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25°C)
1GB: HMP112 P7EFR8C
2GB: HMP125P7EFR8C
2GB: HMP125P7EFR4C
4GB: HMP151P7EFR8C
Pin Symbol Min Max Unit
CK0, /CK0CCK711pF
CKE, ODT CI1 8 12 pF
/CS CI2 8 12 pF
Address, /RAS, /CAS, /WE CI3 8 12 pF
DQ, DM, DQS, /DQS CIO 6 9 pF
Pin Symbol Min Max Unit
CK0, /CK0CCK711pF
CKE, ODT CI1 8 12 pF
/CS CI2 10 15 pF
Address, /RAS, /CAS, /WE CI3 8 12 pF
DQ, DM, DQS, /DQS CIO 6 9 pF
Pin Symbol Min Max Unit
CK0, /CK0CCK711pF
CKE, ODT CI1 8 12 pF
/CS CI2 10 15 pF
Address, /RAS, /CAS, /WE CI3 8 12 pF
DQ, DM, DQS, /DQS CIO 6 9 pF
Pin Symbol Min Max Unit
CK0, /CK0CCK711pF
CKE, ODT CI1 10 15 pF
/CS CI2 10 15 pF
Address, /RAS, /CAS, /WE CI3 10 15 pF
DQ, DM, DQS, /DQS CIO 9 15 pF
Rev. 0.3 / Oct. 2008 17
1
240pin Registered DDR2 SDRAM DIMMs
4GB: HMP151P7EFR4C
8GB: HMP31GP7EMR4C
Note:
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
Pin Symbol Min Max Unit
CK0, /CK0CCK711pF
CKE, ODT CI1 10 15 pF
/CS CI2 10 15 pF
Address, /RAS, /CAS, /WE CI3 10 15 pF
DQ, DM, DQS, /DQS CIO 9 15 pF
Pin Symbol Min Max Unit
CK0, /CK0CCK711pF
CKE, ODT CI1 8 12 pF
/CS CI2 8 12 pF
Address, /RAS, /CAS, /WE CI3 10 15 pF
DQ, DM, DQS, /DQS CIO 18 22 pF
Rev. 0.3 / Oct. 2008 18
1
240pin Registered DDR2 SDRAM DIMMs
IDD SPECIFICATIONS (TCASE: 0 to 95oC)
1GB, 128M x 72 Registered DIMM: HMP112P7EFR8C
2GB, 256M x 72 Registered DIMM: HMP125P7EFR8C
Symbol C4
(DDR2 533@CL4) Y5
(DDR2 667@CL5) S5 /S6
(DDR2 800@CL5&6) Unit Note
IDD0 1235 1280 1325 mA
IDD1 1325 1370 1415 mA
IDD2P 740 740 740 mA
IDD2Q 893 920 938 mA
IDD2N 965 1010 1055 mA
IDD3P(F) 875 875 875 mA
IDD3P(S) 758 758 758 mA
IDD3N 1055 1100 1145 mA
IDD4R 1730 1910 2090 mA
IDD4W 1730 1955 2180 mA
IDD5B 2090 2135 2180 mA
IDD6 540 540 540 mA 1
IDD7 2225 2405 2720 mA
Symbol C4
(DDR2 533@CL4) Y5
(DDR2 667@CL5) S5 /S6
(DDR2 800@CL5&6) Unit Note
IDD0 1550 1640 1730 mA
IDD1 1640 1730 1820 mA
IDD2P 830 830 830 mA
IDD2Q 1136 1190 1226 mA
IDD2N 1280 1370 1460 mA
IDD3P(F) 1100 1100 1100 mA
IDD3P(S) 866 866 866 mA
IDD3N 1460 1550 1640 mA
IDD4R 2045 2270 2495 mA
IDD4W 2045 2315 2585 mA
IDD5B 1405 2495 1585 mA
IDD6 630 630 630 mA 1
IDD7 2675 2765 3125 mA
Rev. 0.3 / Oct. 2008 19
1
240pin Registered DDR2 SDRAM DIMMs
2GB, 256M x 72 Registered DIMM: HMP125P7EFR4C
4GB, 512M x 72 Registered DIMM: HMP151P7EFR8C
Symbol C4
(DDR2 533@CL4) Y5
(DDR2 667@CL5) S5 /S6
(DDR2 800@CL5&6) Unit Note
IDD0 1280 1910 2000 mA
IDD1 2000 2090 2180 mA
IDD2P 830 830 830 mA
IDD2Q 1136 1190 1226 mA
IDD2N 1280 1370 1460 mA
IDD3P(F) 1100 1100 1100 mA
IDD3P(S) 866 866 866 mA
IDD3N 1460 1550 1640 mA
IDD4R 2810 3170 3530 mA
IDD4W 2810 3260 3710 mA
IDD5B 3330 3420 3510 mA
IDD6 630 630 630 mA 1
IDD7 4070 4160 4790 mA
Symbol C4
(DDR2 533@CL4) Y5
(DDR2 667@CL5) S5 /S6
(DDR2 800@CL5&6) Unit Note
IDD0 2180 2360 2540 mA
IDD1 2270 2450 2630 mA
IDD2P 690 690 690 mA
IDD2Q 758 770 778 mA
IDD2N 790 810 830 mA
IDD3P(F) 750 750 750 mA
IDD3P(S) 698 698 698 mA
IDD3N 830 850 870 mA
IDD4R 2675 2290 3305 mA
IDD4W 2675 3035 3395 mA
IDD5B 5420 5780 6140 mA
IDD6 490 490 490 mA 1
IDD7 3305 3485 3935 mA
Rev. 0.3 / Oct. 2008 20
1
240pin Registered DDR2 SDRAM DIMMs
4GB, 512M x 72 Registered DIMM: HMP151P7EFR4C
8GB, 1G x 72 Registered DIMM: HMP31GP7EMR4C
Note: 1. IDD6 current values are guaranteed up to Tcase of 85°C max.
Symbol C4
(DDR2 533@CL4) Y5
(DDR2 667@CL5) S5 /S6
(DDR2 800@CL5&6) Unit Note
IDD0 2450 2630 2810 mA
IDD1 2630 2810 2990 mA
IDD2P 1010 1010 1010 mA
IDD2Q 1622 1730 1802 mA
IDD2N 1910 2090 2270 mA
IDD3P(F) 1550 1550 1550 mA
IDD3P(S) 1082 1082 1082 mA
IDD3N 2270 2450 2630 mA
IDD4R 3440 3890 4340 mA
IDD4W 3440 3980 4520 mA
IDD5B 3960 4140 4320 mA
IDD6 810 810 810 mA 1
IDD7 4430 4880 5600 mA
Symbol C4
(DDR2 533@CL4) Y5
(DDR2 667@CL5) Unit Note
IDD0 3710 4070 mA
IDD1 3890 4250 mA
IDD2P 690 690 mA
IDD2Q 758 770 mA
IDD2N 790 810 mA
IDD3P(F) 750 750 mA
IDD3P(S) 698 698 mA
IDD3N 830 850 mA
IDD4R 4700 5330 mA
IDD4W 4700 5420 mA
IDD5B 5220 5580 mA
IDD6 490 490 mA
IDD7 5690 6320 mA
Rev. 0.3 / Oct. 2008 21
1
240pin Registered DDR2 SDRAM DIMMs
IDD Measurement Conditions
Note:
1. IDD specifications are tested after the device is properly initiali zed
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bu s con s ists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations
of EMRS bits 10 and 11 .
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC (max)
HIGH is defined as Vin ≥ VIHAC (min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and con-
trol signals, and inputs changing between HIGH and LOW eve ry other data transfer (once per clock) for DQ signals not including
masks or strobes
Symbol Conditions Units
IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin
(IDD);CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING mA
IDD1 Operating one bank active-read-precharge current; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin (IDD), tRCD = tRC D(IDD); CKE is HIGH, CS is HIGH
between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA
IDD2P Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING mA
IDD2Q Precharge quiet standby current; All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING mA
IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA
IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Fast PDN Exit MRS(12) = 0 mA
Slow PDN Exit MRS(12) = 1 mA
IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP =tRP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data
bus inputs are SWITCHING mA
IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK =
tCK(IDD), tRAS = tRASmax (IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA
IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
AL = 0; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA
IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING mA
IDD6 Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85℃ max. mA
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL
= tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pat-
tern is same as IDD4R; - Refer to the following page for detailed timing conditions
mA
Rev. 0.3 / Oct. 2008 22
1
240pin Registered DDR2 SDRAM DIMMs
Electrical Characteristics & AC Timings
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
AC Timing Parameters by Speed Grade (DDR2-400 & DDR2-533)
Speed DDR2-800 (S5) DDR2-667 (Y5) DDR2-533 (C4) Unit
Bin (CL-tRCD-tRP) 5-5-5 5-5-5 4-4-4
Parameter min min min
CAS Latency 554ns
tRCD 12.5 15 15 ns
tRP 12.5 15 15 ns
tRC 57.5 60 60 ns
tRAS 45 45 45 ns
Parameter Symbol DDR2-400 DDR2-533 Unit Note
Min Max Min Max
Data-Out edge to Cl ock edge Skew tAC -600 600 -500 500 ps
DQS-Out edge to Clock edge Skew tDQSCK -500 500 -500 450 ns
Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK
Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK
Clock Half Period tHP min
(tCL, tCH) -min
(tCL, tCH) -ns
System Clock Cycle Time tCK 5000 8000 3750 8000 ps
DQ and DM input setup time tDS 150 - 100 - ps 1
DQ and DM input hold time tDH 275 - 225 - ps 1
Control & Address input Pulse Width for each input tIPW 0.6 - 0.6 - tCK
DQ and DM input pulse wid th for each input pulse widt h for
each input tDIPW 0.35 - 0.35 - tCK
Data-out high-impedance window from CK, /CK tHZ - tAC max - tAC max ps
DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps
DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps
DQS-DQ skew for DQS and associated DQ signals tDQSQ - 350 -300ps
DQ hold skew factor tQHS - 450 -400ps
DQ/DQS output hold time from DQS tQH tHP - tQHS -tHP - tQHS -ps
Write command to first DQS latching transition tDQSS WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 tCK
DQS input high pulse width tDQSH 0.35 -0.35 -tCK
DQS input low pulse width tDQSL 0.35 -0.35 -tCK
DQS falling edge to CK setup time tDSS 0.2 -0.2 -tCK
DQS falling edge hold time from CK tDSH 0.2 -0.2 -tCK
Mode register set command cycle time tMRD 2 - 2 - tCK
Write preamble tWPRE 0.35 -0.35 -tCK
Rev. 0.3 / Oct. 2008 23
1
240pin Registered DDR2 SDRAM DIMMs
Note:
1. For details and notes, please refer to the relevant HYNIX component datasheet H5PS1G[4,8]3EFR.
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Write postamble tWPST 0.4 0.6 0.4 0.6 tCK
Address and control input setup time tIS 350 - 250 -ps
Address and control input hold time tIH 475 - 375 -ps
Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK
Read postamble tRPST 0.4 0.6 0.4 0.6 tCK
Auto-Refresh to Active/Auto-Refresh command period tRFC 127.5 -127.5 -ns
Row Active to Row Active Delay for 1KB page size tRRD 7.5 - 7.5 - ns
Row Active to Row Active Delay for 2KB page size tRRD 10 - 10 - ns
Four Activate Window for 1KB page size tFAW 37.5 - 37.5 - ns
Four Activate Window for 2KB page size tFAW 50 - 50 - ns
CAS to CAS command delay tCCD 2 2 tCK
Write recovery time tWR 15 -15-ns
Auto Precharge Write Recovery + Precharge Time tDAL tWR + tRP - tWR + tRP - tCK
Write to Read Command Delay tWTR 10 - 7.5 -ns
Internal read to precharge command delay tRTP 7.5 7.5 ns
Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns
Exit self refresh to a read command tXSRD 200 -200 -tCK
Exit precharge power down to any non-read command tXP 2 - 2 - tCK
Exit active power down to read command tXARD 2 2 tCK
Exit active power down to read command
(Slow exit, Lower power) tXARDS 6 - AL 6 - AL tCK
CKE minimum pulse width
(high and low pulse width) tCKE 3 3tCK
ODT turn-on delay tAOND 2 2 2 2 tCK
ODT turn-on tAON tAC (min) tAC(max)+1 tAC (min) tAC(max)+1 ns
ODT turn-on (Power-Down mode) tAONPD tAC(min)+2 2tCK+tAC(m
ax)+1 tAC(min)+2 2tCK+tAC(m
ax)+1 ns
ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK
ODT turn-off tAOF tAC (min) tAC (max)+
0.6 tAC (min) tAC (max)+
0.6 ns
ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 2.5tCK+tAC(
max)+1 tAC(min)+2 2.5tCK+tAC(
max)+1 ns
ODT to power down entry latency tANPD 3 3 tCK
ODT power down exit latency tAXPD 8 8 tCK
OCD drive mode output delay tOIT 0 12 0 12 ns
Minimum time clocks remains ON after CKE
asynchronously drops LOW tDelay tIS + tCK + tIH tIS + tCK + tIH ns
Average peri odic Refresh Interval tREFI - 7.8 - 7.8 us 2
tREFI -3.9 -3.9 us 3
Parameter Symbol DDR2-400 DDR2-533 Unit Note
Min Max Min Max
Rev. 0.3 / Oct. 2008 24
1
240pin Registered DDR2 SDRAM DIMMs
(DDR2-667 & DDR2-800)
Parameter Symbol DDR2-667 DDR2-800 Unit Note
min max min max
DQ output access time from CK/CK tAC -450 +450 -400 +400 ps
DQS output access time from CK/CK tDQSCK -400 +400 -350 +350 ps
CK high-level width tCH 0.45 0.55 0.45 0.55 tCK
CK low-level width tCL 0.45 0.55 0.45 0.55 tCK
CK half period tHP min(tCL,
tCH) -min(tCL,
tCH) -ps
Clock cycle time, CL=x tCK 3000 8000 2500 ps
DQ and DM input setup time
(differen t ial strobe ) tDS 100 - 50 -ps 1
DQ and DM input hold time
(differen t ial strobe ) tDH 175 - 125 -ps 1
Control & Address input pulse width for each input tIPW 0.6 - 0.6 -tCK
DQ and DM input pulse width for each input tDIPW 0.35 - 0.35 -tCK
Data-out high-impedance time from CK/CK tHZ - tAC max - tAC max ps
DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps
DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps
DQS-DQ skew for DQS and associated DQ signals tDQSQ - 240 -200ps
DQ hold skew factor tQHS - 340 -300ps
DQ/DQS output hold time from DQS tQH tHP - tQHS -tHP - tQHS -ps
First DQS latching transition to associated clock
edge tDQSS - 0.25 + 0.25 - 0.25 + 0.25 tCK
DQS input high pulse width tDQSH 0.35 -0.35 -tCK
DQS input low pulse width tDQSL 0.35 -0.35 -tCK
DQS falling edge to CK setup time tDSS 0.2 -0.2 -tCK
DQS falling edge hold time from CK tDSH 0.2 -0.2 -tCK
Mode register set command cycle time tMRD 2 - 2 - tCK
Write preamble tWPRE 0.35 -0.35 -tCK
Write postamble tWPST 0.4 0.6 0.4 0.6 tCK
Auto-Refresh to Acti ve/Auto-Refresh command
period tRFC 127.5 -127.5 -ns
Row Active to Row Active Delay for 1KB page size tRRD7.5-7.5-ns
Address and control input setup time tIS 200 -175-ps
Address and control input hold time tIH 275 -250-ps
Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK
Read postamble tRPST 0.4 0.6 0.4 0.6 tCK
Activate to precharge command tRAS 45 70000 45 70000 ns
Active to active command period for 1KB page size
products tRRD 7.5 -7.5-ns
Row Active to Row Active Delay for 2KB page size tRRD 10 - 10 - ns
Four Active Window for 1KB page size products tFAW 37.5 -35 -ns
Four Activate Window for 2KB p age size tF AW 50 - 50 - ns
CAS to CAS command delay tCCD 2 2 tCK
Write recov er y time tWR 15 -15-ns
Auto pre c harge w r it e recovery + p r e c h a rge time tDAL WR+tRP -WR+tRP -tCK
Internal write to read command delay tWTR 7.5 -7.5-ns
Internal read to precharge command delay tRTP 7.5 7.5 ns
Rev. 0.3 / Oct. 2008 25
1
240pin Registered DDR2 SDRAM DIMMs
Note:
1. For details and notes, please refer to the relevant HYNIX component datasheet H5PS1G[4,8]3EFR.
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Parameter Symbol DDR2-667 DDR2-800 Unit Note
min max min max
Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns
Exit self refresh to a read command tXSRD 200 -200 -tCK
Exit precharge power down to any non-read
command tXP 2 - 2 - tCK
Exit active power down to read command tXARD 2 2 tCK
Exit active power down to read command
(Slow exit, Lower power) tXARDS 7 - AL 8 - AL tCK
CKE minimum pulse width
(high and low pulse width) tCKE 3 3tCK
ODT turn-on delay tAOND 2 2 2 2 tCK
ODT turn-on tAON tAC (min) tAC (max)
+0.7 tAC (min) tAC (max)
+0.7 ns
ODT turn-on (Power-Down mode) tAONPD tAC(min)+2 2tCK+
tAC(max)+1 tAC (min)
+2 2tCK+
tAC(max)+1 ns
ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK
ODT turn-off tAOF tAC (min) tAC (max)+ 0.6 tAC (min) tAC (max)
+0.6 ns
ODT turn-off (Power-Down mode) tAOFPD tAC (min)
+2 2.5tCK+
tAC(max)+1 tAC (min)
+2 2.5tCK+
tAC(max)+1 ns
ODT to power down entry latency tANPD 3 3 tCK
ODT power down exit latency tAXPD 8 8 tCK
OCD drive mode output delay tOIT 0 12 0 12 ns
Minimum time clocks remains ON after CKE
asynchronously drops LOW tDelay tIS + tCK + tIH tIS + tCK
+ tIH ns
Average pe riodic Refresh Interval tREFI - 7.8 - 7.8 us 2
tREFI -3.9 -3.9 us 3
Rev. 0.3 / Oct. 2008 26
1
240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
128Mx72 (1 rank) - HMP112P7EFR8C
Register
55.063.0 5.0
2X 3.00MIN
Front
1.27 ±0.10
2.70max
Side
1.0
0.35
0.8 ±0.05
2.50 ±0.20
Detail of Contacts A
Note) All dimensions are typical unless otherwise stated. Inches
Millimeters
4X FULL R
DETAIL-A DETAIL-B
128.95
133.35
2X
Ø2.50±
0.10
4X 4.0 ±0.1
2X 2.3 ±0.1
5.175
2X R1.00
10.00
17.80
30.00
0.05
Back
PLL
5.00
1.50 ±0.10
3.80
2.50
Detail of Contacts B
3.0 ±0.15
0.3 ±0.7
Rev. 0.3 / Oct. 2008 27
1
240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
256Mx72 (2 rank) - HMP125P7EFR8C
55.063.0 5.0
2X 3.00MIN
Front
1.27 ±0.10
4.00max
Side
1.0
0.35
0.8 ±0.05
2.50 ±0.20
5.00
1.50 ±0.10
3.80
2.50
Detail of Contacts A Detail of Contacts B
Note) All dimensions are typical unless otherwise stated. Inches
Millimeters
4X FULL R
DETAIL-A DETAIL-B
128.95
133.35
2X
Ø2.50±
0.10
4X 4.0 ±0.1
2X 2.3 ±0.1
5.175
2X R1.00
10.00
17.80
30.00
0.05
Back
3.0 ±0.15
0.3 ±0.7
Register
PLL
Register
Rev. 0.3 / Oct. 2008 28
1
240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
256Mx72 (1 rank) - HMP125P7EFR4C
55.063.0 5.0
2X 3.00MIN
Front
1.27 ±0.10
4.00max
Side
1.0
0.35
0.8 ±0.05
2.50 ±0.20
5.00
1.50 ±0.10
3.80
2.50
Detail of Contacts A Detail of Contacts B
Note) All dimensions are typical unless otherwise stated. Inches
Millimeters
4X FULL R
DETAIL-A DETAIL-B
128.95
133.35
2X
Ø2.50±
0.10
4X 4.0 ±0.1
2X 2.3 ±0.1
5.175
2X R1.00
10.00
17.80
30.00
0.05
Back
3.0 ±0.15
0.3 ±0.7
Register
PLL
Register
Rev. 0.3 / Oct. 2008 29
1
240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
512Mx72 (4 ranks) - HYMP151P7EFR8C
55.063.0 5.0
2X 3.00MIN
Front
1.27 ±0.10
4.00max
Side
1.0
0.35
0.8 ±0.05
2.50 ±0.20
Detail of Contacts A
Note) All dimensions are typical unless otherwise stated. Inches
Millimeters
4X FULL R
DETAIL-A DETAIL-B
128.95
133.35
2X
Ø2.50±
0.10
4X 4.0 ±0.1
2X 2.3 ±0.1
5.175
2X R1.00
10.00
17.80
30.00
0.05
Back
Register
PLL
Register
5.00
1.50 ±0.10
3.80
2.50
Detail of Contacts B
3.0 ±0.15
0.3 ±0.7
Register
Register
Rev. 0.3 / Oct. 2008 30
1
240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
512Mx72 (2 ranks) - HYMP151P7EFR4C
55.063.0 5.0
2X 3.00MIN
Front
1.27 ±0.10
4.00max
Side
1.0
0.35
0.8 ±0.05
2.50 ±0.20
Detail of Contacts A
Note) All dimensions are typical unless otherwise stated. Inches
Millimeters
4X FULL R
DETAIL-A DETAIL-B
128.95
133.35
2X
Ø2.50±
0.10
4X 4.0 ±0.1
2X 2.3 ±0.1
5.175
2X R1.00
10.00
17.80
30.00
0.05
Back
Register
PLL
5.00
1.50 ±0.10
3.80
2.50
Detail of Contacts B
3.0 ±0.15
0.3 ±0.7
Register
Rev. 0.3 / Oct. 2008 31
1
240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
1Gx72 (4 ranks) - HMP31GP7EMR4C
Register
PLL
55.063.0 5.0
2X 3.00MIN
Front
1.27 ±0.10
7.55max
Side
1.0
0.35
0.8 ±0.05
2.50 ±0.20
Detail of Contacts A
Note) All dimensions are typical unless otherwise stated. Inches
Millimeters
4X FULL R
DETAIL-A DETAIL-B
128.95
133.35
2X
Ø2.50±
0.10
4X 4.0 ±0.1
2X 2.3 ±0.1
5.175
2X R1.00
10.00
17.80
30.00
Register
0.05
Back
5.00
1.50 ±0.10
3.80
2.50
Detail of Contacts B
3.0 ±0.15
0.3 ±0.7
Rev. 0.3 / Oct. 2008 32
1
240pin Registered DDR2 SDRAM DIMMs
REVISION HISTORY
Revision History Date
0.1 Initial release Jul. 2008
0.2 Editorial Correction Sep. 2008
0.3 Added 2Rx8, 4Rx8 Oct. 2008
