LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller Datasheet Version 2.0 The LSISAS1064E is a four-port, 3.0 Gbit/s SAS/SATA controller that is compliant with the Fusion-MPTTM (Message Passing Technology) architecture, provides an eight-lane PCI Express interface, and supports Integrated RAIDTM technology. The PCI Express software is backward compatible with previous revisions of the PCI bus and PCI-X bus. The LSISAS1064E supports the PCI Express Base Specification, Revision 1.0a, and the ANSI Serial Attached SCSI Standard, Revision 1.1. Figure 1 and Figure 2 provide examples of LSISAS1064E applications. The point-to-point interconnect feature of the PCI Express bus limits the electrical load on links, allowing increased transmission and reception frequencies. The PCI Express transmission and reception data rates for each full-duplex interconnect is 2.5 Gbits/s. The LSISAS1064E has eight PCI Express phys, which provide host-side possible maximum transmission and reception rates of 4.0 Gbytes/s. The LSISAS1064E supports x8, x4, and x1 PCI Express link widths, and automatically downshifts if plugged into either a x4 connector or into a x8 connector that is wired as a x4 connector. The serial PCI Express interconnect between devices lowers the number of pins per device, which reduces both the PCI Express board design costs and the overall board design complexity. The serial connection also makes the PCI Express performance highly scalable. Figure 1 LSISAS1064E Direct-Connect Example PCI Express Interface 8 LSISAS1064E PCI Express to SAS Controller 32-bit Memory Address/Data Bus Flash ROM/ NVSRAM Serial Interface I2C SAS/SATA Drives DB08-000275-03 May 2006 Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. 1 of 30 Figure 2 LSISAS1064E Controller and LSISASx12 Expander Example PCI Express Interface 8 32-bit Memory Address/Data Bus LSISAS1064E LSISASx12 SAS/SATA Drives Flash ROM/ NVSRAM Serial Interface I2C LSISASx12 SAS/SATA Drives SAS/SATA Drives SAS/SATA Drives PCI Express implements a switch-based technology to interconnect a large number of devices. Communication over the serial interconnect is accomplished using packet-based communication protocol. Quality of Service (QOS) features provide differentiated transmission performance for different applications. Hot Plug/Hot Swap support enables "always-on" systems. Enhanced error handling features, such as end-to-end CRC (ECRC) and Advanced Error Reporting, make PCI Express suitable for robust, high-end server applications. Hot Plug, power management, error handling, and interrupt signaling are accomplished using packet-based messaging rather than sideband signals. This keeps the device pin count low and reduces the system cost. Each of the four SAS phys on the LSISAS1064E is capable of SAS/SATA link rates of 3.0 Gbits/s and 1.5 Gbits/s. The user can configure ports as wide or narrow. Narrow ports have one phy per port. Wide ports have two, three, or four phys per port. Each port supports the SSP, SMP, STP, and SATA protocols. 2 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. The SAS interface uses the proven SCSI command set to ensure reliable data transfers, while providing the connectivity and flexibility of point-to-point serial data transfers. The SAS interface provides improved performance, simplified cabling, smaller connectors, lower pin count, and lower power requirements when compared to parallel SCSI. SAS controllers leverage an electrical and physical connection interface that is compatible with SATA technology. The LSISAS1064E supports the Integrated RAID solution, which is a highly integrated, low cost RAID implementation. It is designed for systems requiring redundancy and high availability, but not needing a full-featured RAID implementation. Integrated RAID technology supports up to two volumes and ten drives. Each volume can contain up to eight drives. The Integrated RAID solution includes Integrated MirroringTM (IM) technology, Integrated Mirroring Enhanced (IME), and Integrated StripingTM (IS) technology. IM provides physical mirroring of two physical drives, plus a hot spare drive. IME supports 3-8 drives plus a hot spare drive. IM and IME require an NVSRAM to support write journaling. IS enables data striping across up to eight physical drives. The Integrated RAID solution is OS independent, easy to install and configure, supports up to eight drives at RAID Level 0, and does not require a special driver. The run-time operation of the Integrated RAID solution is transparent to the operating system. A single firmware build supports all Integrated RAID capabilities. The LSISAS1064E uses the Fusion-MPT architecture, which features a performance based message passing protocol that offloads the host CPU by completely managing all I/Os and minimizes system bus overhead by coalescing interrupts. The proven Fusion-MPT architecture requires only thin, easy-to-develop device drivers that are independent of the I/O bus. LSI Logic provides these device drivers. To meet its flexibility and data transfer requirements, the LSISAS1064E uses an ARM966 processor that operates at 225 MHz. LSI manufactures the LSISAS1064E using GflxTM technology. LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. 3 of 30 Features This section lists the features of the LSISAS1064E. SSP and SAS Features This section describes the SSP and SAS features. * Each phy supports 3.0 Gbit/s and 1.5 Gbit/s SAS data transfers * Provides a serial, point-to-point, enterprise-level storage interface * Supports wide transfers consisting of two, three, or four phys * Supports narrow ports consisting of a single phy * Transfers data using SCSI information units * Is compatible with SATA target devices SATA and STP Features This section describes the SATA and STP features. * Each phy supports 3.0 Gbit/s and 1.5 Gbit/s SATA data transfers * Each phy supports 3.0 Gbit/s and 1.5 Gbit/s STP data transfers * Allows addressing of multiple SATA targets through an expander * Allows multiple initiators to address a single target (in a fail-over configuration) through an expander PCI Express Features The LSISAS1064E supports these PCI Express features. * Provides eight PCI Express phys * Supports a single-phy (1 lane) link transfer rate up to 2.5 Gbits/s in each direction * Supports x8, x4, and x1 link widths * Automatically downshifts to a x4 link width if plugged into a x4 connector or into a x8 connector that is wired as a x4 connector 4 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. * Provides a scalable interface - Single-lane aggregate bandwidth of up to 0.5 Gbytes/s (500 Mbytes/s) - Quad-lane aggregate bandwidth of up to 2.0 Gbytes/s (2000 Mbytes/s) - 8-lane aggregate bandwidth of up to 4.0 Gbytes/s (4000 Mbytes/s) * Offers a maximum payload of 2 Kbytes * Supports serial, point-to-point interconnections between devices - Reduces the electrical load of the connection - Enables higher transmission and reception frequencies * Supports lane reversal and polarity inversion * Supports PCI Express Hot Plug * Supports Power Management - Supports the PCI Power Management 1.2 specification - Supports Active State Power Management, including the L0, L0s, and L1 states, by placing links in a power-savings mode during times of no link activity * Uses a packetized and layered architecture * Achieves a high bandwidth per pin with low overhead and low latency * PCI Express is software compatible with PCI and PCI-X software - Leverages existing PCI device drivers - Supports the Memory, I/O, and Configuration address spaces - Supports memory read/write transactions, I/O read/write transactions, and configuration read/write transactions * Provides 4 Kbytes of PCI Configuration address space per device * Supports posted and nonposted transactions * Provides quality of service (QOS) link configuration and arbitration policies * Supports Traffic Class 0 and one virtual channel * Supports Message Signaled Interrupts (both MSI and MSI-X) as well as INTx interrupt signaling for legacy PCI support * Supports end-to-end CRC (ECRC) and Advanced Error Reporting LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. 5 of 30 Integration These features make the LSISAS1064E easy to integrate: * Leverages the proven Fusion-MPT technology * PCI Express device can use PCI-based device drivers, which reduces integration challenges and risks * Provides unequaled performance through the Fusion-MPT architecture * Reduces time to market with the Fusion-MPT architecture - Single driver binary for SAS/SATA, Ultra320 SCSI, and Fibre Channel products - One firmware build supports all Integrated RAID capabilities - Thin, easy to develop drivers - Reduced integration and certification effort Usability These usability features are incorporated into the design: * Simplifies cabling with point-to-point, serial architecture * Provides drive spin-up sequencing control * Provides up to two LED signals for each SAS/SATA phy to indicate drive activity and faults * Provides a serialized general purpose I/O (SGPIO) interface Flexibility These features increase the flexibility of the LSISAS1064E: * Supports an 8-bit flash ROM interface and an 8-bit nonvolatile RAM (NVSRAM) interface * Offers a flexible programming interface to tune I/O performance * Allows mixed connections to SAS or SATA targets * Allows a grouping of up to four phys in a wide port * Leverages compatible connectors for SAS and SATA connections 6 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. * Supports Integrated RAID technology, which provides for Integrated Mirroring technology and/or Integrated Striping technology * Provides 17 LED signals * Provides four independent GPIO signals Reliability These features enhance the reliability of the LSISAS1064E: * Uses proven GigaBlaze(R) transceivers on both the SAS/SATA phys and the PCI Express phys * Isolates the power and ground of I/O pads and internal chip logic * Provides ESD protection * Provides latch-up protection * Has a high proportion of power and ground pins * Integrated Mirroring technology provides physical mirroring of the boot volume Testability These features enhance the testability of the LSISAS1064E: * Offers JTAG boundary scan * Offers ARM(R) Multi-ICE(R) technology for debugging the ARM966 processor Block Diagram Description Figure 3 provides the block diagram for the LSISAS1064E. The following subsections discuss the block diagram. There is a single Host Interface module and a Quad Port module. The Host Interface module supports the 8-lane PCI Express interface. The Quad Port module supports four SAS phys. LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. 7 of 30 Figure 3 LSISAS1064E Block Diagram Quad Port Module Host Interface Module PCI Express PCI Express Interface Queue Manager PCI TimerConfig AHB Bridge DMA Arbiter AHB Interface SECONDARY SATA Engine AHB Interface CONTEXT System Interface Transport Modules ICE I/F IOP (ARM966) Processor Quad Port Context AHB Bus Quad Port DMA Arbiter AHB Arbiter IRQ Controller GPIO/LED SAS Link SAS Link SAS Link SAS Link SAS Phy SAS Phy SAS Phy SAS Phy Primary AHB Bus TimerConfig Port Layer Connection Manager and Switch SIO A SIO A UART UART XMEM Bus External Memory Context RAM I2C I2C Host Interface Module The LSISAS1064E interfaces with the host through the host interface module. The host interface module contains the PCI Express interface, system interface, IOP (ARM966) processor, timer and configuration, DMA arbiter, PCI timer and configuration, SIO, external memory, I2C, and UART blocks. 8 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. PCI Express Interface The PCI Express interface block supports an 8-lane PCI Express interface. This is a high bandwidth, serial interface that features point-to-point interconnects between devices and an advanced packetized and layered protocol architecture. The PCI Express software is backward compatible with previous implementations of the PCI specification. System Interface In combination with the IOP, the system interface supports the Fusion-MPT architecture. The system interface efficiently passes messages between the LSISAS1064E and the host interface using a high-performance, packetized mailbox architecture. The LSISAS1064E system interface takes advantage of PCI Express point-to-point connections, thereby allowing a dedicated connection to each device with no sharing. IOP (ARM966) Processor The LSISAS1064E I/O processor (IOP) controls the system interface and manages the host side of the Fusion-MPT architecture without host processor intervention, which frees the host processor for other tasks. Timer and Configuration This block supports the LSISAS1064E LED and GPIO interfaces. There are nine LED signals. The GPIO interface contains four independent GPIO signals. This block also supports internal timing adjustments and power-on sense configuration options. DMA Arbiter The LSISAS1064E provides the ability to transfer system memory blocks to and from local memory through the descriptor-based DMA arbiter and router. The DMA channel includes a system DMA FIFO and the internal bus interface logic. PCI Timer and Configuration This PCI timer and configuration module supports the PCI configuration register space and a power-on reset (POR). LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. 9 of 30 SIO The LSISAS1064E provides an SGPIO interface that is compliant with the SFF-8485 specification. A typical use of the serial I/O (SIO) module is to provide control of LEDs. The SIO module is SFF-8485 compliant. External Memory The external memory controller block provides an interface for flash ROM and NVSRAM devices. The external memory bus provides a 32-bit memory bus, parity checking, and chip select signals for NVSRAM and flash ROM. The flash ROM and NVSRAM are capable of 8-bit accesses. Typical system configurations require a flash ROM to store firmware, configuration information, and persistent data information. I2C The LSISAS1064E contains an Inter-IC (I2C) block that communicates with peripherals. The I2C block operates as either a master or a slave on the bus and sustains data rates up to 400 Kbits/s. The I2C block accomplishes byte-wise bidirectional data transfers by using either an interrupt or a polling handshake at the completion of each byte. The I2C block controls all bus timing and performs bus-specific sequences. UART The UART provides test and debug access to the LSISAS1064E. Quad Port Module The Quad Port module in the LSISAS1064E implements the SSP, SMP, and STP/SATA protocols, and manages the SAS/SATA phys. The Quad Port module supports four phys. The following subsections describe the Quad Port module. Transport Modules The transport modules transmit frames to and from the port layer and implement the STP, SSP, and SMP protocols. The Quad Port module has four instances of the transport module, one for each SAS/SATA phy on the LSISAS1064E. The transport modules also manage DMA transfers. 10 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. Queue Manager The queue manager is responsible for managing various queue structures that support the SSP, SMP, and SATA/STP protocols. The queue structures are the primary means for the IOP to initiate I/Os to the hardware, and for the hardware to notify the IOP of I/O status. SATA Engine The SATA engine provides information to the transport modules to enable handling of SATA commands. The SATA engine tracks queued commands per device and provides these tags to the SATA transport layer blocks. Port Layer Connection Manager and Switch The port layer connection manager and switch handles transmission requests from the transport modules and originates connection requests to the SAS links. It is also responsible for handling SAS wide port configurations. SAS Link The SAS link layer manages SAS connections between initiator and target ports, data clocking, and CRC checking on transmitted data. The SAS link is also responsible for starting a link reset sequence. SAS Phys The SAS phys interface to the physical layer, perform serial-to-parallel conversion of received data and parallel-to-serial conversion of transmit data, manage phy reset sequences, and perform 8b/10b encoding. Quad Port DMA Arbiter The quad port arbiter interfaces with the host interface DMA arbiter and determines bus priority between the quad port phys for DMA transfers. Context RAM The context RAM is a memory that is shared between the host interface module and the quad port module. The context RAM holds a portion of the firmware. LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 11 of 30 DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. Signal Descriptions The following subsections provide the signal descriptions for the LSISAS1064E. A `/' following the signal indicates an active LOW signal. PCI Express Signals This section describes the PCI Express signals. Refer to the PCI Express specification for detailed signal descriptions. PCI Express System Signals This section describes the PCI Express system signals. P_REFCLK_P PCI Express Differential Clock Input This signal provides half of the PCI Express differential clock input signal. P_REFCLK_N PCI Express Differential Clock Input This signal provides half of the PCI Express differential clock input signal. RST/ Reset Asserting the RST/ signal causes a reset. Input PCI Express Data Signals This section describes the PCI Express transmit and receive signals. P_RX[7:0]+ PCI Express Receive Differential Data Input P_RX[x]+ provides the positive differential data receiver for PCI Express phy[x]. P_RX[7:0]- PCI Express Receive Differential Data Input P_RX[x]- provides the negative differential data receiver for PCI Express phy[x]. P_TX[7:0]+ PCI Express Transmit Differential Data P_TX[x]+ provides the positive differential data transmitter for PCI Express phy[x]. P_TX[7:0]- PCI Express Transmit Differential Data Output P_TX[x]- provides the negative differential data transmitter for PCI Express phy[x]. 12 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. Output SAS Signals This section describes the SAS interface signals. REFCLK_P, REFCLK_N Input These pins provide the serial differential clock. Connect a 75 MHz oscillator with an accuracy of at least 50ppm to these pins. To use a single-ended crystal, tie the crystal to REFCLK_P and tie REFCLK_N to a resistor termination. RTRIM Resistor Reference Analog This pin provides the analog resistor reference for the GigaBlaze transceivers. The resistor provides a reference to calibrate the 50 termination. RX[3:0]- Receive Negative Differential Data Input RX[x]- provides the negative differential data receiver for SAS/SATA phy[x]. RX[3:0]+ Receive Positive Differential Data Input RX[x]+ provides the positive differential data receiver for SAS/SATA phy[x]. TX[3:0]- Transmit Negative Differential Data Output TX[x]- provides the negative differential data transmit signal for SAS/SATA phy[x]. TX[3:0]+ Transmit Positive Differential Data Output TX[x]+ provides the positive differential data transmit signal for SAS/SATA phy[x]. I2C and UART Signals This section describes the I2C and UART signals. ISTWI_CLK I2C Clock This signal provides the I2C clock signal. Input/Output ISTWI_DATA I2C Data This signal provides the I2C data signal. Input/Output UART_RX UART Receive This signal provides the UART receive signal. Input LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 13 of 30 DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. UART_TX UART Transmit This signal provides the UART transmit signal. Output Memory Interface Signals This section describes the memory interface signals. MCLK Memory Clock Output All synchronous RAM control/data signals reference the rising edge of this clock. ADSC/ Address-Strobe-Controller Output Asserting this active LOW signal initiates read, write, or chip deselect cycles. ADV/ Advance Output Asserting this active LOW signal increments the burst address counter of the selected synchronous SRAM. MAD[31:0] Multiplexed Address/Data Input/Output These signals provide the address and data bus for the flash ROM and NVSRAM. These signals also provide Power-On Sense configuration functions to the LSISAS1064E. These signals are internally pulled LOW. MADP[3:0] Memory Parity Input/Output These signals provide parity checking for MAD[31:0]. These signals are internally pulled HIGH. MOE[1:0]/ Memory Output Enables Output Asserting these active LOW signals enable the selected flash ROM or NVSRAM device to drive data. MOE1/ enables flash ROM devices. MOE0/ enables NVSRAM devices. MWE[1:0]/ Memory Write Enables Output The MWE[1:0]/ signals provide memory enable signals. BWE[3:0]/ Memory Byte Write Enables Output BWE[3]/ and BWE[2]/ enable partial word writes to the flash ROM and the NVSRAM if FLASH_CS/ or NVSRAM_CS/ is asserted. 14 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. NVSRAM_CS/ NVSRAM Chip Select Output Asserting this active LOW signal selects the NVSRAM device. FLASH_CS/ Flash Chip Select Output Asserting this active LOW signal selects the flash ROM. The LSISAS1064E maps flash ROM address space into system memory space. SIO Signals This section describes the SIO signals. SIO_CLK_A SIO Clock Input/Output This signal provides the clock signal for SIO A. SIO_DIN_A SIO Data In A Input This signal provides the data input signal to SIO A. SIO_DOUT_A SIO Data Out A Output This signal provides the data output signal to SIO A and can control the Quad Port LED drives. SIO_END_A SIO End Control Input/Output The SIO module drives this output to end control of the SIO bus. Configuration and General Purpose Signals This section describes the configuration and general purpose pins. TST_RST/ Test Reset Input Asserting this signal forces the chip into a Power-On-Reset (POR) state. This signal has an internal pull-up. The LSISAS1064E does not have an internal POR. REFCLK_B ARM Reference Clock This pin provides the ARM reference clock. MODE[7:0] Mode Select Input This 8-bit bus defines operational and test modes for the chip. These pins have internal pull-downs. Input LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 15 of 30 DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. FAULT_LED[3:0]/ Fault LED Input/Output These output signals indicate a SAS link fault. ACTIVE_LED[3:0]/ Activity LED Input/Output These output signals indicate SAS link activity. GPIO[3:0] General Purpose I/O Input/Output These signals provide general purpose input/output signals. These signals have internal pull-ups. HB_LED/ Heartbeat LED Output Firmware intermittently asserts this signal to indicate that the IOP is operational. JTAG and Test Signals This section describes the JTAG and test signals. FSELA Clock Select This is a test signal. Pull this signal LOW. Input SCAN_ENABLE Scan Enable Input SCAN_MODE Scan Mode Input TCK JTAG Debug Clock Input TRST/ JTAG Debug Reset Input TDI JTAG Debug Test Data In Input TDO JTAG Debug Test Data Out TMS JTAG Debug Test Mode Select Input TCK_ICE Multi-ICE Debug Clock Input RTCK_ICE Multi-ICE Debug Return Clock TRST_ICE/ Multi-ICE Debug Reset Input TDI_ICE Multi-ICE Debug Test Data In Input TDO_ICE Multi-ICE Debug Test Data Out 16 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. Output Output Output TMS_ICE Multi-ICE Debug Test Mode Select Input IDDT IDDQ Test Mode Enable This signal is active HIGH. Input TN/ 3-State Output Enable Control This signal is active LOW. Input PROCMON Process Monitor Test Output Driver TDIODE_P Anode Connection of the Thermal Diode TDIODE_VSS Cathode Connection of the Thermal Diode Output Input Output Power and Ground Signals This section describes the power and ground signals. REFPLL_VDD Power These signals provide 1.2 V power. REFPLL_VSS Ground These signals provide ground. VDD2 Power These signals provide 1.2 V core power. VDDIO33 Power These signals provide 3.3 V I/O power. VSS Ground These signals provide ground. RX_VSS[3:0], RXB_VSS[3:0], TX_VSS[3:0], TXB_VSS[3:0] Ground These signals provide ground for the SAS GigaBlaze core. RX_VDD[3:0], RXB_VDD[3:0], TX_VDD[3:0], TXB_VDD[3:0] These signals provide 1.2 V power for the SAS GigaBlaze core. Power P_RX_VDD[7:0], P_RXB_VDD[7:0], P_TX_VDD[7:0], P_TXB_VDD[7:0] Power These signals provide 1.2 V power for the PCI Express GigaBlaze core. LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 17 of 30 DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. P_RX_VSS[7:0], P_RXB_VSS[7:0], P_TX_VSS[7:0], P_TXB_VSS[7:0] Ground These signals provide ground for the PCI Express GigaBlaze core. Pin Listing Table 1 provides the signal listing by signal name. Table 2 provides the signal listing by pin name. Figure 4 provides a BGA diagram. 18 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. (This page left intentionally blank.) LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 19 of 30 DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. Table 1 LSISAS1064E Pin Assignments Listed by Signal Name1 Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin ACTIVE_LED[0]/ ACTIVE_LED[1]/ ACTIVE_LED[2]/ ACTIVE_LED[3]/ ADSC/ ADV/ BWE[0]/ BWE[1]/ BWE[2]/ BWE[3]/ FAULT_LED[0]/ FAULT_LED[1]/ FAULT_LED[2]/ FAULT_LED[3]/ FLASH_CS/ FSELA GPIO[0] GPIO[1] GPIO[2] GPIO[3] HB_LED/ IDDT ISTWI_CLK ISTWI_DATA MAD[0] MAD[1] MAD[2] MAD[3] MAD[4] MAD[5] MAD[6] MAD[7] MAD[8] MAD[9] MAD[10] MAD[11] MAD[12] MAD[13] MAD[14] MAD[15] MAD[16] MAD[17] MAD[18] MAD[19] MAD[20] MAD[21] MAD[22] MAD[23] MAD[24] MAD[25] MAD[26] MAD[27] MAD[28] MAD[29] MAD[30] MAD[31] MADP[0] MADP[1] MADP[2] MADP[3] MCLK MODE[0] MODE[1] MODE[2] MODE[3] MODE[4] MODE[5] MODE[6] MODE[7] MOE0/ MOE1/ MWE0/ MWE1/ N/C N/C N/C N/C N/C H1 H2 G1 H3 V22 V23 T21 U24 R23 W25 N1 N3 M1 L1 P25 E2 V4 Y1 W3 AB1 P4 AB4 G26 K21 J26 H26 K24 J24 J23 M26 M23 J25 K25 L26 L23 K23 K26 N23 R26 P23 V21 Y26 W24 U21 AA26 W23 AA23 Y23 AB25 AB23 AB24 Y21 AC25 AC26 AB22 AD25 L21 U26 W26 AA22 U23 J6 H4 D1 G4 G5 D2 F4 G6 U25 N24 T23 P24 B14 C24 C25 D3 D23 N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C E1 E3 E13 E22 E23 E24 F1 F6 F22 F23 G20 G21 H5 H6 H21 H23 H25 J1 J2 J3 J4 J5 J22 K1 K5 K6 L4 L5 L6 L22 M5 M6 M21 M22 N6 N21 N22 N25 P2 P6 P21 P22 P26 R1 R4 R5 R6 R22 T6 T26 U1 U2 U5 U6 U22 V1 V2 V5 V6 V24 V25 W2 W4 W5 W6 W7 W21 W22 Y5 Y6 Y22 AA1 AA5 AA6 AB13 AB26 AC12 AC13 N/C N/C N/C N/C N/C N/C N/C NVSRAM_CS/ P_REFCLK_N P_REFCLK_P P_RX_VDD0 P_RX_VDD1 P_RX_VDD2 P_RX_VDD3 P_RX_VDD4 P_RX_VDD5 P_RX_VDD6 P_RX_VDD7 P_RX_VSS0 P_RX_VSS1 P_RX_VSS2 P_RX_VSS3 P_RX_VSS4 P_RX_VSS5 P_RX_VSS6 P_RX_VSS7 P_RX0P_RX0+ P_RX1P_RX1+ P_RX2P_RX2+ P_RX3P_RX3+ P_RX4P_RX4+ P_RX5P_RX5+ P_RX6P_RX6+ P_RX7P_RX7+ P_RXB_VDD0 P_RXB_VDD1 P_RXB_VDD2 P_RXB_VDD3 P_RXB_VDD4 P_RXB_VDD5 P_RXB_VDD6 P_RXB_VDD7 P_RXB_VSS0 P_RXB_VSS1 P_RXB_VSS2 P_RXB_VSS3 P_RXB_VSS4 P_RXB_VSS5 P_RXB_VSS6 P_RXB_VSS7 P_TX_VDD0 P_TX_VDD1 P_TX_VDD2 P_TX_VDD3 P_TX_VDD4 P_TX_VDD5 P_TX_VDD6 P_TX_VDD7 P_TX_VSS0 P_TX_VSS1 P_TX_VSS2 P_TX_VSS3 P_TX_VSS4 P_TX_VSS5 P_TX_VSS6 P_TX_VSS7 P_TX0P_TX0+ P_TX1P_TX1+ AC24 AD1 AD3 AD13 AE3 AE13 AF13 N26 AD14 AE14 AB6 AC7 AC9 AE10 AC15 AD18 AC19 AB21 AB7 AA9 AD9 AB12 AA15 AC17 AA18 AC22 AF4 AF3 AE7 AE6 AF8 AE8 AF11 AF10 AE17 AF17 AF20 AF19 AE21 AE20 AE25 AE24 Y8 AB9 AD10 AF12 AB15 AA17 AD19 AD23 AD7 Y10 AA11 AA13 Y16 AB17 AA19 AA21 AB5 AD4 AC8 AC10 AC14 AD17 AC18 AF23 AA7 AA8 AF7 AB11 AB14 AC16 Y18 AB19 AE2 AF2 AE5 AE4 P_TX2P_TX2+ P_TX3P_TX3+ P_TX4P_TX4+ P_TX5P_TX5+ P_TX6P_TX6+ P_TX7P_TX7+ P_TXB_VDD0 P_TXB_VDD1 P_TXB_VDD2 P_TXB_VDD3 P_TXB_VDD4 P_TXB_VDD5 P_TXB_VDD6 P_TXB_VDD7 P_TXB_VSS0 P_TXB_VSS1 P_TXB_VSS2 P_TXB_VSS3 P_TXB_VSS4 P_TXB_VSS5 P_TXB_VSS6 P_TXB_VSS7 PROCMON REFCLK_B REFCLK_N REFCLK_P REFPLL_VDD REFPLL_VSS RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RST/ RTCK_ICE RTRIM RX_VDD0 RX_VDD1 RX_VDD2 RX_VDD3 RX_VSS0 RX_VSS1 RX_VSS2 AF5 AF6 AE9 AF9 AF15 AF16 AF18 AE18 AF21 AF22 AE23 AE22 Y7 AD8 AB10 AA12 AF14 AA16 AB18 AA20 AC4 AB8 AA10 AC11 AA14 AB16 AE19 AB20 AA4 B13 D12 C13 D13 A13 A3 A4 A5 A6 A8 A9 A10 A11 B3 B4 B5 B6 B7 B8 B9 C3 D24 D26 H24 K2 K3 K4 K22 G22 G23 M4 N2 N4 N5 P1 P3 P5 R21 T1 AB3 T4 C14 E21 D19 C18 D15 D22 F18 D17 RX_VSS3 RX0RX0+ RX1RX1+ RX2RX2+ RX3RX3+ RXB_VDD0 RXB_VDD1 RXB_VDD2 RXB_VDD3 RXB_VSS0 RXB_VSS1 RXB_VSS2 RXB_VSS3 SCAN_ENABLE SCAN_MODE SIO_CLK_A SIO_DIN_A SIO_DOUT_A SIO_END_A TCK TCK_ICE TDI TDI_ICE TDIODE_P TDIODE_VSS TDO TDO_ICE TMS TMS_ICE TN/ TRST_ICE/ TRST/ TST_RST/ TX_VDD0 TX_VDD1 TX_VDD2 TX_VDD3 TX_VSS0 TX_VSS1 TX_VSS2 TX_VSS3 TX0TX0+ TX1TX1+ TX2TX2+ TX3TX3+ TXB_VDD0 TXB_VDD1 TXB_VDD2 TXB_VDD3 TXB_VSS0 TXB_VSS1 TXB_VSS2 TXB_VSS3 UART_RX UART_TX VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 F15 B25 B24 B21 B20 A20 A19 B17 A17 C23 C19 F17 E15 F21 F19 E17 G16 E4 F5 H22 J21 D25 E25 AB2 U3 AC1 T5 V26 T22 AC2 V3 AC3 U4 AD2 W1 Y4 C2 A23 D18 C17 D14 E19 G18 D16 E14 B23 B22 A21 A22 A18 B18 A15 A16 F20 E18 F16 A14 E20 B19 E16 F14 E26 F26 A12 B10 C4 C8 C10 D7 D8 D9 D10 E5 E6 E9 E10 F12 1. N/C pins are not connected. 20 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. Table 1 LSISAS1064E Pin Assignments Listed by Signal Name1 (Cont.) Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 G7 G8 K11 K13 K15 K17 L10 L12 L14 L16 M11 M13 M15 M17 N10 N12 N14 N16 P11 P13 P15 P17 R10 R12 R14 R16 T11 T13 T15 T17 U10 U12 U14 U16 A24 B2 B11 B12 B15 B16 C1 C5 C6 C20 C21 C26 F2 F25 G2 G9 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 G11 G12 G13 G14 G15 G17 G19 G25 H7 H20 J7 J20 K7 K20 L2 L7 L20 L25 M2 M7 M20 M25 N7 N20 P7 P20 R2 R7 R20 R25 T2 T7 T20 T25 U7 U20 V7 V20 W20 Y2 Y9 Y11 Y12 Y13 Y14 Y15 Y17 Y19 Y20 Y25 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AA2 AA25 AC23 AD5 AD6 AD20 AD21 AD24 AD26 AE11 AE12 AE15 AE16 AF24 A2 A7 A25 B1 B26 C7 C9 C11 C12 C15 C16 C22 D4 D5 D6 D11 D20 D21 E7 E8 E11 E12 F3 F7 F8 F9 F10 F11 F13 F24 G3 G10 G24 H8 H9 H10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS H11 H12 H13 H14 H15 H16 H17 H18 H19 J8 J19 K8 K10 K12 K14 K16 K19 L3 L8 L11 L13 L15 L17 L19 L24 M3 M8 M10 M12 M14 M16 M19 M24 N8 N11 N13 N15 N17 N19 P8 P10 P12 P14 P16 P19 R3 R8 R11 R13 R15 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS R17 R19 R24 T3 T8 T10 T12 T14 T16 T19 T24 U8 U11 U13 U15 U17 U19 V8 V19 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Y3 Y24 AA3 AA24 AC5 AC6 AC20 AC21 AD11 AD12 AD15 AD16 AD22 AE1 AE26 AF25 1. N/C pins are not connected. LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 21 of 30 DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. LSISAS1064E Pin Assignments Listed by Pin Number1 Table 2 Pin Signal Pin A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 VSS RESERVED RESERVED RESERVED RESERVED VSS RESERVED RESERVED RESERVED RESERVED VDD2 REFPLL_VSS TXB_VDD3 TX3TX3+ RX3+ TX2RX2+ RX2TX1TX1+ TX_VDD0 VDDIO33 VSS VSS VDDIO33 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED VDD2 VDDIO33 VDDIO33 REFCLK_B N/C VDDIO33 VDDIO33 RX3TX2+ TXB_VSS1 RX1+ RX1TX0+ TX0RX0+ RX0VSS VDDIO33 TST_RST/ RESERVED VDD2 VDDIO33 VDDIO33 VSS VDD2 VSS VDD2 VSS VSS REFCLK_P RTRIM VSS VSS TX_VDD2 RX_VDD2 RXB_VDD1 VDDIO33 VDDIO33 VSS RXB_VDD0 N/C N/C VDDIO33 MODE[2] MODE[5] D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 Signal N/C VSS VSS VSS VDD2 VDD2 VDD2 VDD2 VSS REFCLK_N REFPLL_VDD TX_VDD3 RX_VDD3 TX_VSS2 RX_VSS2 TX_VDD1 RX_VDD1 VSS VSS RX_VSS0 N/C RESERVED SIO_DOUT_A RESERVED N/C FSELA N/C SCAN_ENABLE VDD2 VDD2 VSS VSS VDD2 VDD2 VSS VSS N/C TX_VSS3 RXB_VDD3 TXB_VSS2 RXB_VSS2 TXB_VDD1 TX_VSS0 TXB_VSS0 RX_VDD0 N/C N/C N/C SIO_END_A UART_RX N/C VDDIO33 VSS MODE[6] SCAN_MODE N/C VSS VSS VSS VSS VSS VDD2 VSS TXB_VSS3 RX_VSS3 TXB_VDD2 RXB_VDD2 RX_VSS1 RXB_VSS1 TXB_VDD0 RXB_VSS0 N/C N/C VSS VDDIO33 UART_TX ACTIVE_LED[2]/ VDDIO33 Pin G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 J7 J8 J19 J20 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K7 K8 K10 K11 K12 K13 Signal VSS MODE[3] MODE[4] MODE[7] VDD2 VDD2 VDDIO33 VSS VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 RXB_VSS3 VDDIO33 TX_VSS1 VDDIO33 N/C N/C RESERVED RESERVED VSS VDDIO33 ISTWI_CLK ACTIVE_LED[0]/ ACTIVE_LED[1]/ ACTIVE_LED[3]/ MODE[1] N/C N/C VDDIO33 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIO33 N/C SIO_CLK_A N/C RESERVED N/C MAD[1] N/C N/C N/C N/C N/C MODE[0] VDDIO33 VSS VSS VDDIO33 SIO_DIN_A N/C MAD[4] MAD[3] MAD[7] MAD[0] N/C RESERVED RESERVED RESERVED N/C N/C VDDIO33 VSS VSS VDD2 VSS VDD2 Pin K14 K15 K16 K17 K19 K20 K21 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L6 L7 L8 L10 L11 L12 L13 L14 L15 L16 L17 L19 L20 L21 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M7 M8 M10 M11 M12 M13 M14 M15 M16 M17 M19 M20 M21 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 N7 N8 N10 N11 N12 N13 N14 N15 N16 N17 N19 N20 Signal VSS VDD2 VSS VDD2 VSS VDDIO33 ISTWI_DATA RESERVED MAD[11] MAD[2] MAD[8] MAD[12] FAULT_LED[3]/ VDDIO33 VSS N/C N/C N/C VDDIO33 VSS VDD2 VSS VDD2 VSS VDD2 VSS VDD2 VSS VSS VDDIO33 MADP[0] N/C MAD[10] VSS VDDIO33 MAD[9] FAULT_LED[2]/ VDDIO33 VSS RESERVED N/C N/C VDDIO33 VSS VSS VDD2 VSS VDD2 VSS VDD2 VSS VDD2 VSS VDDIO33 N/C N/C MAD[6] VSS VDDIO33 MAD[5] FAULT_LED[0]/ RESERVED FAULT_LED[1]/ RESERVED RESERVED N/C VDDIO33 VSS VDD2 VSS VDD2 VSS VDD2 VSS VDD2 VSS VSS VDDIO33 Pin Signal N21 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P6 P7 P8 P10 P11 P12 P13 P14 P15 P16 P17 P19 P20 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R7 R8 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T6 T7 T8 T10 T11 T12 T13 T14 T15 T16 T17 T19 T20 T21 T22 T23 T24 T25 T26 N/C N/C MAD[13] MOE1/ N/C NVSRAM_CS/ RESERVED N/C RESERVED HB_LED/ RESERVED N/C VDDIO33 VSS VSS VDD2 VSS VDD2 VSS VDD2 VSS VDD2 VSS VDDIO33 N/C N/C MAD[15] MWE1/ FLASH_CS/ N/C N/C VDDIO33 VSS N/C N/C N/C VDDIO33 VSS VDD2 VSS VDD2 VSS VDD2 VSS VDD2 VSS VSS VDDIO33 RESERVED N/C BWE[2]/ VSS VDDIO33 MAD[14] RESERVED VDDIO33 VSS RTCK_ICE TDI_ICE N/C VDDIO33 VSS VSS VDD2 VSS VDD2 VSS VDD2 VSS VDD2 VSS VDDIO33 BWE[0]/ TDIODE_VSS MWE0/ VSS VDDIO33 N/C 1. N/C pins are not connected. 22 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. LSISAS1064E Pin Assignments Listed by Pin Number1 (Cont.) Table 2 Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal U1 U2 U3 U4 U5 U6 U7 U8 U10 U11 U12 U13 U14 U15 U16 U17 U19 U20 U21 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V6 V7 V8 V19 V20 V21 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 N/C N/C TCK_ICE TMS_ICE N/C N/C VDDIO33 VSS VDD2 VSS VDD2 VSS VDD2 VSS VDD2 VSS VSS VDDIO33 MAD[19] N/C MCLK BWE[1]/ MOE0/ MADP[1] N/C N/C TDO_ICE GPIO[0] N/C N/C VDDIO33 VSS VSS VDDIO33 MAD[16] ADSC/ ADV/ N/C N/C TDIODE_P TRST_ICE/ N/C GPIO[2] N/C N/C N/C N/C VSS VSS VSS W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIO33 N/C N/C MAD[21] MAD[18] BWE[3]/ MADP[2] GPIO[1] VDDIO33 VSS TRST/ N/C N/C P_TXB_VDD0 P_RXB_VDD0 VDDIO33 P_RXB_VSS1 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 P_RXB_VSS4 VDDIO33 P_TX_VSS6 VDDIO33 VDDIO33 MAD[27] N/C MAD[23] VSS VDDIO33 MAD[17] N/C VDDIO33 VSS PROCMON N/C N/C P_TX_VSS0 P_TX_VSS1 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 P_RX_VSS1 P_TXB_VSS2 P_RXB_VSS2 P_TXB_VDD3 P_RXB_VSS3 P_TXB_VSS4 P_RX_VSS4 P_TXB_VDD5 P_RXB_VDD5 P_RX_VSS6 P_RXB_VSS6 P_TXB_VDD7 P_RXB_VSS7 MADP[3] MAD[22] VSS VDDIO33 MAD[20] GPIO[3] TCK RST/ IDDT P_TX_VDD0 P_RX_VDD0 P_RX_VSS0 P_TXB_VSS1 P_RXB_VDD1 P_TXB_VDD2 P_TX_VSS3 P_RX_VSS3 N/C P_TX_VSS4 P_RXB_VDD4 P_TXB_VSS5 P_RXB_VSS5 P_TXB_VDD6 P_TX_VSS7 P_TXB_VSS7 P_RX_VDD7 MAD[30] MAD[25] MAD[26] MAD[24] N/C TDI TDO TMS P_TXB_VSS0 VSS VSS AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 P_RX_VDD1 P_TX_VDD2 P_RX_VDD2 P_TX_VDD3 P_TXB_VSS3 N/C N/C P_TX_VDD4 P_RX_VDD4 P_TX_VSS5 P_RX_VSS5 P_TX_VDD6 P_RX_VDD6 VSS VSS P_RX_VSS7 VDDIO33 N/C MAD[28] MAD[29] N/C TN/ N/C P_TX_VDD1 VDDIO33 VDDIO33 P_RXB_VSS0 P_TXB_VDD1 P_RX_VSS2 P_RXB_VDD2 VSS VSS N/C P_REFCLK_N VSS VSS P_TX_VDD5 P_RX_VDD5 P_RXB_VDD6 VDDIO33 VDDIO33 VSS P_RXB_VDD7 VDDIO33 MAD[31] VDDIO33 VSS P_TX0N/C P_TX1+ AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 P_TX1P_RX1+ P_RX1P_RX2+ P_TX3P_RX_VDD3 VDDIO33 VDDIO33 N/C P_REFCLK_P VDDIO33 VDDIO33 P_RX4P_TX5+ P_TXB_VSS6 P_RX6+ P_RX6P_TX7+ P_TX7P_RX7+ P_RX7VSS P_TX0+ P_RX0+ P_RX0P_TX2P_TX2+ P_TX_VSS2 P_RX2P_TX3+ P_RX3+ P_RX3P_RXB_VDD3 N/C P_TXB_VDD4 P_TX4P_TX4+ P_RX4+ P_TX5P_RX5+ P_RX5P_TX6P_TX6+ P_TX_VDD7 VDDIO33 VSS 1. N/C pins are not connected. LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 23 of 30 DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. Figure 4 LSISAS1064E 636 EPBGA-T - Top View (Sheet 1 of 2) 24 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. Figure 4 LSISAS1064E 636 EPBGA-T - Top View (Sheet 2 of 2) LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 25 of 30 DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. Package Drawing The LSISAS1064E uses a 636 EPBGA-T package. The package code is 8C. Figure 5 provides the package drawing. 26 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. Figure 5 636-Ball EPBGA-T (8C) Mechanical Drawing (Sheet 1 of 3) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI marketing representative by requesting the outline drawing for package code 8C. LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 27 of 30 DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. Figure 5 636-Ball EPBGA-T (8C) Mechanical (Sheet 2 of 3); Bottom View (Cont.) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI marketing representative by requesting the outline drawing for package code 8C. 28 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. Figure 5 636-Ball EPBGA-T (8C) Mechanical (Sheet 3 of 3); Bottom View (Cont.) vB Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI marketing representative by requesting the outline drawing for package code 8C. LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 29 of 30 DB08-000275-03 May 2006 - Version 2.0 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved. Notes Headquarters LSI Logic Corporation North American Headquarters Milpitas CA Tel: 408.433.8000 LSI Logic Europe Ltd. European Headquarters Bracknell England Tel: 44.1344.413200 Fax: 44.1344.413254 LSI Logic K.K. Headquarters Tokyo Japan Tel: 81.3.5463.7821 Fax: 81.3.5463.7820 AP Doc. No. DB08-000275-03 To receive product literature, visit us at http://www.lsilogic.com. For a current list of our distributors, sales offices, and design resource centers, view our web page located at http://www.lsilogic.com/contacts/index.html. ISO 9000 Certified Purchase of I2C components of LSI Logic Corporation, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C standard Specification as defined by Philips. LSI Logic, the LSI Logic logo design, Fusion-MPT, Gflx, GigaBlaze, Integrated Mirroring, Integrated RAID, and Integrated Striping are trademarks or registered trademarks of LSI Logic Corporation. ARM and Multi-ICE are registered trademarks of ARM Ltd., used under license. PCI-X is a registered trademark of PCI SIG. All other brand and product names may be trademarks of their respective companies. LSI Logic products are not intended for use in life-support appliances, devices, or systems. Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic officer is prohibited. LSI Logic Corporation reserves the right to make changes to any products and services herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase, lease, or use of a product or service from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or of third parties. 30 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller May 2006 Copyright (c) 2004-2006 by LSI Logic Corporation. All rights reserved.