Standard Products QCOTSTM UT8Q512 512K x 8 SRAM Data Sheet February, 2003 FEATURES q 20ns (3.3 volt supply) maximum address access time q Asynchronous operation for compatibility with industrystandard 512K x 8 SRAMs q TTL compatible inputs and output levels, three-state bidirectional data bus q Typical radiation performance - Total dose: 50krads - >100krads(Si), for any orbit, using Aeroflex UTMC patented shielded package INTRODUCTION The QCOTSTM UT8Q512 Quantified Commercial Off-theShelf product is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (E), an active LOW Output Enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected. Writing to the devicei s accomplished by taking Chip Enable one (E) input LOW and Write Enable (W) inputs LOW. Data on the eight I/O pins (DQ0 through DQ 7 ) is then written into the location specified on the address pins (A0 through A18 ). Reading from the device is accomplished by taking Chip Enable one (E) and Output Enable (G) LOW while forcing Write Enable (W) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. - SEL Immune >80 MeV-cm2 /mg - LET TH(0.25) = >10 MeV-cm 2/mg - Saturated Cross Section cm2 per bit, 5.0E-9 - <1E-8 errors/bit-day, Adams 90% geosynchronous heavy ion q Packaging options: - 36-lead ceramic flatpack (3.42 grams) - 36-lead flatpack shielded (10.77 grams) q Standard Microcircuit Drawing 5962-99607 - QML T and Q compliant Clk. Gen. Pre-Charge Circuit Row Select A0 A1 A2 I/O Circuit Column Select A9 CLK Gen. A18 Data Control A12 A13 A14 A15 A16 A17 DQ0 - DQ7 Memory Array 1024 Rows 512x8 Columns A10 A11 A3 A4 A5 A6 A7 A8 The eight input/output pins (DQ0 through DQ 7) are placed in a high impedance state when the device is deselected (E, HIGH), the outputs are disabled (G HIGH), or during a write operation (E LOWand W LOW). E W G Figure 1. UT8Q512 SRAM Block Diagram DEVICE OPERATION A0 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A2 A3 A4 E DQ0 DQ1 VD D V SS DQ2 DQ3 W A5 A6 A7 A8 A9 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 The UT8Q512 has three control inputs called Enable 1 ( E), Write Enable ( W), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). E Device Enable controls device selection, active, and standby modes. Asserting E enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs. NC A18 A17 A16 A15 G DQ7 DQ6 VS S VD D DQ5 DQ4 A14 A13 A12 A11 A10 NC Table 1. Device Operation Truth Table Figure 2. 25ns SRAM Pinout (36) PIN NAMES G W E I/O Mode Mode X1 X 1 3-state Standby X 0 0 Data in Write 1 1 0 3-state Read2 0 1 0 Data out Read A(18:0) Address Notes: 1. "X" is defined as a "don't care" condition. 2. Device active; outputs disabled. DQ(7:0) Data Input/Output READ CYCLE E Enable W Write Enable G Output Enable A combination of W greater than V IH (min) and E less than V IL (max) defines a read cycle. Read access time is measured from the latter of Device Enable, Output Enable, or valid address to valid data output. V DD Power V SS Ground SRAM Read Cycle 1, the Address Access in figure 3a, is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(7:0) after the specified t AVQV is satisfied. Outputs remain active throughout the entire cycle. As long as Device Enable and Output Enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV ). SRAM read Cycle 2, the Chip Enable - Controlled Access in figure 3b, is initiated by E going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified t ETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0). SRAM read Cycle 3, the Output Enable - Controlled Access in figure 3c, is initiated by G going active while E is asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless t AVQV or tETQV have not been satisfied. 2 WRITE CYCLE A combination of W less than VIL (max) and E less than VIL(max) defines a write cycle. The state of G is a "don't care" for a write cycle. The outputs are placed in the high-impedance state when either G is greater than V IH (min), or when W is less than VIL (max). Write Cycle 1, the Write Enable - Controlled Access in figure 4a, is defined by a write terminated by W going high, with E still active. The write pulse width is defined by t WLWH when the write is initiated by W, and by t ETWH when the write is initiated by E. Unless the outputs have been previously placed in the highimpedance state byG, the user must wait t WLQZ before applying data to the nine bidirectional pins DQ(7:0) to avoid bus contention. Write Cycle 2, the Chip Enable - Controlled Access in figure 4b, is defined by a write terminated by the latter of E going inactive. The write pulse width is defined by tWLEF when the write is initiated by W, and by t ETEF when the write is initiated by the E going active. For the W initiated write, unless the outputs have been previously placed in the high-impedance state 3 by G, the user must wait t WLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention. TYPICAL RADIATION HARDNESS Table 2. Typical Radiation Hardness Design Specifications 1 Total Dose 50 krad(Si) nominal Heavy Ion Error Rate2 <1E-8 Errors/Bit-Day Notes: 1. The SRAM will not latchup during radiation exposure under recommended operating conditions. 2. 90% worst case particle environment, Geosynchronous orbit, 100 m ils of Aluminum. ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS ) SYMBOL PARAMETER LIMITS VDD DC supply voltage -0.5 to 4.6V V I/O Voltage on any pin -0.5 to 4.6V TSTG Storage temperature -65 to +150C PD Maximum power dissipation TJ Maximum junction temperature 2 +150C Thermal resistance, junction-to-case3 10C/W DC input current 10 mA JC II 1.0W Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life. 3. Test per MIL-STD-883, Method 1012. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDD Positive supply voltage 3.0 to 3.6V TC Case temperature range (C) screening: -55 to +125C (E) screening: -40 to +125C VIN DC input voltage 0V to V DD 4 DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (-55C to +125C for (C) screening and -40oC to +125oC for (W) screening) (V DD = 3.3V + 0.3) SYMBOL PARAMETER CONDITION MIN MAX 2.0 UNIT V IH High-level input voltage (CMOS) V V IL Low-level input voltage (CMOS) 0.8 V V OL1 Low-level output voltage IOL = 8mA, V DD =3.0V 0.4 V V OL2 Low-level output voltage IOL = 200A,VDD =3.0V 0.08 V VOH1 High-level output voltage IOH = -4mA,VDD =3.0V VOH2 High-level output voltage IOH = -200A,VDD =3.0V CIN 1 Input capacitance = 1MHz @ 0V 10 pF CIO 1 Bidirectional I/O capacitance = 1MHz @ 0V 12 pF IIN Input leakage current VSS < V IN < V DD, VDD = VDD (max) -2 2 A I OZ Three-state output leakage current 0V < VO < V DD -2 2 A -90 90 mA 125 mA 180 mA -55C and 25C -40oC and 25oC 6 6 mA mA +125C 40 mA 2.4 V V DD-0.10 V VDD = VDD (max) G = V DD (max) IOS 2, 3 IDD (OP) Short-circuit output current 0V < VO < V DD Supply current operating @ 1MHz Inputs: VIL = 0.8V, VIH = 2.0V IOUT = 0mA VDD = VDD (max) I DD1(OP) Supply current operating @40MHz Inputs: VIL = 0.8V, VIH = 2.0V IOUT = 0mA VDD = VDD (max) IDD2 (SB) Nominal standby supply current @0MHz Inputs: VIL = VSS IOUT = 0mA E = VDD - 0.5 VDD = VDD (max) VIH = V DD - 0.5V Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 101 9 . 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 5 AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)* (-55C to +125C for (C) screening and -40oC to +125oC for (W) screening) (V DD = 3.3V + 0.3) SYMBOL PARAMETER MIN MAX tAVAV 1 Read cycle time tAVQV Read access time tAXQX Output hold time 3 ns tGLQX G-controlled Output Enable time 0 ns tGLQV G-controlled Output Enable time (Read Cycle 3) 10 ns tGHQZ 2 G-controlled output three-state time 10 ns tETQX 3 E-controlled Output Enable time tETQV 3 E-controlled access time 25 ns E-controlled output three-state time 10 ns tEFQZ 1 ,2 ,4 20 UNIT ns 25 3 ns Notes: * Post-radiation performance guaranteed at 25 C per MIL-STD-883 Method 1019. 1. Functional test. 2. Three-state is defined as a 300mV change from steady-state output voltage (see Figure 3). 3. The ET (enable true) notation refers to the falling edge of E. SEU immunity does not affect the read parameters. 4. The EF (enable false) notation refers to the rising edge of E. SEU immunity does not affect the read parameters. High Z to Active Levels Active to High Z Levels VH - 300mV VLOAD + 300mV } VLOAD { { } VLOAD - 300mV VL + 300mV Figure 3. 3-Volt SRAM Loading 6 ns tAVAV A(18:0) DQ(7:0) Previous Valid Data Valid Data tAVQV tAXQX Assumptions: 1 . E and G < VIL (max) and W > VIH (min) Figure 4a. SRAM Read Cycle 1: Address Access A(18:0) E t ETQV DQ(7:0) tEFQZ tETQX DATA VALID Assumptions: 1. G < V IL (max) and W > V IH (min) Figure 4b. SRAM Read Cycle 2: Chip Enable -Controlled Access t AVQV A(18:0) G tGHQZ tGLQX DATA VALID DQ(7:0) Assumptions: 1 . E< VIL (max) and W > VIH (min) tGLQV Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access 7 AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)* (-55C to +125C for (C) screening and -40oC to +125oC for (E) screening) (V DD = 3.3V + 0.3) SYMBOL PARAMETER MIN MAX UNIT tAVAV 1 Write cycle time 20 ns tETWH Device Enable to end of write 20 ns tAVET Address setup time for write (E - controlled) 0 ns tAVWL Address setup time for write (W - controlled) 0 ns tWLWH Write pulse width 20 ns tWHAX Address hold time for write (W - controlled) 2 ns tEFAX Address hold time for Device Enable (E - controlled) 2 ns tWLQZ 2 W - controlled three-state time tWHQX W - controlled Output Enable time 5 ns tETEF Device Enable pulse width (E - controlled) 20 ns tDVWH Data setup time 15 ns tWHDX2 Data hold time 2 ns tWLEF Device Enable controlled write pulse width 20 ns tDVEF 2 Data setup time 15 ns tEFDX Data hold time 2 ns tAVWH Address valid to end of write 20 ns Write disable time 5 ns tWHWL1 10 Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 101 9 . 1. Functional test performed with outputs disabled (G high). 2 . Three-state is defined as 300mV change from steady-state output voltage (see Figure 3). 8 ns A(18:0) t AVAV2 E tAVWH t ETWH t WHWL W tAVWL t WLWH tWHAX Q(7:0) tWLQZ D(7:0) tWHQX APPLIED DATA Assumptions: 1. G < V IL (max). If G > V IH (min) then Q(8:0) will be in three-state for the entire cycle. 2. G high for t AVAV cycle. tDVWH tWHDX Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access 9 tAVAV 3 A(18:0) tETEF t AVET tEFAX E or t AVET E tETEF tEFAX tWLEF W D(7:0) APPLIED DATA t WLQZ t DVEF Q(7:0) t EFDX Assumptions & Notes: 1. G < V IL (max). If G > V IH (min) then Q(7:0) will be in three-state for the entire cycle. 2. Either E scenario above can occur. 3. G high for t AVAV cycle. Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access CMOS 90% V DD-0.05V 300 ohms 10% V LOAD = 1.55V 10% 0.5V < 5ns 50pF < 5ns Input Pulses Notes: 1. 50pF including scope probe and test socket capacitance. 2. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = V DD/2). Figure 6. AC Test Loads and Input Waveforms 10 DATA RETENTION MODE VDD 50% VDR > 2.0V 50% tR t EFR E Figure 7. Low V DD Data Retention Waveform DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) (1 Second Data Retention Test) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT V DR VDD for data retention 2.0 -- V I DDR 1,2 Data retention current -- 2.0 mA tEFR 1,3 Chip select to data retention time 0 ns tAVAV ns tR1,3 Operation recovery time Notes: 1. E = VDD - .2V, all other inputs = VDR or V SS. 2. Data retention current (I D D R) Tc = 25oC. 3. Not guaranteed or tested. DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) (10 Second Data Retention Test, Tc= -55 o C to +125oC for (C) screening SYMBOL PARAMETER V DD 1 tEFR2, 3 tR2, 3 VDD for data retention Chip select to data retention time Operation recovery time Notes: 1. Performed at VDD (min) and VDD (max). 2. E = VSS , all other inputs = VDR or V SS . 3. Not guaranteed or tested. 11 MINIMUM MAXIMUM UNIT 3.0 3.6 V 0 ns tAVAV ns PACKAGING 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to V SS . 3. Lead finishes are in accordance to MIL-PRF-38535. 4. Lead position and coplanarity are not measured. 5. ID mark is vendor option. 6. Total weight is approx. 3.42 grams Figure 8. 36-pin Ceramic FLATPACK 12 1. All package finishes are per MIL-PRF-38535. 2. Letter designations are for cross-reference to MIL-STD-1835. 3. All leads increase max. limit by 0.003 measured at the center of the flat, when lead finish A (solder) is applied. 4. Total weight is approx. 10.77 g. 5. X-rays are an ineffective test for shielded packages. Figure 9. 36-lead flatpack shielded package 13 ORDERING INFORMATION 512K x 8 SRAM: UT8Q512 - * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow (W) = Extended Industrial Temperature Range Flow (-40o C to +125o C) Package Type: (I) = 36-lead flatpack shielded package (bottom brazed) (U) = 36-lead flatpack package (bottom brazed) = 25ns access time, 3.3V operation 20 = 20ns access time, 3.3V operation -Aeroflex UTMC Core Part Number Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25 C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55C, room temp, and +125C. Radiation neither tested nor guaranteed. 5. 36LBBFP Shielded Package for reduced high rel orders only. 6. Extended Industrial Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -40C to +125 C. Radiation neither tested nor guaranteed. 14 512K x 8 SRAM: SMD 5962 - 99607 ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (X) = 36-lead flatpack shielded package (bottom-brazed) (U) = 36-lead ceramic flatpack (bottom-brazed) Class Designator: (T) = QML Class T (Q) = QML Class Q Device Type 01 = 25ns access time, 3.3V operation, Mil-Temp 02 = 25ns access time, 3.3V operation, Extended Industrial Temp (-40oC to +125oC) 03 = 20ns access time, 3.3V operation, Mil-Temp 04 = 20ns access time, 3.3V operation, Extended Industrial Temp (-40oC to +125oC) Drawing Number: 99607 Total Dose: (D) = 1E4 (10krad)(Si)) (P) = 3E4 (30krad)(Si)) (contact factory) (L) = 5E4 (50krad(Si)) (contact factory) Federal Stock Class Designator: No options Notes: 1 .Lead finish (A,C, or X) must be specified. 2 .If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3 .Total dose radiation must be specified when ordering. 15