HEF4044BTD-T - NXP Semiconductors / Philips Semiconductors

1. General description

The HEF4044B is a quad R/S latch with 3-state outputs, with a common output enab le

input (OE). Each latch has an active LOW set inp ut (1S to 4S), an active LOW re set inpu t

(1R to 4R) and an active HIGH 3-state output (1Q to 4Q).

When OE is HIGH, the latch outpu t (nQ) is d etermined by the nR and nS input s as shown

in Table 3. When OE is LOW, the latch outputs are in the high impedance OFF-state. OE

does not affect the state of the latch. The high impedance of f-state fea ture allows common

bussing of the outputs.

It operates over a recommended VDD power supply r ange of 3 V to 15 V refer enced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is

also suita ble for use over the industrial (−40 °C to +85 °C) temperature range.

2. Features

Fully static operation

5 V, 10 V, and 15 V parametric ratings

St andardized symmetrical output characte ristics

Operates across the full industrial temperature range −40 °C to +85 °C

Complies with JEDEC standard JESD 13-B

3. Applications

Four-bit storage with outpu t enable

4. Ordering information

HEF4044B

Quad R/S latch with 3-state outputs

Rev. 09 — 15 December 2009 Product data sheet

Table 1. Ordering information

All types operate from

−

C to +85

Type number Package

Name Description Version

HEF4044BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

HEF4044BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 09 — 15 December 2009 2 of 13

NXP Semiconductors HEF4044B

Quad R/S latch with 3-state outputs

5. Functional diagram

6. Pinning information

6.1 Pinning

Fig 1. Functional diagram Fig 2. Logic diagram for one latch

001aae621

3-STATE

OUTPUTS

5OE

001aai5

to other latches

Fig 3. Pin configuration

HEF4044B

4Q V

n.c. 4S

1S 4R

1R 1Q

OE 3R

2R 3S

2S 3Q

001aae622

Product data sheet Rev. 09 — 15 December 2009 3 of 13

NXP Semiconductors HEF4044B

Quad R/S latch with 3-state outputs

6.2 Pin description

7. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance state.

8. Limiting values

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.

[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.

Table 2. Pin description

Symbol Pin Description

n.c. 2 not connected

1S to 4S 3, 7, 11, 15 set input (active LOW)

1R to 4R 4, 6, 12, 14 reset input (active LOW)

OE 5 common output enable input

VSS 8 ground supply voltage

1Q to 4Q 13, 9, 10, 1 3-state buffered latch output

VDD 16 supply voltage

Table 3. Function table[1]

Input Output

OE nS nR nQ

LXXZ

HLHH

HXLL

HHHlatched

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +18 V

IIK input clamping curre nt VI<−0.5 V or VI>V

DD + 0.5 V - ±10 mA

VIinput voltage −0.5 VDD + 0.5 V

IOK output clamping current VO<−0.5 V or VO>V

DD + 0.5 V - ±10 mA

II/O input/output current - ±10 mA

IDD supply current - 50 mA

Tstg storage temperature −65 +150 °C

Tamb ambient temperature −40 +85 °C

Ptot total power dissipation Tamb −40 °C to +85 °C

DIP16 package [1] -750mW

SO16 package [2] -500mW

per output - 100 mW

Product data sheet Rev. 09 — 15 December 2009 4 of 13

NXP Semiconductors HEF4044B

Quad R/S latch with 3-state outputs

9. Recommended operating conditions

10. Static characteristics

Table 5. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air −40 - +85 °C

Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 μs/V

VDD = 10 V - - 0.5 μs/V

VDD = 15 V - - 0.08 μs/V

Table 6. Static characteristics

VSS = 0 V; VI = VSS or VDD unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = 25 °C Tamb = 85 °CUnit

Min Max Min Max Min Max

VIH HIGH-level input voltage |IO| < 1 μA 5 V 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - V

15 V 11.0 - 11.0 - 11.0 - V

VIL LOW-level input voltage |IO| < 1 μA 5 V - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 V

15 V - 4.0 - 4.0 - 4.0 V

VOH HIGH-level output voltage |IO| < 1 μA 5 V 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - V

VOL LOW-level output voltage |IO| < 1 μA 5 V - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 V

IOH HIGH-lev el ou tp ut current VO = 2.5 V 5 V −1.7 - −1.4 - −1.1 - mA

VO = 4.6 V 5 V −0.52 - −0.44 - −0.36 - mA

VO = 9.5 V 10 V −1.3 - −1.1 - −0.9 - mA

VO = 13.5 V 15 V −3.6 - −3.0 - −2.4 - mA

IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA

VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA

VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA

IIinput leakage current 15 V - ±0.3 - ±0.3 - ±1.0 μA

IOZ OFF-state output current nQ output HIGH;

returned to VDD

15 V - 1.6 - 1.6 - 12.0 μA

nQ output LOW;

returned to VSS

15 V - 1.6 - 1.6 - 12.0 μA

Product data sheet Rev. 09 — 15 December 2009 5 of 13

NXP Semiconductors HEF4044B

Quad R/S latch with 3-state outputs

11. Dynamic characteristics

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

IDD supply current IO = 0 A 5 V - 20 - 20 - 150 μA

10 V - 40 - 40 - 300 μA

15 V - 80 - 80 - 600 μA

CIinput capacitance - - - 7.5 - - pF

Table 6. Static characteristics …continued

VSS = 0 V; VI = VSS or VDD unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = 25 °C Tamb = 85 °CUnit

Min Max Min Max Min Max

Table 7. Dynamic characteristics

VSS = 0 V; Tamb = 25

C; for test circuit see Figure 6; unless otherwise speci fied.

Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit

tPHL HIGH to LOW

propagation delay nR to nQ; see

Figure 4 5 V [1] 63 ns + (0.55 ns/pF)CL- 90 185 ns

10 V 29 ns + (0.23 ns/pF)CL-4080ns

15 V 22 ns + (0.16 ns/pF)CL-3060ns

tPLH LOW to HIGH

propagation delay nS to nQ;

see Figure 4 5 V [1] 63 ns + (0.55 ns/pF)CL- 90 180 ns

10 V 29 ns + (0.23 ns/pF)CL-4080ns

15 V 22 ns + (0.16 ns/pF)CL-3060ns

tttransition time see Figure 4 5 V [1] 10 ns + (1.00 ns/p F)C L- 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL-3060ns

15 V 6 ns + (0.28 ns/pF)CL-2040ns

tPHZ HIGH to OFF-state

propagation delay OE → nQ;

see Figure 5 5 V - 50 100 ns

10 V - 30 60 ns

15 V - 25 50 ns

tPLZ LOW to OFF-state

propagation delay OE → nQ;

see Figure 5 5 V - 30 60 ns

10 V - 25 45 ns

15 V - 20 40 ns

tPZH OFF-state to HIGH

propagation delay OE → nQ;

see Figure 5 5 V - 50 100 ns

10 V - 25 50 ns

15 V - 20 40 ns

tPZL OFF-state to LOW

propagation delay OE → nQ;

see Figure 5 5 V - 50 95 ns

10 V - 25 45 ns

15 V - 20 35 ns

tWpulse width nS input LOW;

minimum width;

see Figure 4

5 V 3015- ns

10 V 2010- ns

15 V 16 8 - ns

nR input LOW;

minimum width;

see Figure 4

5 V 3015- ns

10 V 2010- ns

15 V 16 8 - ns

Product data sheet Rev. 09 — 15 December 2009 6 of 13

NXP Semiconductors HEF4044B

Quad R/S latch with 3-state outputs

12. Waveforms

Table 8. Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf

≤

20 ns; Tamb = 25

Symbol Parameter VDD Typical formula for PD (μW) where:

PDdynamic power

dissipation 5 V PD = 1300 × fi + Σ(fo × CL) × VDD2fi = input frequency in MHz,

fo = output frequency in MHz,

CL = output load capacitance in pF,

VDD = supply voltage in V,

Σ(fo × CL) = sum of the outputs.

10 V PD = 5200 × fi + Σ(fo × CL) × VDD2

15 V PD = 12900 × fi + Σ(fo × CL) × VDD2

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig 4. Set (nS) and reset (nR) inputs pulse width and propagation delay to latch output (nQ) and

output nQ transition time

001aai54

output nQ

input nS

tTHL

tTLH

VOL

VOH

0 V

tWtW

90 %

10 %

input nR

0 V

10 %

90 %

tPLH tPHL

Product data sheet Rev. 09 — 15 December 2009 7 of 13

NXP Semiconductors HEF4044B

Quad R/S latch with 3-state outputs

Measurement points are given in Table 9.

Fig 5. Output enable (OE) to latch output (nQ) enable time (tPZL and tPZH) and disable time (tPLZ and tPHZ)

001aag35

tPLZ

tPHZ

outputs off outputs onoutputs on

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

OE input

VDD

VSS

VDD

VSS

tPZL

tPZH

Table 9. Measurement points

Supply voltage Input Output

VDD VIVMVMVXVY

5 V to 15 V VDD or VSS 0.5VDD 0.5VDD 0.1VDD 0.9VDD

Product data sheet Rev. 09 — 15 December 2009 8 of 13

NXP Semiconductors HEF4044B

Quad R/S latch with 3-state outputs

a. Input waveform

b. Test circuit

Test and measurement data is given in Table 10.

Definitions test circuit:

DUT = Device Under Test.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

Fig 6. Test circuit for measuring switching times

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aaj78

001aaj91

EXT

DUT

Table 10. Test data

Supply voltage Input Load VEXT

VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH

5 V to 15 V VDD ≤ 20 ns 50 pF 1 kΩopen VDD GND

Product data sheet Rev. 09 — 15 December 2009 9 of 13

NXP Semiconductors HEF4044B

Quad R/S latch with 3-state outputs

13. Package outline

Fig 7. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05 0.2542.54 7.62 8.25

7.80

10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051

0.021

0.015

0.014

0.009

1.25

0.85

0.049

0.033

0.77

0.73

0.26

0.24

0.14

0.12 0.010.1 0.3 0.32

0.31

0.39

0.33 0.030.17 0.02 0.13

IP16: plastic dual in-line package; 16 leads (300 mil) SOT38

-4

Product data sheet Rev. 09 — 15 December 2009 10 of 13

NXP Semiconductors HEF4044B

Quad R/S latch with 3-state outputs

Fig 8. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8 1.27 6.2

5.8

0.7

0.6

0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15 0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

O16: plastic small outline package; 16 leads; body width 3.9 mm SOT109

-1

Product data sheet Rev. 09 — 15 December 2009 11 of 13

NXP Semiconductors HEF4044B

Quad R/S latch with 3-state outputs

14. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4044B_9 20091215 Product data sheet - HEF4044B_8

Modifications: •Section 12 “Waveforms” Table 10 “Test data” tPLZ and tPZL value updated.

HEF4044B_8 20091127 Product data sheet - HEF4044B_7

HEF4044B_7 20090721 Product data sheet - HEF4044B_6

HEF4044B_6 20081111 Product data sheet - HEF4044B_5

HEF4044B_5 20080812 Product data sheet - HEF4044B_4

HEF4044B_4 20080717 Product data sheet - HEF4044B_CNV_3

HEF4044B_CNV_3 19950101 Product specification - HEF4044B_CNV_2

HEF4044B_CNV_2 19950101 Produ ct specification - -

Product data sheet Rev. 09 — 15 December 2009 12 of 13

NXP Semiconductors HEF4044B

Quad R/S latch with 3-state outputs

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short dat a sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

15.3 Disclaimers

General — In formation in this document is believed to be accurate and

reliable. However, NXP Semiconduct ors does not give any repr esenta tions or

warranties, expressed or impli ed, as to the accuracy or completeness of such

information and shall have no liability for th e co nsequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and with out

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are no t designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ra tings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other co nditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may af fect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between inf ormation in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Not hing in this document may be interpret ed or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patent s or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

15.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respective ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

NXP Semiconductors HEF4044B

Quad R/S latch with 3-state outputs

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 December 2009

Document identifier: HEF4044B_9

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 3

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

9 Recommended operating conditions. . . . . . . . 4

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

16 Contact information. . . . . . . . . . . . . . . . . . . . . 12

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13