Memory Cell Array
512 x 256 x 16
Column Gate
I/O Buffer
9
8
512
256
16
256x16
CS
OE
I/O1 I/O16
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
LB
UB
OE, WE
X Decoder
Control
Logic
CS,LB,UB
Control
Logic
Y Decoder
Address Buffer
■ DESCRIPTION
The SRM2AW216LLBT1/7 is a 131,072 words x 16-bit asynchronous, random access memory on a monolithic
CMOS chip. Its very low standby power requirement makes it ideat for applications requiring non-volatile syorage
with back-up batteries. The asynchronous and static nature of the memory requires no external clock or refreshing
circuit. It is possible to contorol the date width by the data byte control. Both the Input and output ports are TTL
compatible and 3-state output allows easy expansion of memory capacity. The temperature range of the
SRM2AW216LLBT1/7 is from –40 to 85°C, and it is suitable for the industrial products.
■ FEATURES
● Fast Access time........................ 100ns (at 1.8V) / 70ns (at 2.2V)
● Low supply current ..................... LL Version
● Completely static........................ No clock required
● Supply voltage............................ 1.8V to 2.85V
● TTL compatible inputs and outputs
● 3-state output with wired-OR capability
● Non-volatile storage with back-up batteries
● Package ..................................... SRM2AW216LLBT TFBGA-48 pin (Tape CSP)
2M-bit Static RAM
PF988-02
SRM2AW216LLBT
1/7
■ BLOCK DIAGRAM
●Super Low Voltage Operation and Low Current Consumption
●Access Time 100ns (1.8V) / 70ns (2.2V)
●131,072 Words x 16-bit Asynchtonous
●Wide Temperature Range
Super Low Voltage
Operation
Products
SRM2AW216LLBT
1/7
2
■ PIN CONFIGURATION
A0 to A16
WE
OE
CS
LB
UB
I/O1 to 16
VDD
VSS
NC
Address Input
Write Enable
Output Enable
Chip Select
LOWER Byte Enable
UPPER Byte Enable
Data I/O
Power Supply (1.8V to 2.85V)
Power Supply (0V)
No connection
A
B
C
D
E
F
G
H
213456
LB OE A0
A3
A5
NC
NC
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CS
I/O2
I/O4
I/O5
I/O6
WE
A11
NC
NCNC
I/O1
I/O3
VDD
VSS
I/O7
I/O8
UB
I/O9
I/O10 I/O11
I/O12I/O12
I/O13
I/O14
NC
A8
I/O15
I/O16
VSS
VDD
TFBGA-48 pin
Top view (Looking through part)
SRM2AW216LLBT
■ PIN DESCRIPTION
SRM2AW216LLBT
1/7
3
Supply voltage
Input voltage
Input/Output voltage
Power dissipation
Operating temperature
Storage temperature
Soldering temperature and time
Parameter VDD
VI
VI/O
PD
Topr
Tstg
Tsol
Symbol Ratings Unit
– 0.5 * to 3.6
– 0.5 * to VDD + 0.3
– 0.5 * to VDD + 0.3
0.5
– 40 to 85
– 65 to 150
260°C, 10s (at lead)
(VSS=0V)
* VI,VI/O (Min.) = –3.0V (Pulse width is 50ns)
V
V
V
W
°C
—
(Ta = –40 to 85 °C)
Parameter
Supply voltage
Input voltege
Symbol
VDD
VSS
VIH
VIL
V
V
V
V
* if pulse width is less than 50ns it is – 3.0V
Min.
1.8
0.0
0.8VDD
– 0.3*
Typ.
2.0
0.0
–
–
Max.
2.2
0.0
VDD+0.3
0.3
Min.
2.2
0.0
2.0
– 0.3 *
Typ.
2.5
0.0
–
–
Max.
2.85
0.0
VDD+0.3
0.3
Unit
Parameter Symbol Conditions Unit
Input leakage current
Standby supply current
Average operating current
Operating Supply Current
High level output voltage
ILI
ILO
VOH
Low level output voltage VOL
IDDS
IDDS1
IDDA
IDDA1
IDDO
µA
(VSS =0V, Ta = –40 to 85 °C)
VDD = 1.8 to 2.2V
VDD = 1.8 to 2.2V VDD = 2.2 to 2.85V
VDD = 2.2 to 2.85V
VI = 0 to VDD
LB and UB = VIH or
CS = VIH or WE = VIL
or OE = VIH, VI/O = 0 to VDD
CS ≥ VDD – 0.2V
LB and UB = VIH or
CS = VIH
Output leakage current
–1.0
Min. Typ. *1 Max.
– 1.0
µA–1.0 – 1.0
mA– – 0.8
µA
–
–
–
–
–40 to 85 °C
–40 to 70 °C
–40 to 40 °C
25 °C
–
–
–
0.15
15
10
3.0
0.6
mA–2035
mA– 2.5 4
mA– 2.5 4
V
V
–
VDD–0.2
–
–
–
–
–
–
–
–
–
0.2
–1.0
Min. Typ.*2 Max.
– 1.0
–1.0 – 1.0
– – 1.0
–
–
–
–
–
–
–
0.2
20
13.5
4
0.8
–3545
–35
–35
1.8
VDD–0.2
–
–
–
–
–
–
–
–
0.4
0.2
*1 : Typical values are measured at Ta = 25°C and VDD = 2.0V
*2 : Typical values are measured at Ta = 25°C and VDD = 2.5V
(Ta = 25°C, f = 1MHz)
Parameter Symbol Unit
Conditions
Address Capacitance
Input Capacitance
I/O Capacitance
CADD
CI
CI/O
VI = 0V
VI = 0V
VI/O = 0V
Max.Min. Typ.
Note : This parameter is made by the inspection data of sample, not of all products
VI = VIL or VIH
II/O = 0mA, tcyc = Min.
VI = VIL or VIH
II/O = 0mA, tcyc = 1µs
VI = VIL or VIH
II/O = 0mA
–
–
–
–
–
–
8
8
10
pF
pF
pF
LL
VDD
≥
2.2V, IOH = -0.5mA
IOH = -100µA
VDD
≥
2.2V, IOH = 0.5mA
IOH = 100µA
■ ABSOLUTE MAXIMUM RATINGS
■ DC RECOMMENDED OPERATING CONDITIONS
● Terminal Capacitance
■ ELECTRICAL CHARACTERISTICS
● DC Electrical Characteristics
SRM2AW216LLBT
1/7
4
Unit
SRM2AW216LLBT
1
SRM2AW216LLBT
7
1.8 to 2.2V 2.2 to 2.85V
Min.
100
–
–
–
–
10
–
5
–
5
–
10
Max.
–
100
100
60
60
–
40
–
40
–
40
–
Min.
70
–
–
–
–
5
–
0
–
0
–
10
Max.
–
70
70
40
40
–
30
–
30
–
30
–
Parameter Symbol Conditions
(V
SS
= 0V, Ta = –40 to 85°C)
Read cycle time
Address access time
CS access time
OE access time
LB, UB access time
CS output set time
CS output floating
LB, UB output set time
LB, UB output floating
OE output set time
OE output floating
Output hold time
t
RC
t
ACC
t
ACS
t
OE
t
AB
t
CLZ
t
CHZ
t
BLZ
t
BHZ
t
OLZ
t
OHZ
t
OH
1
1
1
1
1
2
2
2
2
2
2
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
SRM2AW216LLTT
1
SRM2AW216LLBT
7
1.8 to 2.2V 2.2 to 2.85V
100
85
85
0
80
85
0
50
0
–
5
–
–
–
–
–
–
–
–
–
40
–
70
60
60
0
55
60
0
35
0
–
5
–
–
–
–
–
–
–
–
–
30
–
Parameter Symbol Conditions
(V
SS
= 0V, Ta = –40 to 85°C)
Write cycle time
Chip select time (CS)
Address enable time
Address setup time
Write pulse width
LB, UB select time
Address hold time
Data setup time
Data hold time
WE output floating
WE output set time
t
WC
t
CW
t
AW
t
AS
t
WP
t
BW
t
WR
t
DW
t
DH
t
WHZ
t
OW
1
1
1
1
1
1
1
1
1
2
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min. Max. Min. Max.
1TTL
I/O C
L
*1 Test Conditions
1. Input pulse level : 0.3V to 2.2V (2.2V to 2.85V)
0.3V to 0.8VDD (1.8V to 2.2V)
2. tr = tf = 5ns
3. Input and output timing reference levels :1.1V (2.2V to 2.85V)
:1/2VDD (1.8V to 2.2V)
4. Output load : CL =50pF (Includes Jig Capacitance)
*2 Test Conditions
1. Input pulse level : 0.3V to 2.2V (2.2V to 2.85V)
0.3V to 0.8VDD (1.8V to 2.2V)
2. tr = tf = 5ns
3. Input timing reference levels :1.1V (2.2V to 2.85V)
:1/2VDD (1.8V to 2.2V)
4. Output timing reference levels : ±200mV (the level displaced from stable
output voltage level)
5. Output load :CL = 5pF (Includes Jig Capacitance)
❍ Write Cycle
● AC Electrical Characteristics
❍ Read Cycle
1TTL
I/O C
L
SRM2AW216LLBT
1/7
5
Note : *1 During read cycle time, WE is to be "High" level.
*2 In write cycle time that is controlled by CS, output buffer is to be "Hi-Z" state if OE is "Low" level.
*3 When output buffer is in output state, be careful that do not input the opposite signals to the output data.
❍ Read Cycle
*1
A0 to 16
LB, UB
OE
I/O1 to 16
(Dout)
t
RC
t
ACC
t
CHZ
t
ACS
t
CLZ
t
AB
t
BLZ
t
BHZ
t
OE
t
OHZ
t
OLZ
❍ Write Cycle 1 (CS Control)
*2, *3
t
WC
t
AW
t
CW
t
DW
t
WR
t
AS
t
DH
t
WHZ
❍ Write Cycle 3 (UB, LB Control)
*3
t
WC
t
WP
t
BW
t
DW
t
WR
t
AS
t
DH
❍ Write Cycle 2 (WE Control)
*3
A0 to 16
CS
LB, UB
WE
I/O1 to 16
(Dout)
(Din)
t
WC
t
CW
t
WP
t
DW
t
BW
t
WR
t
AS
t
WHZ
t
OW
t
DH
A0 to 16
CS
LB, UB
WE
I/O1 to 16
(Dout)
(Din)
LB, UB
WE
CS
A0 to 16
CS
I/O1 to 16
(Dout)
(Din)
t
OH
Parameter Symbol Conditions Min. Typ. Max. Unit
Data retention supply voltage
Data retention curren
Data hold time
Operation recovery time
V
DDR
I
DDR
t
CDR
t
R
1.5
–
–
–
–
0
5
–40 to 85°C
–40 to 70°C
–40 to 40°C
+25°C
2.85
18
12
3.5
0.7
–
–
V
µA
ns
ms
(V
SS
= 0V, Ta = –40 to 85°C)
V
DDR
= 3.0V, CS ≥ V
DD
– 0.2V
or LB and UB ≥ V
DD
– 0.2V
CS ≤ 0.2V
–
–
–
–
0.2
–
–
LL
Data retention timing (CS Control)
V
DD
CS
t
CDR
t
R
V
DDR
≥ 1.5V
CS ≥V
DD
– 0.2V
1.8V1.8V
Data hold time
V
IL
V
IL
0.8xV
DD
0.8xV
DD
● DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY
(for just 3.0V operation)
● Timing Chart
SRM2AW216LLBT
1/7
6
● Reading data
It is possible to control the data width by LB and UB pins.
(1) Reading data from lower byte
Data is able to be read when the address is set while holding CS ="Low", OE= "Low", LB ="Low" and WE =
"High".
(2) Reading data from upper byte
Data is able to be read when the address is set while holding CS = "Low", OE = "Low", UB = "Low" and WE
="High".
(3) Reading data from both bytes
Data is able to be read when the address is set while holding CS = "Low", OE ="Low", UB ="Low", LB =
"Low", and WE = "High"
Since I/O pins are in "Hi-Z" state when OE = "High", the data bus line can be used for any other objective, then
access time apparently is able to be cut down.
● Writing data
(1) Writing data into lower byte
There are the following three ways of writing data into memory.
i) Hold WE = "Low", UB = "High" and LB = "Low", set address and give "Low" pulse to CS.
ii) Hold CS = "Low", UB = "High" and LB = "Low", set address and give "Low" pulse to WE.
iii) Set address and give "Low" pulse to CS, UB = "High" and "Low" pulse to WE, LB.
Anyway, data on I/O pins are latched up into the memory cell during CS ="Low", WE ="Low", and LB = "Low".
(2) Writing data into upper byre
There are the following three ways of writing data into the memory.
i) Hold WE = "Low", LB = "High" and UB = "Low", set address and give "Low" pulse to CS.
ii) Hold CS = "Low", LB = "High" and UB = "Low", set address and give "Low" pulse to WE.
iii) Set address and give "Low" pulse to CS, LB = "High" and "Low" pulse to WE, UB.
Anyway, data on I/O pins are latched up into the memory cell during CS = "Low", WE = "Low", and UB = "Low".
(3)Writing data into both bytes
There are the following three ways of writing data into the memory.
i) Hold WE = "Low", LB and UB = "Low", set address and give "Low" pulse to CS.
ii) Hold CS = "Low", LB and UB = "Low", set address and give "Low" pulse to WE.
iii) Set address give "Low" pulse to both pins of LB and UB, "Low" pulse to CS and "Low" pulse to WE.
CS
H
L
L
L
L
L
L
L
L
X
H
L
H
L
L
H
L
X
LB X
H
H
L
L
H
L
L
X
UB X
X
X
X
X
L
L
L
H
OE X
X
L
L
L
H
H
H
H
WE I/O1 to 8 I
DD
MODE I
DDS,
I
DDS1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
High-Z
High-Z
Data In
High-Z
Data In
DataOut
High-Z
Data Out
High-Z
I/O9 to 16
High-Z
High-Z
High-Z
Data In
Data In
High-Z
DataOut
Data Out
High-Z
Not Selected
Output disable
Lower Byte Write
Upper Byte Write
All Byte Write
Lower Byte Read
Upper Byte Read
All Byte Read
Output disable
X : Hi
g
h or Low
■ FUNCTIONS
● Truth Table
SRM2AW216LLBT
1/7
7
Anyway, data on I/O pins are latched up into the memory cell during CS = "Low" , WE = "Low", UB and LB =
"Low". As DATA I/O pins are in "Hi-Z" when any of CS is "High", OE or LB, UB are "High" level, the contention
on the data bus can be avoided. But during I/O pins are in the output state, the data that is opposite to the
output data should not be given.
When CS "High" or LB, UB = "High" level. the chip is in the standby mode which has rataining data operation.
In this case data I/O pins are Hi-Z, and all inputs of addresses, WE, OE and all input data are inhibited. When
CS, LB and UB level are in the range over VDD–0.2V, there is almost no current flow except through the high
resistance parts of the memory.
● Data retention at low voltage
In case of the data retention in the stadby mode, the power supply can be gone down till the specified voltage.
But it is impossible to write or read in this mode.
● Standby mode
SRM2AW216LLBT
1/7
8
654 321
A
B
C
D
E
F
G
H
654321
A
B
C
D
E
F
G
H
BOTTOM VIEW
SIDE VIEW
TOP VIEW
SRAM Die
Base Tape
INDEX
0.75 T yp.
1.0 Max.
0.75 T yp.
8.0 ± 0.2
7.0 ± 0.2
φ0.35±0.05
TFBGA-48 pin
Unit : mm
■ PACKAGE DIMENSIONS
SRM2AW216LLBT
1/7
9
■ CHARACTERISTICS CURVES
Under Measurement
SRM2AW216LLBT
1/7
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko
Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out
of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation
that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual
property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this
material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the
subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an
export license from the Ministry of International Trade and Industry or other approval from another government agency.
© Seiko Epson Corporation 1999 All right reserved.
ELECTRONIC DEVICES MARKETING DIVISION
IC Marketing & Engineering Group
ED International Marketing Department I (Europe & U.S.A.)
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone : 042-587-5812 FAX : 042-587-5564
ED International Marketing Department II (Asia)
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone : 042-587-5814 FAX : 042-587-5110
