© 2009 Microchip Technology Inc. DS11177F-page 1
MCP606/7/8/9
Features
• Low Input Offset Voltage: 250 µV (maximum)
• Rail-to-Rail Output
• Low Input Bias Current: 80 pA (maximum at
+85°C)
• Low Quiescent Current: 25 µA (maximum)
• Power Supply Voltage: 2.5V to 6.0V
• Unity-Gain Stable
• Chip Select (CS) Capability: MCP608
• Industrial Temperature Range: -40°C to +85°C
• No Phase Reversal
• Available in Single, Dual and Quad Packages
Typical Applications
• Battery Power Instruments
• High-Impedance Applications
• Strain Gauges
• Medical Instruments
• Test Equipment
Design Aids
• SPICE Macro Models
• FilterLab® Software
• Mindi™ Circuit Designer & Simulator
• Analog Demonstration and Evaluation Boards
• Application Notes
Typical Application
Description
The MCP606/7/8/9 family of ope rationa l amplifiers (op
amps) from Microchip Technology Inc. are unity-gain
stable with low offset voltage (250 µV, maximum).
Performance characteristics include rail-to-rail output
swing capability and low input bias current (80 pA at
+85°C, maximum). These features make this family of
op amps well suited for single-supply, precision,
high-impedance, battery-powered applications.
The single is available i n standard 8-lead PDIP, SOIC
and TSSOP packages, as well as in a SOT-23-5
package. The single MCP608 with Chip Select (CS) is
offered in the standard 8-lead PDIP, SOIC and TSSOP
packages. The dual MCP607 is offered in the standard
8-lead PDIP, SOIC and TSSOP packages. Finally, the
quad MCP609 is offered in the standard 14-lead PDIP,
SOIC and TSSOP packages. All devices are fully
specified from -40°C to +85°C, with power supplies
from 2.5V to 6.0V.
Package Types
Low-Side Battery Current Sensor
RF
To Load
2.5V
RG
5kΩ50 kΩTo Load
VOUT
RSEN
10Ω(VLM)
(VLP)
IL
to
6.0V
VOUT VLM I+LRSEN RFRG
⁄
()=
MCP606
VIN+
VIN–
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
NC
NC
PDIP, SOIC,TSSOP
PDIP, SOIC,TSSOP PDIP, SOIC,TSSOP
PDIP, SOIC,TSSOP
SOT-23-5
VIN+
VSS VIN–
1
2
3
5
4
VDD
VOUT
VINA+
VINA–
VSS
VOUTB
VINB–
1
2
3
4
8
7
6
5VINB+
VDD
VOUTA
VIN+
VIN–
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
CS
NC
VINA+
VINA–
VDD
VIND–
VIND+
1
2
3
4
14
13
12
11 VSS
VOUTD
VOUTA
VINB–
VINB+
VOUTB
VINC+
VINC–
5
6
7
10
9
8VOUTC
MCP606 MCP606
MCP607 MCP608
MCP609
2.5V to 6.0V Micropower CMOS Op Amp
MCP606/7/8/9
DS11177F-page 2 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS11177F-page 3
MCP606/7/8/9
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD –V
SS ........................................................................7.0V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+, VIN–) ††........ VSS –1.0VtoV
DD +1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD +0.3V
Difference Input Voltage ...................................... |VDD –V
SS|
Output Short Circuit Current ................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature .................................–65° C to +150° C
Maximum Junction Temperature (TJ).........................+150° C
ESD Protection On All Pins (HBM; MM).............. ≥ 3 kV; 200V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”.
DC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS =GND, T
A=+25°C, V
CM =V
DD/2,
VOUT ≈VDD/2, VL = VDD/2, RL = 100 kΩ to VL, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -250 — +250 µV
Input Offset Drift with Temperature ΔVOS/ΔTA—±1.8—µV/°CT
A = -40°C to +85°C
Power Supply Rejection Ratio PSRR 80 93 — dB
Input Bias Current and Impedance
Input Bias Current IB—1—pA
At Temperature IB——80pAT
A = +85°C
Input Offset Bias Current IOS —1—pA
Common Mode Input Impedance ZCM —10
13||6 — Ω||pF
Differential Input Impedance ZDIFF —10
13||6 — Ω||pF
Common Mode
Common Mode Input Range VCMR VSS –0.3 V
DD – 1.1 V CMRR ≥ 75 dB
Common Mode Rejection Ratio CMRR 75 91 — dB VDD = 5V, VCM = -0.3V to 3.9V
Open-Loop Gain
DC Open-Loop Gain
(Large-signal) AOL 105 121 — dB RL = 25 kΩ to VL,
VOUT = 50 mV to VDD –50mV
DC Open-Loop Gain
(Large-signal) AOL 100 118 — dB RL = 5 kΩ to VL,
VOUT = 0.1V to VDD –0.1V
Output
Maximum Output Voltage Swing VOL, VOH VSS +15 — V
DD –20 mV R
L = 25 kΩ to VL,
0.5V input overdrive
VOL, VOH VSS +45 — V
DD –60 mV R
L = 5 kΩ to VL,
0.5V input overdrive
Linear Output Voltage Range VOUT VSS +50 — V
DD –50 mV R
L = 25 kΩ to VL,
AOL ≥ 105 dB
VOUT VSS +100 — V
DD – 100 mV RL = 5 kΩ to VL,
AOL ≥ 100 dB
Output Short Circuit Current ISC —7—mAV
DD = 2.5V
ISC —17—mAV
DD = 5.5V
Power Supply
Supply Voltage VDD 2.5 — 6.0 V
Quiescent Current per Amplifier IQ— 18.7 25 µA IO = 0
Note 1: All parts with date codes Nove mber 2007 and later have been screened to ensure operation at VDD = 6.0V. However,
the other minimum and maximum specifications are measured at 2.5V and 5.5V.
MCP606/7/8/9
DS11177F-page 4 © 2009 Microchip Technology Inc.
AC CHARACTERISTICS
MCP608 CHIP SELECT CHARACTERISTICS
FIGURE 1-1: Timing Diagram for the CS
Pin on the MCP608.
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS =GND, T
A=+25°C, V
CM =V
DD/2,
VOUT ≈VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL= 60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 155 — kHz
Phase Margin PM — 62 — ° G = +1 V/V
Slew Rate SR — 0.08 — V/µs
Noise
Input Noise Voltage Eni —2.8—µV
P-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —38—nV/√Hz f = 1 kHz
Input Noise Current Density ini —3—fA/√Hz f = 1 kHz
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS =GND, T
A=+25°C, V
CM =V
DD/2,
VOUT ≈VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL= 60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logic Threshold, Low VIL VSS —0.2V
DD V
CS Input Current, Low ICSL -0.1 0.01 — µA CS = 0.2VDD
CS High Specifications
CS Logic Threshold, High VIH 0.8 VDD —V
DD V
CS Input Current, High ICSH —0.010.1 µACS = VDD
CS Input High, GND Current ISS -2 -0.05 — µA CS = VDD
Amplifier Output Leakage, CS High IO(LEAK) —10—nACS = VDD
CS Dynamic Specifications
CS Low to Amplifier Output Turn-on Time tON — 9 100 µs CS = 0.2VDD to VOUT = 0.9 VDD/2,
G = +1 V/V, RL = 1 kΩ to VSS
CS High to Amplifier Output Hi-Z tOFF —0.1— µsCS = 0.8VDD to VOUT = 0.1 VDD/2,
G = +1 V/V, RL = 1 kΩ to VSS
CS Hysteresis VHYST —0.6— VV
DD = 5.0V
CS
VOUT
ISS
ICS
VIL VIH
tON tOFF
-50 nA -50 nA
-18.7 µA
-50 nA -50 nA
Hi-Z Hi-Z
(typical) (typical) (typical)
(typical) (typical)
© 2009 Microchip Technology Inc. DS11177F-page 5
MCP606/7/8/9
TEMPERATURE CHARACTERISTICS
1.1 Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-3. The bypass
capacitors are laid out according to the rules discussed
in Section 4.5 “Supply Bypass”.
FIGURE 1-2: AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
FIGURE 1-3: AC and DC Test Circuit for
Most Inverting Gain Conditions.
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 — +85 °C
Operating Temperature Range TA-40 — +125 °C Note 1
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT23 θJA — 220.7 — °C/W
Thermal Resistance, 8L-PDIP θJA —89.3— °C/W
Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W
Thermal Resistance, 8L-TSSOP θJA — 139 — °C/W
Thermal Resistance, 14L-PDIP θJA —70—°C/W
Thermal Resistance, 14L-SOIC θJA —95.3— °C/W
Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W
Note 1: The MCP606/7/8/9 operate over this extended temperature range, but with reduced performance. In any case, the
Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
VDD
RGRF
RNVOUT
VIN
VDD/2
1µF
CLRL
VL
0.1 µF
MCP60X
VDD
RGRF
RNVOUT
VDD/2
VIN
1µF
CLRL
VL
0.1 µF
MCP60X
MCP606/7/8/9
DS11177F-page 6 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS11177F-page 7
MCP606/7/8/9
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA=+25°C, V
CM =V
DD/2, VOUT ≈VDD/2,
VL = VDD/2, RL= 100 kΩ to VL, CL= 60 pF, and CS is tied low.
FIGURE 2-1: Input Offset V oltage at
VDD =5.5V.
FIGURE 2-2: Input Offset V oltage at
VDD =2.5V.
FIGURE 2-3: Quiescent Current vs.
Power Supply Voltage.
FIGURE 2-4: Input Offset Voltage Drift
Magnitude at VDD =5.5V.
FIGURE 2-5: Input Offset Voltage Drift
Magnitude at VDD =2.5V.
FIGURE 2-6: Quiescent Current vs.
Ambient Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provide d for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified pow er supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
16%
-250
-200
-150
-100
-50
0
50
100
150
200
250
Input Offset Voltage (µV)
Percentage of Occurances ( )
1200 Samples
VDD = 5.5V
0%
2%
4%
6%
8%
10%
12%
14%
16%
-250
-200
-150
-100
-50
0
50
100
150
200
250
Input Offset Voltage (µV)
Percentage of Occurances ( )
1200 Samples
VDD = 2.5V
0
2
4
6
8
10
12
14
16
18
20
22
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Quiescent Current
per Amplifier (µA)
TA
= +85°C
TA
= +25°C
TA = -40°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
-8-6-4-202468
Input Offset Voltage Drift (µV/°C)
Percentage of Occurances
206 Samples
VDD = 5.5V
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
-8 -6 -4 -2 0 2 4 6 8
Input Offset Voltage Drift (µV/°C)
Percentage of Occurances
206 Samples
VDD = 2.5V
12
14
16
18
20
22
24
-50 -25 0 25 50 75 100
Ambient Temperature (°C)
Quiescent Current
per Amplifier (µA)
VDD = 5.5V
VDD = 2.5V
MCP606/7/8/9
DS11177F-page 8 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA=+25°C, V
CM =V
DD/2, VOUT ≈VDD/2,
VL = VDD/2, RL= 100 kΩ to VL, CL= 60 pF, and CS is tied low.
FIGURE 2-7: Input Offset Voltage vs.
Ambient Temperature.
FIGURE 2-8: Open-Loop Gain and Phase
vs. Frequency.
FIGURE 2-9: Channel-to-Channel
Separation (MCP607 and MCP609 only).
FIGURE 2-10: Input Offset Voltage vs.
Common Mode Input Voltage.
FIGURE 2-11 : Gain Bandwid th Product,
Phase Margin vs. Ambient Temperature.
FIGURE 2-12: Input Noise Voltage Density
vs. Frequency.
0
100
200
300
400
500
-50-25 0 255075100
Ambient Temperature (°C)
Input Offset Voltage (µV)
VDD =2.5V
VDD = 5.5V
Representative Part
-20
0
20
40
60
80
100
120
Frequency (Hz)
Open-Loop Gain (dB)
-225
-180
-135
-90
-45
0
45
90
Open-Loop Phase (°)
Gain
Phase
RL = 25 kΩ
0.01 10.1 10 1k100 10k 1M100k
80
90
100
110
120
130
140
1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
Channel to Channel
Separation (dB)
Referred to Input
100 100k10k1k
-20
0
20
40
60
80
100
120
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
TA = +85°C
TA = +25°C
TA = -40°C
VDD = 5.5V
0
20
40
60
80
100
120
140
160
-50 -25 0 25 50 75 100
Ambient Temperature (°C)
Gain Bandwidth Product
(kHz)
0
10
20
30
40
50
60
70
80
Phase Margin (°)
Phase Margin
GBWP
VDD = 5.0V
10
100
1000
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
Input Noise Voltage Density
(nV/√Hz)
0.1 1 10 100 1k 10k 100k
© 2009 Microchip Technology Inc. DS11177F-page 9
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA=+25°C, V
CM =V
DD/2, VOUT ≈VDD/2,
VL = VDD/2, RL= 100 kΩ to VL, CL= 60 pF, and CS is tied low.
FIGURE 2-13: Input Bias Current, Input
Offset Current vs. Ambient Temperature.
FIGURE 2-14: DC Open-Loop Gain vs.
Load Resistance.
FIGURE 2-15: CMRR, PSRR vs.
Frequency.
FIGURE 2-16: Input Bias Current, Input
Offset Current vs. Common Mode Input Voltage.
FIGURE 2-17: DC Open-Loop Gain vs.
Power Supply Voltage.
FIGURE 2-18: CMRR, PSRR vs. Ambient
Temperature.
0.1
1
10
100
25 30 35 40 45 50 55 60 65 70 75 80 85
Ambient Temperature (°C)
Input Bias and Offset
Currents
(pA)
IB
| IOS |
VDD = 5.5V
VCM = VDD
100
105
110
115
120
125
130
135
1.E+02 1.E+03 1.E+04 1.E+05
Load Resistance (Ω)
DC Open-Loop Gain (dB)
VDD = 2.5V
VDD = 5.5V
100 100k10k1k
0
20
40
60
80
100
120
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04
Frequency (Hz)
CMRR and PSRR (dB)
PSRR-
PSRR+
CMRR
0.1 1 10 100 1k 10k
-10
0
10
20
30
40
50
60
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias and Offset
Currents
(pA)
IB
IOS
TA = 85°C
VDD = 5.5V
90
100
110
120
130
140
150
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
DC Open-Loop Gain (dB)
RL = 25 kΩ
75
80
85
90
95
100
-50 -25 0 25 50 75 100
Ambient Temperature (°C)
CMRR and PSRR (dB)
CMRR
PSRR
MCP606/7/8/9
DS11177F-page 10 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA=+25°C, V
CM =V
DD/2, VOUT ≈VDD/2,
VL = VDD/2, RL= 100 kΩ to VL, CL= 60 pF, and CS is tied low.
FIGURE 2-19: Output Voltage Headroom
vs. Output Current Magnitude.
FIGURE 2-20: Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-21: Slew Rate vs. Ambient
Temperature.
FIGURE 2-22: Output Voltage Headroom
vs. Ambient Temperature at RL=5kΩ.
FIGURE 2-23: The MCP606/7/8/9 Show
No Phase Reversal.
FIGURE 2-24: Output Short Circuit Current
Magnitude vs. Ambient Temperature.
1
10
100
1000
0.1 1 10 100
Output Current (mA)
Output Voltage Headroom
(mV)
VDD = 2.5V
VDD = 5.5V
VDD - VOH
VOL - VSS
0.1
1
10
1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
Maximum Output Voltage
Swing (V)
VDD = 2.5V
100 100k10k1k
VDD = 5.5V
0.00
0.02
0.04
0.06
0.08
0.10
0.12
-50 -25 0 25 50 75 100
Ambient Temperature (°C)
Slew Rate (V/µs)
Low to High
High to Low
0
5
10
15
20
25
30
35
40
-50 -25 0 25 50 75 100
Ambient Temperature (°C)
Output Voltage Headroom
(mV)
RL = 5 kΩ
VDD = 5.5V
VDD = 2.5V
VDD - VOH
VOL - VSS
-1
0
1
2
3
4
5
6
Time (100 µs/div)
Input and Output Voltages (V)
VOUT
VIN
G = +2 V/V
VDD = 5.0V
0
5
10
15
20
25
-50-25 0 255075100
Ambient Temperature (°C)
Output Short Circuit Current
Magnitude (mA)
+ISC , VDD
= 2.5V
| -ISC |, VDD
= 2.5V
+ISC , VDD = 5.5V
| -ISC |, VDD = 5.5V
© 2009 Microchip Technology Inc. DS11177F-page 11
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA=+25°C, V
CM =V
DD/2, VOUT ≈VDD/2,
VL = VDD/2, RL= 100 kΩ to VL, CL= 60 pF, and CS is tied low.
FIGURE 2-25: Large-signa l, Non-inverting
Pulse Response.
FIGURE 2-26: Small-signal, Non-inverting
Pulse Response.
FIGURE 2-27: Chip Select (CS) Hysteresis
(MCP608 only).
FIGURE 2-28: Large-signal, Inverting
Pulse Response.
FIGURE 2-29: Small-signal, Inverting Pulse
Response.
FIGURE 2-30: Amplifier Output Response
Times vs. Chip Select (CS) Pulse (MCP608
only).
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (50 µs/div)
Output Voltge (V)
VDD = 5.0V
Time (50 µs/div)
Output Voltage (20 mV/div)
VDD = 5.0V
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.00.51.01.52.02.53.03.54.04.55.0
CS Input Voltage (V)
Internal CS Switch Output (V)
Amplifier Output Active
Amplifier Output Hi-Z
VDD = 5.0V
Hysteresis
CS Input
High to Low
CS Input
Low to High
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (50 µs/div)
Output Voltage (V)
VDD = 5.0V
Time (50 µs/div)
Output Voltage (20 mV/div)
RL = 25 kΩ
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (5 µs/div)
Output Voltage (V)
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
Chip Select Voltage (V)
CS
VOUT
Output
Hi-Z
Output
Hi-Z
Output Enabled
G = +1 V/V
RL = 1 kΩ to VSS
MCP606/7/8/9
DS11177F-page 12 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA=+25°C, V
CM =V
DD/2, VOUT ≈VDD/2,
VL = VDD/2, RL= 100 kΩ to VL, CL= 60 pF, and CS is tied low.
FIGURE 2-31: Measured Input Current vs.
Input Voltage (below VSS).
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
© 2009 Microchip Technology Inc. DS11177F-page 13
MCP606/7/8/9
3.0 PIN DESCRIPTIONS
Description s of the pi ns are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Analog Outputs
The output pins are low-impedance voltage sources.
3.2 Analog Inputs
The non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
3.3 Chip Select Digital Input
The Chip Select (CS) pin is a Schmitt-triggered, CMOS
logic input. It is used to place the MCP608 op amp in a
Low-power mode, with the out put(s) in a Hi-Z state.
3.4 Power Supply Pins
The positive power supply pin (VDD) is 2.5V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the output pins are at voltages
between VSS and VDD; while the input pins are at
voltages between VSS – 0.3V and VDD +0.3V.
Typically, these parts are used in a single-supply
(positive) configuration. In this case, VSS is connected
to ground and VDD is connected to the supply. VDD will
need bypass capacitors .
MCP606
MCP607 MCP608 MCP609 Symbol Description
PDIP, SOIC,
TSSOP SOT-23-5
61161V
OUT, VOUTA Output (op amp A)
24222V
IN–, VINA– Inverting Input (op amp A)
33333V
IN+, VINA+ Non-inverting Input (op amp A)
75874V
DD Positive Power Supply
——5—5V
INB+ Non-inverting Input (op amp B)
——6—6V
INB– Inverting Input (op amp B)
——7—7V
OUTB Output (op amp B)
————8V
OUTC Output (op amp B)
————9V
INC– Inverting Input (op amp C)
————10V
INC+ Non-inverting Input (op amp C)
424411V
SS Negative Power Supply
————12V
IND+ Non-inverting Input (op amp D)
————13V
IND– Inverting Input (op amp D)
————14V
OUTD Output (op amp D)
———8—CS
Chip Select
1, 5, 8 — — 1, 5 — NC No Internal Connection
MCP606/7/8/9
DS11177F-page 14 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS11177F-page 15
MCP606/7/8/9
4.0 APPLICATIONS INFORMATION
The MCP606/7/8/9 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process
These op amps are unity-gain stable and suitable for a
wide range of general purpose applications.
4.1 Rail-to-Rail Inputs
4.1.1 PHASE REVERSAL
The MCP606/7/8/9 op amp is designed to prevent
phase reversal when the inpu t pins exceed the sup ply
voltages. Figure 2-23 shows the input voltage
exceeding the supply voltage without any phase
reversal.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damag e and/or improper operation
of these op amps, the circuit they are in must li mit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resi stors R1 and R2 also limit
the current through D1 and D2.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, current through the
diodes D1 and D2 needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-31. Applications that are
high impedance may need to limit th e useable voltage
range.
4.1.3 NORMAL OPERATION
The input stage of the MCP606/7/8/9 op amps use a
PMOS input stage. It operates at low common mode
input voltage (V
CM
), including ground. WIth this
topology, the device operates with V
CM
up to V
DD
–1.1V
and 0.3V below V
SS
.
Figure 4-3 shows a unity gain buffer . Since VOUT is the
same voltage as the inverting input, VOUT must be kept
below VDD–1.2V for correct operation.
FIGURE 4-3: Unity Gain Buffer ha s a
Limited VOUT Range.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage Bond
Pad VIN–
V1R1
VDD
D1
R1>VSS – (minimum expected V1)
2mA
R2>VSS – (minimum expected V2)
2mA
V2R2
D2
R3
MCP60X
VOUT
+
–
VIN
MCP60X
MCP606/7/8/9
DS11177F-page 16 © 2009 Microchip Technology Inc.
4.2 Rail-to-Rail Output
There are two specifications that describe the
output-swing capability of the MCP606/7/8/9 family of
op amps. The first specification (Maximum Output
Voltage Swing) defines the absolute maximum swing
that can be achieved under the specified load
conditions. For instance, the output voltage swings to
within 15 mV of the negative rail with a 25 kΩ load to
VDD/2. Figure 2-23 shows how the output voltage is
limited when the input goes beyond the linear region of
operation.
The second specification that describes the output-
swing capability of these amplifiers (Linear Output
V oltage Range) defines the maximum output swing that
can be achieved while the amplifie r still operates in its
linear region. To verify linear operation in this range, the
large-signal DC Open-Loop Gain (AOL) is measured at
points inside the supply rails. The measurement must
meet the specified AOL conditions in the specification
table.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage-feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain-peaking in th e frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
FIGURE 4-4: Output Resistor, RISO
stabilizes large capacitive loads.
Figure 4-5 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN=+2V/V).
FIGURE 4-5: Recommended RISO V alues
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable . Bench evaluati on and simula-
tions with the MCP606/7/8/9 SPICE macro model are
helpful.
4.4 MCP608 Chip Select
The MCP608 is a single op amp with Chip Select (CS).
When CS is pulled high, the supply current drops to
50 nA (typical) and flows through the CS pin to VSS.
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS low, the amplifier
is enabled. The CS pin has an internal 5 MΩ (typical)
pull-down resistor conne cted to VSS, so it will go lo w if
the CS pins is left floating. Figure 1-1 shows the output
voltage and supply current response to a CS pulse.
4.5 Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single-supply) should ha ve a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with other nearby analog parts.
VIN
RISO VOUT
CL
MCP60X
100
1000
10000
10 100 1000 10000
Normalized Load Capacitance; CL/GN (F)
Recommended R ISO (Ω)
10p 10n1n100p
100
10k
1k
GN = +1
GN = +2
GN ≥ +4
© 2009 Microchip Technology Inc. DS11177F-page 17
MCP606/7/8/9
4.6 Unused Op Amps
An unused op amp in a quad package (MCP609)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
FIGURE 4-6: Unused Op Amps.
4.7 PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 10 12Ω. A 5V difference woul d
cause 5 pA of current to flow, which is greater than the
MCP606/7/8/9 family’s bias current at +25°C (1 pA,
typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensi tive pin s (or trace s). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in Figure 4-7.
FIGURE 4-7: Example Guard Ring Layout
for Inverting Gain.
1. Non-inverting Gain and Unity-gain Buffer:
a) Connect the non-inverting pi n (VIN+) to the
input with a wire that does not touch the
PCB surface.
b) Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
2. Inverting Gain and Transimpedance Gain
(convert current to voltage, such as photo
detectors) amplifiers:
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases th e guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
4.8 Application Circuits
4.8.1 LOW-SIDE BATTERY CURRENT
SENSOR
The MCP606/7/8/9 op amps can be used to sen se the
load current on the low-side of a battery using the
circuit in Figure 4-8. In this circuit, the current from the
power supply (minus th e current required to power the
MCP606) flows through a sense resistor (RSEN), which
converts it to voltage. This is gained by the the amplifier
and resistors, RG and RF. Since the non-inverting input
of the amplifier is at the load’s negative supply (VLM),
the gain from RSEN to VOUT is RF/RG.
FIGURE 4-8: Low Side Battery Current
Sensor.
Since the input bias curre nt and input offset voltage of
the MCP606 are low, and the input is capable of
swinging below ground, there is very little error
generated by the amplifier. The quiescent current is
very low, which helps conserve battery power. The
rail-to-rail output makes it possible to read very low
currents.
VDD
VDD
R1
R2
VDD
VREF
VREF VDD R2
R1R2
+
-------------------
⋅
=
¼ MCP609 (A) ¼ MCP609 (B)
Guard Rin g
VSS
VIN-V
IN+
VOUT VLM I+LRSEN RFRG
⁄
()=
RF
To Load
2.5V
RG
5kΩ50 kΩTo Load
VOUT
RSEN
10Ω(VLM)
(VLP)
IL
to
6.0V
MCP606
MCP606/7/8/9
DS11177F-page 18 © 2009 Microchip Technology Inc.
4.8.2 PHOTODIODE AMPLIFIERS
Sensors that produce an output current and have high
output impedance can be connected to a
transimpedance amplifier. The transimpedance
amplifier convert s the current into volt age. Photodiodes
are one sensor that produce an output current.
The key op amp characteristics that are needed for
these circuits are: low input offset voltage, low input
bias current, high input impedance and an input
common mode range that includes ground. The low
input offset voltage and low input bias current support
a very low voltage drop across the photodiode; this
gives the best photodiode linearity. Since the
photodiode is biased at ground, the op amp’s input
needs to function well both above and below ground.
4.8.2.1 Photo-Voltaic Mode
Figure 4-9 shows a transimpedance amplifier with a
photodiode (D 1) biased in the Photo-voltaic mode (0V
across D1), which is used for precision photodiode
sensing.
As light impinges on D1, charge is genera ted, causing
a current to flow in the reverse bias direction of D1. The
op amp’s negative feedback forces the voltage across
the D1 to be nearly 0V. Resistor R2 converts the current
into voltage. Capacitor C2 limits the bandwidth and
helps stabilize the circuit when D1’s junction
capacitance is large.
FIGURE 4-9: Photodiode (in Photo-volt aic
mode) and Transimpedance Amplifier.
4.8.2.2 Photo-Conductive Mode
Figure 4-9 shows a transimpedance amplifier with a
photodiode (D1) bi ased in the Photo-co nductive mode
(D1 is reverse biased), which is used for high-speed
applications.
As light impinges on D1, charge is genera ted, causing
a current to flow in the reverse bias direction of D1.
Placing a negative bias on D1 significantly redu ces its
junction capacitance, which allows the circuit to
operate at a much higher speed. This reverse bias also
increases the dark current and current noise, however.
Resistor R2 convert s the current into voltage. Cap acitor
C2 limits the bandwidth and helps stabilize the circuit
when D1’s junction capacitance is large.
FIGURE 4-10: Photodiode (in Photo-
conductive mode) and Transimpedance
Amplifier.
4.8.3 TWO OP AMP INSTRUMENTATION
AMPLIFIER
The two op amp instrumentation amplifier shown in
Figure 4-11 serves the function of taking the difference
of two input voltages, level-shifting it and gaining it to
the output. This configuration is best suited for higher
gains (i.e., gain > 3 V/V). The reference voltag e (VREF)
is typically at mid-supply (VDD/2) in a single-supply
environment.
FIGURE 4-11 : Two Op Amp
Instrumentation Amplifier.
The key specifications that make the MCP606/7/8/9
family appropriate for this application circuit are low
input bias current, low offset voltage and high
common-mode rejection.
VOUT ID1R2
=
R2
D1
VOUT
Light
C2
VDD
ID1
MCP606
VOUT ID1R2
=
R2
D1
VOUT
Light
C2
VDD
ID1
VB
VB0
<
MCP606
VOUT V1V2
–()1R1
R2
------ 2R1
RG
----------++
⎝⎠
⎜⎟
⎛⎞
VREF
+=
R2
R1VOUT
V2
VREF
R1
R2
V1
RG
½
MCP607
½
MCP607
© 2009 Microchip Technology Inc. DS11177F-page 19
MCP606/7/8/9
4.8.4 THREE OP AMP
INSTRUMENTATION AMPLIFIER
A classic, three op amp instrumentation amplifier is
illustrated in Figure 4-12. The two input op amps
provide differential signal gain and a common mode
gain of +1. The output op amp is a difference amplifier,
which converts its input signal from differential to a sin-
gle ended output; it rejects common mode signals at its
input. The gain of this circuit is simply adjusted with one
resistor (RG). The reference voltage (VREF) is typically
referenced to mid-supply (VDD/2) in single-supply
applications.
FIGURE 4-12: Three Op Amp
Instrumentation Amplifier.
4.8.5 PRECISION GAIN WITH GOOD
LOAD ISOLATION
In Figure 4-13, the MCP606 op amps, R1 and R2
provide a high gain to the input signal (VIN). The
MCP606’s low offset voltage makes this an accurate
circuit.
The MCP601 is configured as a unity-gain buffer. It
isolates the MCP606’s output from the load, increasing
the high-gain stage’s precision. Since the MCP601 has
a higher output current, with the two amplifiers being
housed in separate packages, there is minimal change
in the MCP606’s offset voltage due to loading effect.
FIGURE 4-13: Precision Gain with Good
Load Isolation.
VOUT V1V2
–()12R2
RG
---------+
⎝⎠
⎜⎟
⎛⎞
R4
R3
------
⎝⎠
⎜⎟
⎛⎞VREF
+=
R2VREF
V1
R4
R3
R2
RG
VOUT
V2
R4
R3
½
MCP607
½
MCP607
MCP606
VOUT VIN 1R
2R1
⁄
+()=
R2
R1
VOUT
VIN MCP601
MCP606
MCP606/7/8/9
DS11177F-page 20 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS11177F-page 21
MCP606/7/8/9
5.0 DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP606/7/8/9 fam ily of op amps.
5.1 SPICE Macro Model
The latest SPICE macro model for the MCP606/7/8/9
op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2 FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, th e
FilterLab d esign tool provides fu ll schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, whic h can be
used with the macro model to simulate actual filter
performance.
5.3 Mindi™ Circuit Designer &
Simulator
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power-management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
Circuit Designer & Simulator can be downloaded to a
personal computer or workstation.
5.4 Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparasion
reports. Helpful links are also provided for Datasheets,
Purchase, and Sampling of Microchip parts.
5.5 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools.
Two of our boards that are especially useful are:
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
• 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N
SOIC14EV
5.6 Application Notes
The following Microchip Application Notes are avail-
able on the Microchip web site at www.microchip. com/
appnotes and are recommended as supplemental
reference resources.
•ADN003: “Select the Right Operational Amp lifier
for your Filtering Circuits”, DS21821
•AN722: “Operational Amplifier T opologies and DC
Specifications”, DS00722
•AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
•AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
•AN990: “Analog Se nsor Conditioning Circuits –
An Overview”, DS00990
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
MCP606/7/8/9
DS11177F-page 22 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS11177F-page 23
MCP606/7/8/9
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
5-Lead SOT-23 (MCP606)Example:
XXNN SB25
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP606
I/P256
0722
MCP606
I/SN0722
256
MCP606
I/P 256
0936
MCP606I
SN 0936
256
3
e
OR
OR
3
e
8-Lead TSSOP Example:
XXXX
YYWW
NNN
606
I936
256
MCP606/7/8/9
DS11177F-page 24 © 2009 Microchip Technology Inc.
Package Marking Information (Continued)
14-Lead TSSOP (MCP609) Example:
XXXXXXXX
YYWW
NNN
609IST
0936
256
14-Lead PDIP (300 mil) (MCP609)Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
MCP609-I/P
0722256
MCP609
0936256
I/P
3
e
OR
14-Lead SOIC (150 mil) (MCP609)Example:
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX MCP609ISL
0722256
MCP609
0936256
I/SL^^
OR
3
e
© 2009 Microchip Technology Inc. DS11177F-page 25
MCP606/7/8/9
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MCP606/7/8/9
DS11177F-page 30 © 2009 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2009 Microchip Technology Inc. DS11177F-page 31
MCP606/7/8/9
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DS11177F-page 32 © 2009 Microchip Technology Inc.
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© 2009 Microchip Technology Inc. DS11177F-page 35
MCP606/7/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP606/7/8/9
DS11177F-page 36 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS11177F-page 37
MCP606/7/8/9
APPENDIX A: REVISION HISTORY
Revision F (September 2009)
The following is the list of modificatio ns:
1. Corrected RL text in Figure 2-22 in Section 2.0
“Typical Performance Curves”.
2. Corrected devices’ pins in Table 3-1
(Section 3.0 “Pin Descriptions”).
3. Updated Section 6.0 “Packaging Informa-
tion”. Updated package outline drawings.
Revision E (March 2008)
The following is the list of modificatio ns:
1. Increased maximum operating V DD.
2. Added test circuits.
3. Updated performance curves.
4. Added Figure 2-31.
5. Added Section 4.1.1 “Phase Reversal”,
Section 4.1.2 “Input Voltage and Current
Limits”, ad Section 4.1.3 “Normal Opera-
tion”.
6. Updated Section 5.0 “Design Aids”
7. Updated Section 6.0 “Packaging Informa-
tion”. Updated package outline drawings.
Revision D (February 2005)
The following is the list of modificatio ns:
1. Added Section 3.0 “Pin Descriptions”.
2. Updated Section 4.0 “Applications Information”.
3. Added Section 4.3 “Capacitive Loads”
4. Updated Section 5.0 “Design Aids” to include
FilterLab® and to point to the latest SPICE
macro model.
5. Corrected and updated Section 6.0 “Packaging
Information”.
6. Added Appendix A: “Revision History”.
Revision C (January 2001)
• Undocumented changes
Revision B (May 2000)
• Undocumented changes
Revision A (January 2000)
• Original Release of this Document.
MCP606/7/8/9
DS11177F-page 38 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS11177F-page 39
MCP606/7/8/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device MCP606 = Single Op Amp
MCP606T = Single Op Amp
Tape and Reel (SOIC, TSSOP)
MCP607 = Dual Op Amp
MCP607T = Dual Op Amp
Tape and Reel (SOIC, TSSOP)
MCP608 = Single Op Amp with CS
MCP608T = Single Op Amp with CS
Tape and Reel (SOIC, TSSOP)
MCP609 = Quad Op Amp
MCP609T = Quad Op Amp
Tape and Reel (SOIC, TSSOP)
Temperature Range I = -40°C to +85°C
Package OT = Plastic SOT - 23, 5-lead
P = Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC ( 3.90 mm body), 8-lead
SL = Plastic SOIC (3.90 mm body), 14-lead
ST = Plastic TSSOP, 8-lead, 14-lead
Examples:
a) MCP606-I/P: Industrial Temperature,
8LD PDIP package.
b) MCP606-I/SN: Industrial Temperature,
8LD SOIC package.
c) MCP606T-I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC package.
d) MCP606-I/ST: Industrial Temperature,
8LD TSSOP package.
e) MCP606T -I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT-23 package.
a) MCP607-I/P: Industrial Temperature,
8LD PDIP package.
b) MCP607T -I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC package.
a) MCP608-I/SN: Industrial Temperature,
8LD SOIC package.
b) MCP608T -I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC package.
a) MCP609-I/P: Industrial Temperature,
14LD PDIP package.
b) MCP609T -I/SL: Tape and Reel,
Industrial Temperature,
14LD SOIC package.
PART NO. X/XX
PackageTemperature
Range
Device
MCP606/7/8/9
DS11177F-page 40 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS11177F-page 41
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defen d, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts
allow unauthorized access to you r software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:200 2 certif ication for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design cent ers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and
analog product s. In addition, Microchip ’s quality system for the desig n
and manufacture of development systems is ISO 9001:2000 certified.
DS11177F-page 42 © 2009 Microchip Technology Inc.
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03/26/09
