1
©2009 Integrated Device Technology, Inc.
JANUARY 2009
DSC 5681/5
IDT70P5258ML
IDT70P525ML
IDT70V525ML
Features
◆◆
◆◆
◆High-speed access
– Industrial: 55ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT70P5258ML and IDT70P525ML
Active: 54mW (typ.)
Standby: 7.2
µ
W (typ.)
– IDT70V525ML
Active: 450mW (typ.)
Standby: 250
µ
W (typ.)
Functional Block Diagram
HIGH-SPEED
8K x 16 TriPort
STATIC RAM
R/
W
P1
BE
0P1,
BE
1P1
OE
P1
I/O
0P1
-I/O
15P1
A
0P1
-A
11P1
R/
W
P2
CE
P2
OE
P2
I/O
0P2
-I/O
15P2
A
0P2
-A
11P2
Memory
Array
PORT 1
I/O
Control
PORT 1
Address
Decode
R/
W
P1
OE
P1
PORT 2
I/O
Control
PORT 3
I/O
Control
5681 drw 01
R/
W
P3
CE
P3
OE
P3
I/O
0P3
-I/O
15P3
A
0P3
-A
11P3
,
PORT 2
Address
Decode
PORT 3
Address
Decode
Interrupt
Control
CE
P2,
CE
P3
OE
P2,
OE
P3
R/W
P2,
R/W
P3
INT
P1 - P2
INT
P1 - P3
BE
0P1,
BE
1P1
INT
P3 - P1
INT
P2 - P1
BE
0P1,
BE
1P1
◆◆
◆◆
◆TriPort architecture allows simultaneous access to the
memory from all three ports
◆◆
◆◆
◆Fully asynchronous operation from each of the three
ports: P1, P2, and P3
◆◆
◆◆
◆IDT70P5258 supports 3.0V and 1.8V I/O's
◆◆
◆◆
◆Available in 144-ball 0.5mm-pitch fpBGA
◆◆
◆◆
◆Industrial temperature range (–40°C to +85°C)
◆◆
◆◆
◆Greeen parts available, see ordering information
6.42
IDT70X525XML Preliminary
Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range
2
NOTES:
1. VDDQ for 70P5258.
Pin Configurations(1,2,3)
Description
The IDT70X525X is a high-speed 8K x 16 TriPort Static RAM designed
to be used in systems where multiple access into a common RAM is
required. This TriPort Static RAM offers increased system performance
in multiprocessor systems that have a need to communicate in real time and
also offers added benefit for high-speed systems in which multiple access
is required in the same cycle.
The IDT70X525X is also designed to be used in systems where on-
chip hardware port arbitration is not needed. This part lends itself to those
systems which cannot tolerate wait states or are designed to be able to
externally arbitrated or withstand contention when more than one port
simultaneously accesses the same TriPort RAM location.
The IDT70X525X provides three independent ports with separate
control, address, and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. It is the user’s
responsibility to ensure data integrity when simultaneously accessing the
same memory location from mutiple ports. An automatic power down
feature, controlled by BE0 and BE1 on Port 1 and CE on Port 2 and on
Port 3, permits the on-chip circuitry of each port to enter a very low power
standby power mode.
The IDT70X525X is packaged in a 144-ball 0.5mm-pitch fpBGA.
J9 J10
K9 K10
J1 J2 J3 J4
K1 K2 K3 K4
J5 J6 J7 J8
K5 K6 K7 K8
A
2P1
A
1P1
A
0P1
A
3P1
A
10P1
I/O
4P1
I/O
0P1
I/O
3P1
I/O
2P1
I/O
1P1 J11 J12
K11 K12
V
DD
V
DD
Vss
Vss
Vss Vss V
DD
VssVss V
DD
V
DD
V
DD
C10
A9
D9
C9
B9
D10
A10
B10
E9 E10
F9 F10
G9 G10
H9 H10
D8
C8C7
B8
A8
D7
B7
A7
B6
C6
D6
A5
B5
C5
D5
A4
B4
C4
D4
A3
B3
C3
D3D2
C2
B2
A2A1
B1
C1
D1
E1 E2 E3 E4
F1 F2 F3 F4
G1 G2 G3 G4
H1 H2 H3 H4
A6
E5 E6 E7 E8
F5 F6 F8
G5 G6 G7 G8
H5 H6 H7 H8
F7
5681 drw 02
,
12/19/03
Vss
VssVss
Vss
Vss
Vss
R/W
P2
OE
P2
V
DD(1)
NC
V
DD
C12
A11
D11
C11
B11
D12
A12
B12
E11 E12
F11 F12
G11 G12
H11 H12
Vss
Vss
NC
I/O
15P2
I/O
12P2
I/O
11P2
I/O
14P2
I/O
13P2
I/O
8P2
I/O
4P2
I/O
0P2
I/O
3P2
I/O
10P2
I/O
7P2
I/O
9P2
I/O
6P2
I/O
5P2
I/O
2P2
I/O
1P2
I/O
15P3
I/O
12P3
I/O
11P3
I/O
14P3
I/O
13P3
I/O
8P3
I/O
4P3
I/O
0P3
I/O
3P3
I/O
10P3
I/O
7P3
I/O
9P3
I/O
6P3
I/O
5P3
I/O
2P3
I/O
1P3
R/W
P3
OE
P3
A
5P2
A
8P2
A
11P2
A
6P2
A
2P2
A
1P2
A
0P2
A
3P2
A
7P2
A
9P2
A
4P2
A
10P2
A
5P3
A
8P3
A
11P3
A
6P3
A
2P3
A
1P3
A
0P3
A
3P3
A
7P3
A
9P3
A
4P3
A
10P3
CE
P3
CE
P2
V
DD(1)
V
DD(1)
V
DD
V
DD
Vss
VssVss
Vss
VssVssVss
V
DD
V
DD(1)
V
DD
VssVssVss V
DD
V
DD
A
5P1
A
8P1
A
11P1
A
6P1
A
7P1
A
9P1
A
4P1
BE
0P1
R/W
P1
OE
P1
I/O
15P1
I/O
12P1
I/O
11P1
I/O
14P1
I/O
13P1
I/O
8P1
I/O
10P1
I/O
7P1
I/O
9P1
I/O
6P1
I/O
5P1
V
DD
L9 L10
M9 M10
L1 L2 L3 L4
M1 M2 M3 M4
L5 L6 L7 L8
M5 M6 M7 M8
L11 L12
M11 M12
BE
1P1
NC
INT
P3P1
INT
P2P1
INT
P1P3
INT
P1P2
V
DD(1)
70(P/V)525XBZ
BZ-144
Top View
6.42
IDT70X525XML Preliminary
Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range
3
Pin Configurations(1,2)
NOTES:
1. All VDD pins must be connected to the power supply.
2. All VSS pins must be connected to the ground supply.
3. IDT70P5258 only.
4. For Port 2 and Port 3.
Symbol Pin Name
A
0P1
- A
11P1
Ad d re s s Line s - P o rt 1 (Inp ut)
A
0P2
- A
11P2
Ad d re s s Line s - P o rt 2 (Inp ut)
A
0P3
- A
11P3
Ad d re s s Line s - P o rt 3 (Inp ut)
I/O
0P1
- I/O
15P1
D ata I/O - P or t 1
I/O
0P2
- I/O
15P2
D ata I/O - P or t 2
I/O
0P3
- I/O
15P3
D ata I/O - P or t 3
R/W
P1
Re ad / Wri te - Po rt 1 (Inp ut)
R/W
P2
Re ad / Wri te - Po rt 2 (Inp ut)
R/W
P3
Re ad / Wri te - Po rt 3 (Inp ut)
CE
P2
Chip Enab l e - Port 2 (Inp ut)
CE
P3
Chip Enab l e - Port 3 (Inp ut)
OE
P1
Outp ut E nabl e - P o rt 1 (Inp ut)
OE
P2
Outp ut E nabl e - P o rt 2 (Inp ut)
OE
P3
Outp ut E nabl e - P o rt 3 (Inp ut)
BE
0P1
B ank Enab l e 0 - P o rt 1 (Inp ut)
BE
1P1
B ank Enab l e 1 - P o rt 1 (Inp ut)
INT
P1 - P2
Interrupt
P1 - P2
- Po rt 1 (Outp ut)
INT
P1 - P3
Interrupt
P1 - P3
- Po rt 1 (Outp ut)
INT
P2 - P1
Interrupt
P2 - P1
- P o rt 2 (Output)
INT
P3 - P1
Interrupt
P3 - P1
- P o rt 3 (Output)
V
DD
P o we r (Input)
V
DDQ
Port Power Supply (Input)
(3,4)
V
SS
Gro und ( Inp ut)
5681 tbl 01
6.42
IDT70X525XML Preliminary
Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range
4
NOTES:
1. This parameter is determined by device characterization but is not production tested.
2. 3dV references the interpolated capacitance when the input and the output signals switch
from 0V to 3V or from 3V to 0V.
Capacitance(1)
(TA = +25°C, f = 1.0MHz)
lobmySretemaraPtroPsnoitidnoC
)2(
xaMtinU
C
NI
tupnI ecnaticapaC 1troPV
NI
Vd3=81Fp
3&2troPV
NI
Vd3=9Fp
C
TUO
tuptuO ecnaticapaC 1troPV
TUO
Vd3=02Fp
3&2troPV
TUO
Vd3=11Fp
30lbt1865
Maximum Operating Temperature
and Supply Voltage(1)
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
edarGerutarepmeTtneibmAeciveDV
SS
V
DD
lairtsudnIC°58+otC°04-
525P07 8525P07 V0 V8.1
+
Vm001
525V07V0V0.3
+
Vm003
40lbt1865
6.42
IDT70X525XML Preliminary
Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range
5
NOTES:
1. The supply voltage for all ports on the IDT70P525 and IDT70V525 is supplied by VDD so there are no VDDQ pins
on these devices.
2. VIL > -1.5V for pulse width less than 10ns.
3. VTERM must not exceed VDD + 10% for Port 1 or VDDQ + 10% for Port 2 and Port 3.
Recommended DC Operating Conditions
Symbol Device Port Parameter Min. Typ. Max. Unit
V
DD
70P5258
All Supp ly Vo ltage
1.7 1.8 1.9
V70P525 1.7 1.8 1.9
70V525 2.7 3 3.3
V
DDQ
70P5258 Po rt 2 & 3
I/ O Sup pl y Vo ltag e
(1)
2.733.3
V70P525 N/A
____ ____ ____
70V525 N/A
____ ____ ____
V
SS
All All Ground 0 0 0 V
V
IH
70P5258 Port 1
In p ut H igh Vol ta g e
1.2
____
V
DD
+0.2
V
Po rt 2 & 3 2
____
V
DDQ
+0.2
70P525 All 1.2
____
V
DD
+0.2
70V525 All 2
____
V
DD
+0.2
V
IL
70P5258 Port 1
In p ut L o w Vo l tage
-0.2
____
0.4
V
Po rt 2 & 3 -0. 2
____
0.6
70P525 All -0.2
____
0.4
70V525 All -0.2
____
0.6
5681 tbl 02
Absolute Maximum Ratings(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed VDD + 10% for Port 1 or VDDQ + 10% for Port 2 and Port 3 for more than
25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VDD
+ 10% (Port 1) or VDDQ + 10% (Port 2 and Port 3).
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
4. VDDQ + 0.3V for 70P5258.
lobmySgnitaRlairtsudnItinU
V
MRET
VnoegatloVylppuS
DD
DNGottcepseRhtiw 9.2+ot5.0-V
V
MRET
VnoegatloVylppuS
DDQ
DNGottcepseRhtiw 6.3+ot5.0-V
V
MRET
)2(
egatloVlanimreT DNGottcepseRhtiw Vot5.0-
DD
3.0+
)4(
V
T
SAIB
)3(
saiBrednUerutarepmeT521+ot55-
o
C
T
GTS
erutarepmeTegarotS051+ot56-
o
C
T
NJ
eutarepmeTnoitcnuJ051+
o
C
I
TUO
)525V07rof( tnerruCtuptuOCD05Am
I
TUO
525P07rof( )8525P07dna tnerruCtuptuOCD02Am
50lbt1865
6.42
IDT70X525XML Preliminary
Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range
6
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,4)
70P5258
70P525
Ind'l Only 70V525
Ind'l Only
Sym bol Parameter Test Condi tion Ver sion Typ.
(1)
Max. Typ.
(1)
Max. Unit
I
DD
Dynamic Operating Current
(Both Ports Active - CMOS
Le vel Inputs )
CE = VIL, Outp uts Op e n
f = fMAX
(2)
IND'L L 30 50 150 180 mA
ISB1 Stand by Curre nt (Bo th Ports -
CMOS Le v e l Inp uts ) CER and CEL = VIH
f = fMAX
(2)
IND'L L .004 .016 5 10 mA
ISB2 Stand by Current (One Po rt -
CMOS Le v e l Inp uts ) CE"
A
" = V
IL
and CE"
B
" = V
IH
(3)
, Active Po rt Outp uts Open
f = f
MAX
(2)
IND'L L 17 28 90 110 mA
ISB3 Ful l Stand b y Current (Bo th
Po rts - CMOS Le vel Inp uts ) Both Ports CEL and CER > V
DDQ
- 0.2V,
VIN > V
DDQ
- 0.2V or VIN < 0.2V
f = f
MAX
(2)
IND'L L 4 16 84 150 µA
ISB4 Stand by Current (One Po rt -
CMOS Le v e l Inp uts ) CE"A" < 0 . 2V and CE"B" > V
DDQ
- 0. 2V
(3)
VIN > V
DDQ
- 0.2V or VIN < 0.2V, Active Port Outputs Open
f = fMAX
(2)
IND'L L 17 28 90 110 mA
56 81 tb l 0 6
NOTES:
1. VDD = 1.8V for 70P5258 and 70P525. VDD = 3.0V for 70V525, TA = +25°C, and are not production tested. IDD DC = 15mA (typ.)
2. At f = fMAX, address and control lines are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”.
3. For the 70P5258, if Port "A" is Port 1 then Port "B" may be either Port 2 or Port 3. If Port "A" is either Port 2 or Port 3, Port "B" must be Port 1.
4. VDD = 1.8V + 100mV for 70P525 and 70P5258. VDD = 3.0V + 300mV for 70V525.
NOTE:
1. At VDD < 2.0V input leakages are undefined.
2. VDD = 1.8V + 100mV for 70P525 and 70P5258. VDD = 3.0V + 300mV for 70V525.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(2)
Symbol Device Port Parameter Test Conditions Min. Max. Unit
I
LI
70P5258 All
Inp ut Le akag e Curre nt
V
DD
= 1. 8V, V
IN
= 0V to V
DD
____
1
µA
70P525 All V
DD
= 1. 8V, V
IN
= 0V to V
DD
____
1
70V525 All V
DD
= 3. 0V, V
IN
= 0V to V
DD
____
1
I
LO
70P5258 All
Outp ut Le akag e Curre nt
CEx = BEx = V
IH
, V
OUT
= 0V to V
DD
____
1
µA
70P525 All CEx = BEx = V
IH
, V
OUT
= 0V to V
DD
____
1
70V525 All CEx = BEx = V
IH
, V
OUT
= 0V to V
DD
____
1
V
OL
70P5258 Port 1
Outp ut Low Vo ltag e
I
OL
= +0.1mA
____
0.2
V
Port 2 & 3 I
OL
= +2mA
____
0.4
70P525 All I
OL
= +0.1mA
____
0.2
70V525 All I
OL
= +2mA
____
0.4
V
OH
70P5258 Port 1
Outp ut Hig h Vo ltag e
I
OH
= -0.1mA 1.4
____
V
Port 2 & 3 I
OH
= -2mA 2.1
____
70P525 All I
OH
= -0.1mA 1.4
____
70V525 All I
OH
= -2mA 2.1
____
5681 tbl 07
6.42
IDT70X525XML Preliminary
Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range
7
AC Test Conditions
Input Pulse Leve ls
Inp ut Rise / Fal l Tim e s
Input Timing Refe re nce Le ve ls
Outp ut R efe re nce Lev e l s
Outp ut Load
GND to 3.0V/GND to 1.8V
3ns Max.
1.5V/0.9V
1.5V/0.9V
Fi g ure s 1, 2 and 3
5681 tb l 08
Timing Wavef orm of Read Cyc le No. 1, Any Port(1)
NOTE:
1. R/W = VIH and CE (or BEX) = VIL.
5681 drw 07
t
AA
t
OH
t
OH
DATA
OUT
ADDRESS
t
RC
DATA VALIDPREVIOUS DATA VALID
,
DATA
OUT
3.3V
435Ω
590Ω
30pF
5681 drw 05
Figure3. AC Output Test Load for the 70V525
(for tHZ, tLX, t WZ, tOW)
Figure 1. AC Output Test Load for the 70P525 and 70P5258
R1
R2
3
0pF
(1)
3
.
0
V
/
1
.
8
V
5681 drw 04
3.0V 1.8V
R1 1022Ω13500Ω
R2 729Ω10800Ω
5681 tb l 09
5681 drw 06
D
ATA
OUT
3.3V
435Ω
590Ω
5pF
Figure 2. AC Output Test Load for the 70V525
6.42
IDT70X525XML Preliminary
Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range
8
Timing Wa v eform of Read Cyc le No . 2, Any Port(1, 2)
NOTES:
1. R/W = VIH for Read Cycles.
2. Addresses valid prior to or coincident with CE (or BEx) transition LOW.
3. CE for Port 2 or Port 3, BEx for Port 1.
4. Timing depends on which signal is asserted last, CE (or BEx) or OE.
5. Timing depends on which signal is deasserted first, CE (or BEx) or OE.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
70X525X
Ind'l Only
Symbol Parameter Min. Max. Unit
RE AD CYCLE
t
RC
Read Cy cle Time 55 ____ ns
t
AA
Address Access Time ____ 55 ns
t
ACE
Chip Enable Access Time ____ 55 ns
t
AOE
Output Enable Access Time ____ 30 ns
t
OH
Output Ho ld fro m Ad dress Chang e 5 ____ ns
t
LZ
Output Lo w-Z Time
(1,2)
5____ ns
t
HZ
Outp ut Hig h-Z Time
(1,2)
____ 25 ns
t
PU
Chip Enab le to P ower Up Ti me
(2)
0____ ns
t
PD
Chip Dis ab le to Po we r Do wn Time
(2)
____ 55 ns
5681 tb 1 0
t
LZ
t
AOE
5681 drw 08
t
HZ
DATA
OUT
CExorBEx
(3)
t
ACE
VALID DATA
OE
CURRENT I
CC
I
SB
t
PU
50%
t
PD
50%
,
(4) (5)
6.42
IDT70X525XML Preliminary
Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range
9
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
70X525X
Ind'l Only
Symbol Parameter Min. Max. Unit
WRI TE CYCLE
t
WC
Write Cycle Time 55
____
ns
t
EW
Chip Enable to End -o f-Write 45
____
ns
t
AW
Address Valid to End-of-Write 45
____
ns
t
AS
Address Set-up Time 0
____
ns
t
WP
Write Pulse Width
(3)
40
____
ns
t
WR
Write Re covery Time 0
____
ns
t
DW
Da ta Val i d to E n d - o f-W rite 30
____
ns
t
HZ
Outp ut Hig h-Z Tim e
(1,2)
____
25 ns
t
DH
Data Ho l d Ti me 0
____
ns
t
WZ
Write Enab le to Output in High-Z
(1,2)
____
25 ns
t
OW
Ou tp u t A c ti v e from E n d -of-Wr i te
(1,2)
0
____
ns
5681 tb l 11
6.42
IDT70X525XML Preliminary
Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range
10
5681 drw 10
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
R/W
t
EW
t
DH
(6) (2) (3)
,
CE or BEx
Timing W av eform of Write Cy cle No . 1, R/W Controlled Timing(5)
Timing W aveform of Write Cyc le No. 2, CE Controlled Timing(1,5)
NOTES:
1. R/W or CE (or BEx) = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE (or BEx) = VIL and a R/W = VIL.
3. tWR is measured from the earlier of CE (or BEx) or R/W = VIH to the end of write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE (or BEx) LOW transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE (or BEx) or R/W.
7. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 3). This parameter is guaranteed but is not production tested.
CE or BEx
5681 drw 0
9
tAW tWR
tDW
DATAIN
R/W
tWP
DATAOUT
tWZ
(7)
(4) (4)
(2)
tOW
(7)
tHZ
tLZ
(7)
tHZ
(3)
tDH
(6)
tAS
ADDRESS
tWC
6.42
IDT70X525XML Preliminary
Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range
11
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70X525X
Ind'l Only
Symbol Parameter Min. Max. Unit
INTERRUPT TIMI NG
t
AS
Address Set-up Time 0
____
ns
t
WR
Write Re c o ve ry Ti me 0
____
ns
t
INS
Inte r ru p t Se t Tim e
____
45 ns
t
INR
Inte r ru p t Re se t Ti m e
____
45 ns
5681 tb l 12
Wa v eform of Interrupt Timing(1)
5681 drw 12
ADDR"A" INTERRUPT SET ADDRESS
CE"A" or BEx“A”
R/W"A"
tAS
tWC
tWR
(3) (4)
tINS
(3)
INT"B"
(2)
,
5681 drw 13
ADDR"B" INTERRUPT CLEAR ADDRESS
OE"B"
tAS
tRC
(3)
tINR
(3)
INT"B"
(2)
,
CE“B” or BEx“B”
NOTES:
1 . If Port A is Port 1, Port B may be either Port 2 or Port 3. If Port A is either Port 2 or Port 3, Port B must be Port 1.
2 . See Interrupt Truth Table II.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.42
IDT70X525XML Preliminary
Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range
12
Functional Description
The IDT70X525X provides three ports with separate control, address,
and I/O pins that permit independent access for reads or writes to the two
banks of memory. These devices have an automatic power down feature
controlled by BE0 and BE1 on Port 1 and CE on Port 2 and Port 3. The
CE (or BEX) controls on-chip power down circuitry that permits the
respective port to go into standby mode when not selected (CE or BEX =
VIH). When Port 1 is enabled, it has access to the full memory. When Port
2 is active it has access to Bank 1 of the memory. When Port 3 is active it
has access to Bank 2 of the memory. See Truth Table I for a description
of the Read/Write operation.
T ruth T able I – R ead/Write Contro l
NOTE:
1. Both BE0, and BE1 cannot be active (BEx = VIL) simultaneously.
2. Memory Bank 0 for Port 2. Memory Bank 1 for Port 3.
BE
0
BE
1
R/WCE OE D
0-
D
15
Function
PORT 1
HHXXXZPort Deselected
LHLXXDATA
IN
Da ta on po r t writte n i n to M em o r y B a nk 0
LHHXLDATA
OUT
Data i n Mem o ry Ba nk 0 outp ut o n po rt
HLLXXDATA
IN
Da ta on po r t writte n i n to M em o r y B a nk 1
HLHXLDATA
OUT
Data i n Mem o ry Ba nk 1 outp ut o n po rt
XXXX HZOutputs Disabled
L LXXXXNot Allowed
PORT 2
or
PORT 3
X X X H X Z Port Deselected
XXLLXDATA
IN
Da ta on po r t writte n i n to M em o r y B a nk
(2)
XXHLLDATA
OUT
Data in Me mory Bank
(2)
output on port
XXXX HZOutputs Disabled
HHXHXZ
BE
0
= BE
1
= CE
P
3
= V
IH
, Sleep mode
5681 tbl 13
6.42
IDT70X525XML Preliminary
Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range
13
Port 1 Port 2 or 3
Function
R/WBE
0
BE
1
OE A
11
- A
0
INT
P
1
-
P
2
INT
P
1
-
P
3
R/WCE OEA
11
- A
0
INT
P
x
-
P
1
L L H X FFF X X X X X X L Set P2 INT Flag
XXXXX X X X L LFFF HReset P2 INT Flag
L H L X FFF X X X X X X L Set P3 INT Flag
XXXXX X X X L LFFF HReset P3 INT Flag
XXXXX L X LLXFFE X Se t P1 INT
P1-P2
Flag
(1)
X LHLFFEH X XXXX X Reset P1 INT
P1-P2
Flag
XXXXX X L LLXFFE X Se t P1 INT
P1-P3
Flag
(2)
XHL LFFEX H XXXX X Reset P1 INT
P1-P3
Flag
5681 tbl 14
T ruth Table II - Interrupt Flag
NOTE:
1 . Port 2 sets the INTP1 - P2 flag on Port 1 so all signals refer to Port 2.
2 . Port 3 sets the INTP1 - P3 flag on Port 1 so all signals refer to Port 3.
Interrupts
If the user chooses the interrupt function, a memory location (mailbox
or message center) is assigned to each port. Interrupt P1 - P2 of Port 1
(INTP1 - P2) is asserted when Port 2 writes to memory location FFE(HEX),
where a write is defined as CE = R/W = VIL per Truth Table II. Port 1 clears
the interrupt by accessing address location FFE when BE0 = VIL, R/W is
a "don't care". Interrupt P1 - P3 of Port 1 (INTP1 - P3) is asserted when Port
3 writes to memory location FFE (HEX), where a write is defined as CE=
R/W = VIL. Port 1 clears the interrupt by accessing address location FFE
when BE1 = VIL, R/W is a "don't care". Port 2's interrupt flag (INTP2 - P1)
is asserted when Port 1 writes to memory location FFF (HEX), where a
write is defined as BE0 = R/W = VIL. Port 2 clears the interrupt by accessing
address location FFF when CE = VIL, R/W is a "don't care". Likewise, Port
3's interrupt flag (INTP3 - P1) is asserted when Port 1 writes to memory
location FFF (HEX), where a write is defined as BE1= R/W = VIL. Port 3
clears the interrupt by accessing address location FFF when CE= VIL, R/
W is a "don't care".
6.42
IDT70X525XML Preliminary
Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range
14
Ordering Information
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
BZ 144-Ball Ball Grid Array (BZ144-1)
Speed in nanoseconds
Low Power
128K (8K x 16) TriPort RAM
Industrial Only
55
XXXX
Device
Type
5681 drw 14
L
70P5258
70P525
70V525
A
Industrial (-40°Cto+85°C)
I
G
(1)
Green
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
10/14/03: Initial datasheet
03/23/04: Page 7 Corrected tOH spec min to 5ns in AC Electrical CharacteristicsTable 10
5/26/05: Page 1 Added green availability to features
Page 13 Added green indicator to ordering information
Page 1 & 13 Replaced old logo ® with new TM logo
05/08/06: Page 5 Updated VTERM in Absolute Maximum Ratings table and added footnote 3 & 4
07/25/08: Page 6 Corrected a typo in the DC Chars table
01/19/09: Page 14 Removed "IDT" from orderable part number
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
NOTE:
1. Green parts available. For specific speeds, packages and powers contact your sales office.
