ACT-F128K32 High Speed 4 Megabit FLASH Multichip Module CIRCUIT TECHNOLOGY www.aeroflex.com Features 4 Low Power 128K x 8 FLASH Die in One MCM MIL-PRF-38534 Compliant MCMs Available Industry Standard Pinouts Packaging - Hermetic Ceramic Package Organized as 128K x 32 User Configurable to 256K x 16 or 512K x 8 Upgradable to 512K x 32 in same Package Style Access Times of 60, 70, 90, 120 and 150ns +5V Programing, 5V 10% Supply 100,000 Erase/Program Cycles Typical, 0C to +70C Low Standby Current TTL Compatible Inputs and CMOS Outputs Embedded Erase and Program Algorithms Page Program Operation and Internal Program Control Time Commercial, Industrial and Military Temperature Ranges 68 Lead, .88" x .88" x .160" Single-Cavity Small Outline gull wing, Aeroflex code# "F5" (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint) 66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder, Aeroflex code# "P3" 66 Pin, 1.08" x 1.08" x .185" PGA Type, With Shoulder, Aeroflex code# "P7" Sector Architecture (Each Die) 8 Equal size sectors of 64K bytes each Any Combination of Sectors can be erased with one command sequence Supports Full Chip Erase DESC SMD# 5962-94716 Released (P3,P7,F5) Block Diagram - PGA Type Package (P3,P7) & CQFP (F5) WE 1 CE1 WE 2 CE2 WE 3 CE3 WE4 CE4 OE A0-A 16 128Kx8 128Kx8 128Kx8 128Kx8 8 8 8 8 I/O0-7 I/O8-15 I/O 16-23 I/O24-31 Pin Description I/O0-31 Data I/O A0-16 Address Inputs WE 1-4 Write Enables CE1-4 Chip Enables OE Output Enable VCC Power Supply GND Ground NC Not Connected General Description The ACT-F128K32 is a high speed, 4 megabit CMOS flash multichip module (MCM) designed for full temperature range military, space, or high reliability applications. The MCM can be organized as a 128K x 32 bits, 256K x 16 bits or 512K x 8 bits device and is input TTL and output CMOS compatible. The command register is written by bringing WE to a logic low level (VIL), while CE is low and OE is at logic high level (VIH). Reading is accomplished by chip Enable (CE) and Output Enable (OE) being logically active, see Figure 9. Access time grades of 60ns, 70ns, 90ns, 120ns and 150ns maximum are standard. The ACT-F128K32 is packaged in a hermetically eroflex Circuit Technology - Advanced Multichip Modules (c) SCD1667 REV C 10/28/02 General Description, Cont'd, sealed co-fired ceramic 66 pin, 1.08" sq PGA or a 68 lead, .88" sq Ceramic Gull Wing CQFP package for operation over the temperature range of -55C to +125C and military environment. Each flash memory die is organized as 128KX8 bits and is designed to be programmed in-system with the standard system 5.0V Vcc supply. A 12.0V VPP is not required for write or erase operations. The MCM can also be reprogrammed with standard EPROM programmers (with the proper socket). The standard ACT-F128K32 offers access times between 60ns and 150ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the device has separate chip enable (CE) and write enable (WE). The ACT-F128K32 is command set compatible with JEDEC standard 1 Mbit EEPROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0V Flash or EPROM devices. The ACT-F128K32 is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.3 Aeroflex Circuit Technology second. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array, (if it is not already programmed before) executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. Each die in the module or any individual sector of the die is typically erased and verified in 1.3 seconds (if already completely preprogrammed). Each die also features a sector erase architecture. The sector mode allows for 16K byte blocks of memory to be erased and reprogrammed without affecting other blocks. The ACT-F128K32 is erased when shipped from the factory. The device features single 5.0V power supply operation for both read and write functions. lnternally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of D7 or by the Toggle Bit feature on D6. Once the end of a program or erase cycle has been completed,-+ the device internally resets to the read mode. All bits of each die, or all bits within a sector of a die, are erased via Fowler-Nordhiem tunneling. Bytes are programmed one byte at a time by hot electron injection. DESC Standard Military Drawing (SMD) numbers are released. 2 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 A Absolute Maximum Ratings Parameter Symbol Range Units Case Operating Temperature TC -55 to +125 C Storage Temperature Range TSTG -65 to +150 C Supply Voltage Range VCC -2.0 to +7.0 V Signal Voltage Range (Any Pin Except A9) Note 1 VG -2.0 to +7.0 V Maximum Lead Temperature (10 seconds) 300 C Data Retention 10 Years 100,000 Minimum Endurance (Write/Erase cycles) -2.0 to +14.0 VID A9 Voltage for sector protect, Note 2 V Note 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -2.0v for periods of up to 20ns. Maximum DC voltage on input and I/O pins is VCC + 0.5V. During voltage transitions, inputs and I/O pins may overshoot to VCC + 2.0V for periods up to 20 ns. Note 2. Minimum DC input voltage on A9 is -0.5V. During voltage transitions, A9 may undershoot VSS to -2.0V for periods of up to 20ns. Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns. Normal Operating Conditions Symbol VCC VIH Parameter Minimum Maximum Units Power Supply Voltage +4.5 +5.5 V Input High Voltage +2.0 VCC + 0.5 V VIL Input Low Voltage -0.5 +0.8 V TC Operating Temperature (Military) -55 +125 C VID A9 Voltage for sector protect 11.5 12.5 V A Capacitance (V IN= 0V, f = 1MHz, TC = 25C) Symbol Maximum Units 50 pF 50 pF CQFP(F5) Package 20 pF PGA(P3,P7) Package 20 pF CCE Chip Enable Capacitance 20 pF CI/O I/O0 - I/O31 Capacitance 20 pF CAD Parameter A0 - A16 Capacitance COE OE Capacitance CWE Write Enable Capacitance Parameters Guaranteed but not tested DC Characteristics - CMOS Compatible (Vcc = 5.0V, Vss = 0V, TC = -55C to +125C, unless otherwise indicated) Parameter Input Leakage Current Output Leakage Current Sym Speeds 60, 70, 90, 120 & 150ns Conditions ILI Minimum VCC = 5.5V, ViN = GND to VCC ILOX32 VCC = 5.5V, ViN = GND to VCC Maximum Units 10 A 10 A Active Operating Supply Current for Read (1) ICC1 CE = VIL, OE = VIH, f = 5MHz 140 mA Active Operating Supply Current for Program or Erase(2) ICC2 CE = VIL, OE = VIH 200 mA Standby Supply Current ICC3 VCC = 5.5V, CE = VIH, f = 5MHz 6.5 mA Static Supply Current (4) ICC4 VCC = 5.5V, CE = VIH 0.6 mA Output Low Voltage VOL IOL = +8.0 mA, VCC = 4.5V Output High Voltage VOH1 IOH = -2.5 mA, VCC = 4.5V 0.85 x VCC Output High Voltage (4) VOH2 IOH = -100 A, VCC = 4.5V VCC - 0.4 V Low Power Supply Lock-Out Voltage (4) VLKO 3.2 V 0.45 V V Note 1. The Icc current listed includes both the DC operating current and the frequency dependent component (At 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at V IN. Note 2. Icc active while Embedded Algorithm (Program or Erase) is in progress. Note 3. DC Test conditions: VIL = 0.3V, VIH = VCC - 0.3V, unless otherwise indicated Note 4. Parameter Guaranteed but not tested. Aeroflex Circuit Technology 3 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 Characteristics - Read Only Operations (Vcc = 5.0V, Vss = 0V, TC = -55C to +125C) Symbol Parameter -60 JEDEC Stand'd -70 -90 Min Max Min Max Min Max 60 70 90 -120 -150 Min Max Min Max Read Cycle Time tAVAV tRC Address Access Time tAVQV tACC 60 70 90 120 120 150 150 Units ns ns Chip Enable Access Time tELQV tCE 60 70 90 120 150 ns Output Enable to Output Valid tGLQV tOE 30 35 40 50 55 ns Chip Enable to Output High Z (1) tEHQZ tDF 20 20 25 30 35 ns Output Enable High to Output High Z (1) tGHQZ tDF 20 20 25 30 35 ns Output Hold from Address, CE or OE Change, whichever is first tAXQX tOH 0 0 0 0 0 ns Note 1. Guaranteed by design, but not tested AC Characteristics - Write/Erase/Program Operations, WE Controlled (Vcc = 5.0V, Vss = 0V, Tc = -55C to +125C) Symbol Parameter -60 -70 -90 JEDEC Stand'd Min Max Min Max Min Max -120 -150 Min Max Min Max Units Write Cycle Time tAVAC tWC 60 70 90 120 150 ns Chip Enable Setup Time tELWL tCE 0 0 0 0 0 ns Write Enable Pulse Width tWLWH tWP 30 35 45 50 50 ns Address Setup Time tAVWL tAS 0 0 0 0 0 ns Data Setup Time tDVWH tDS 30 30 45 50 50 ns Data Hold Time tWHDX tDH 0 0 0 0 0 ns Address Hold Time tWLAX tAH 45 45 45 50 50 ns Chip Enable Hold Time (1) tWHEH tCH 0 0 0 0 0 ns Write Enable Pulse Width High tWHWL tWPH 20 20 20 20 Duration of Byte Programming Operation tWHWH1 14 TYP 14 TYP 14 TYP 14 20 TYP 14 ns TYP s Sector Erase Time tWHWH2 60 60 60 60 60 Sec Chip Erase Time tWHWH3 120 120 120 120 120 Sec tGHWL 0 0 0 0 0 s tVCE 50 50 50 50 50 s Output Enable Setup Time (1) tOES 0 0 0 0 0 ns Output Enable Hold Time (1) tOEH 10 10 10 10 10 ns Read Recovery Time before Write (1) Vcc Setup Time (1) 12.5 Chip Programming Time 12.5 12.5 12.5 12.5 Sec Note 1. Guaranteed by design, but not tested AC Characteristics - Write/Erase/Program Operations, CE Controlled (Vcc = 5.0V, Vss = 0V, TC = -55C to +125C) Parameter Symbol -60 -70 -90 JEDEC Stand'd Min Max Min Max Min Max -120 -150 Min Max Min Max Units Write Cycle Time tAVAC tWC 60 70 90 120 150 ns Write Enable Setup Time tWLEL tWS 0 0 0 0 0 ns Chip Enable Pulse Width tELEH tCP 35 35 45 50 55 ns ns Address Setup Time tAVEL tAS 0 0 0 0 0 Data Setup Time tDVEH tDS 30 30 45 50 55 ns Data Hold Time tEHDX tDH 0 0 0 0 0 ns Address Hold Time tELAX tAH 45 45 45 50 55 ns ns Write Enable Hold Time (1) tEHWH tWH 0 0 0 0 0 Write Select Pulse Width High tEHEL tCPH 20 20 20 20 20 Duration of Byte Programming tWHWH1 Sector Erase Time tWHWH2 Chip Erase Time tWHWH3 Read Recovery Time (1) tGHEL 14 TYP 14 TYP 14 TYP 60 120 0 60 120 0 12.5 Chip Programming Time 60 TYP 120 0 12.5 14 60 120 0 12.5 14 ns TYP s 60 Sec 120 Sec 12.5 Sec 0 12.5 ns Note 1. Guaranteed by design, but not tested Aeroflex Circuit Technology 4 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 A current consumed is typically less than 400 A; and a TTL standby mode (CE is held VIH) is approximately 1 mA. In the standby mode the outputs are in a high impedance state, independent of the OE input. If the device is deselected during erasure or programming, the device will draw active current until the operation is completed. Device Operation The ACT-F128K32 MCM is composed of four, one megabit flash EEPROMs. The following description is for the individual flash EEPROM device, is applicable to each of the four memory chips inside the MCM. Chip 1 is distinguished by CE1 and I/O1-7, Chip 2 by CE2 and I/08-15, Chip 3 by CE3 and I/016-23, and Chip 4 by CE4 and I/024-31. Programming of the ACT-F128K32 is accomplished by executing the program command sequence. The program algorithm, which is an internal algorithm, automatically times the program pulse widths and verifies proper cell status. Sectors can be programed and verified in less than 0.3 second. Erase is accomplished by executing the erase command sequence. The erase algorithm, which is internal, automatically preprograms the array if it is not already programed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell status. The entire memory is typically erased and verified in 3 seconds (if pre-programmed). The sector mode allows for 16K byte blocks of memory to be erased and reprogrammed without affecting other blocks. WRITE Device erasure and programming are accomplished via the command register. The contents of the register serve as input to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy an addressable memory location. The register is a latch used to store the command, along with address and data information needed to execute the command. The command register is written by bringing WE to a logic low level (VIL), while CE is low and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later. Data is latched on the rising edge of the WE or CE whichever occurs first. Standard microprocessor write timings are used. Refer to AC Program Characteristics and Waveforms, Figures 3, 8 and 13. Bus Operation READ Command Definitions The ACT-F128K32 has two control functions, both of which must be logically active, to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output-Enable (OE) is the output control and should be used to gate data to the output pins of the chip selected. Figure 7 illustrates AC read timing waveforms. Device operations are selected by writing specific address and data sequences into the command register. Table 3 defines these register command sequences. READ/RESET COMMAND The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard Microprocessor read cycles will retrieve array data. This OUTPUT DISABLE With Output-Enable at a logic high level (VIH), output from the device is disabled. Output pins are placed in a high impedance state. STANDBY MODE The ACT-F128K32 has two standby modes, a CMOS standby mode (CE input held at Vcc + 0.5V), where the Table 2 - Sector Addresses Table Table 1 - Bus Operations Operation CE OE WE A0 A1 A9 I/O A14 Address Range READ L L H A0 A1 A9 DOUT SA0 0 0 0 00000h - 03FFFh STANDBY H X X X HIGH Z SA1 0 0 1 04000h - 07FFFh HIGH Z SA2 0 1 0 08000h - 0BFFFh SA3 0 1 1 0C000h - 0FFFFh SA4 1 0 0 10000h - 13FFFh SA5 1 0 1 14000h - 17FFFh SA6 1 1 0 18000h - 1BFFFh SA7 1 1 1 1C000h - 1FFFFh X OUTPUT DISABLE L H H X WRITE L H L A0 A1 A9 ENABLE SECTOR PROTECT VERIFY SECTOR PROTECT Aeroflex Circuit Technology L L VID L L H X L X X X H X VID VID A16 A15 DIN X Code 5 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 A Table 3 -- Commands Definitions Command Sequence Read/Reset Bus Write Cycle First Bus Write Second Bus Write Third Bus Write Cycle Cycle Cycle Fourth Bus Read/Write Cycle Req'd Addr Data Addr Data Addr Data Addr Data 4 5555H AAH 2AAAH 55H 5555H F0H RA RD Fifth Bus Write Sixth Bus Write Cycle Cycle Addr Data Addr Data Byte Program 6 5555H AAH 2AAAH 55H 5555H A0H PA PD Chip Erase 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Sector Erase 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H NOTES: 1. Address bit A15 = X = Don't Care. Write Sequences may be initiated with A15 in either state. 2. Address bit A16 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA). 3. RA = Address of the memory location to be read PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A16, A15, A14 will uniquely select any sector. 4. RD = Data read from location RA during read Operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. CHIP ERASE default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Figure 7 for the specific timing parameters. Chip erase is a six bus cycle operation. There are two 'unlock' write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence (Figure 4) the device will automatically program and verify the entire memory for an all zero data pattem prior to electrical erase. The erase is performed concurrently on all sectors at the same time . The system is not required to provide any controls or timings during these operations. Note: Post Erase data state is all "1"s. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on D7 is "1" (see Write Operation Status section - Table 3) at which time the device retums to read mode. See Figures 4 and 9. BYTE PROGRAMING The device is programmed on a byte-byte basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever occurs later, while the data is latched on the rising edge of CE or WE whichever occurs first. The rising edge of CE or WE (whichever happens first) begins programming using the Embedded Program Algorithm. Upon executing the program algorithm command sequence the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell. The automatic programming operation is completed when the data on D 7 (also used as Data Polling) is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched. Therefore, the device requires that a valid address be supplied by the system at this particular instance of time for Data Polling operations. Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during the Embedded Program Algorithm will be ignored. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may cause the device to exceed programming time limits (D5 = 1) or result in an apparent success, according to the data polling algorithm, but a read from reset/read mode will show that the data is still "0". Only erase operations can convert "0"s to "1"s. Figure 3 illustrates the programming algorithm using typical command strings and bus operations. Aeroflex Circuit Technology SECTOR ERASE Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "setup" command. Two more "unlock" write cycles are then followed by the sector erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (30H) is latched on the rising edge of WE. After a time-out of 80s from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. This sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than 80s otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 80s from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs 6 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 A LOGICAL INHIBIT within the 80s time-out window the timer is reset. (Monitor D3 to determine if the sector erase timer window is still open, see section D3, Sector Erase Timer.) Any commarid other than Sector Erase during this period will reset the device to read mode, ignoring the previous command string. In that case, restart the erase on those sectors and allow them to complete. Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 7). Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. Post Erase data state is all "1"s. The automatic sector erase begins after the 80s time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on D7, Data Polling, is "1" (see Write Operatlon Status secton) at which time the device returns to read mode. Data Polling must be performed at an address within any of the sectors being erased. Figure 4 illustrates the Embedded Erase Algorithm. Writing is inhibited by holding anyone of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be logical zero while OE is a logical one. POWER-UP WRITE INHIBIT Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. Write Operation Status D7 DATA POLLING The ACT-F128K32 features Data Polling as a method to indicate to the host that the internal algorithms are in progress or completed. During the program algorithm, an attempt to read the device will produce compliment data of the data last written to D 7. Upon completion of the programming algorithm an attempt to read the device will produce the true data last written to D7. Data Polling is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. During the erase algorithm, D7 will be "0" until the erase operation is completed. Upon completion data at D7 is "1". For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Data Polling is Valid after the last rising edge of the sector erase WE pulse. The Data Polling feature is only active during the programming algorithm, erase algorithm, or sector erase time-out. See Figures 6 and 10 for the Data Polling specifications. Data Protection The ACT-F128K32 is designed to offer protection against accidental erasure or programming caused by spurious system level singles that may exist during power transitions. During power up the device automatically resets the internal state machine in the read mode. Also, with its control register architecture, alteration of the memory content only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power-up and power-down transitions or system noise. LOW Vcc WRITE INHIBIT D6 TOGGLE BIT To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for VCC less than 3.2V (typically 3.7V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to read mode. Subsequent writes will be ignored until the It is the users Vcc level is greater than VLKO. responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 3.2V. The ACT-F128K32 also features the "Toggle Bit" as a method to indicate to the host system that algorithms are in progress or completed. During a program or erase algorithm cycle, successive attempts to read data from the device will result in D 6 toggling between one and zero. Once the program or erase algorithm cycle is completed, D 6 Will stop toggling and valid data will be read on successive attempts. During programming the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase the Toggle Bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is active during the sector time out. See Figure 1 and 5. WRITE PULSE GLITCH PROTECTION Noise pulses of less than 5ns (typical) on OE, CE or WE will not initiate a write cycle. Aeroflex Circuit Technology 7 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 A Table 4 -- Hardware Sequence Flags In Progress Exceeding Time Limits Status D7 D6 Auto-Programming D7 Toggle 0 0 0 Programming in Auto Erase 0 Toggle 0 0 1 Erase in Auto Erase 0 Toggle 0 1 1 Auto-Programming D7 Toggle 1 0 0 Programming in Auto Erase T0 Toggle 1 0 1 0 Toggle 1 1 1 Erase in Auto Erase D 2 - D0 Reserved for future use Reserved for future use Sector Protection Algorithims D5 EXCEEDED TIMING LIMITS D5 will indicate if the program or erase time has exceeded the specified limits. Under these conditions D5 will produce a "1". The Program or erase cycle was not successfully completed. Data Polling is the only operation function of the device under this condition. The CE circuit will partially power down the device under these conditions by approximately 8 mA per chip. The OE and WE pins will control the output disable functions as shown in Table 1. To reset the device, write the reset command sequence to the device. This allows the system to continue to use the other active sectors in the device. SECTOR PROTECTION The ACT-F128K32 features hardware sector protection which will disable both program and erase operations to an individual sector or any group of sectors. To activate this mode, the programming equipment must force VID on control pin OE and address pin A9. The sector addresses should be set using higher address lines A16, A15, and A14. The protection mechanism begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. It is also possible to verify if a sector is protected during the sector protection operation. This is done by setting CE = OE = VIL and WE = VIH (A9 remains high at VID). Reading the device at address location XXX2H, where the higher order addresses (A16, A15 and A14) define a particular sector, will produce 01H at data outputs D0 D7, for a protected sector. D4 - HARDWARE SEQUENCE FLAG If the device has exceeded the specified erase or program time and D5 is "1", then D4 Will indicate which step in the algorithm the device exceeded the limits. A "0" in D4 indicates in programming, a "1" indicates an erase. (See Table 4) SECTOR UNPROTECT D3 SECTOR ERASE TIMER The ACT-F128K32 also features a sector unprotect mode, so that a protected sector may be unprotected to incorporate any changes in the code. All sectors should be protected prior to unprotecting any sector. To activate this mode, the programming equipment must force VID on control pins OE, CE, and address pin A9. The address pins A6, A7, and A12 should be set to VIH, and A6 = VIL. The unprotection mechanism begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. It is also possible to determine if a sector is unprotected in the system by writing the autoselect command. Performing a read operation at address location XXX2H, where the higher order addresses (A16, A15, and A14) define a particular sector address, will produce 00H at data outputs (D0-D7) for an unprotected sector. After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, D3 may be used to determine if the sector erase timer window is still open. If D3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If D3 is low ("0"), the device will accept additional sector erase commands. To ensure the command has been accepted, the software should check the status of D3 prior to and following each subsequent sector erase command. If D3 were high on the second status check, the command may not have been accepted. Aeroflex Circuit Technology D5 D4 D3 8 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 A Figure 1 AC Waveforms for Toggle Bit During Embedded Algorithm Operations CE tOEH WE tOES OE Data D0-D7 D6=Toggle D6=Toggle D6 Stop Toggle D0-D7 Valid tOE A Figure 2 AC Test Circuit Current Source IOL To Device Under Test CL = 50 pF Parameter Input Pulse Level Input Rise and Fall VZ ~ 1.5 V (Bipolar Supply) Input and Output Timing Reference Output Lead Capacitance Typical 0 - 3.0 5 1.5 50 Units V ns V pF IOH Current Source Notes: 1) V Z is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance ZO = 75. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance. Aeroflex Circuit Technology 9 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 Figure 3 Programming Algorithm Bus Operations Command Sequence Comments Program Valid Address/Data Sequence Standby Write Read Data Polling to Verify Programming Standby Compare Data Output to Data Expected Start Write Program Command Sequence (See Below) A Data Poll Device Increment Address No Last Address ? Yes Programming Complete Program Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/A0H Programming Address/Program Data Aeroflex Circuit Technology 10 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 Figure 4 Erase Algorithm Bus Operations Command Sequence Comments Standby Write Erase Read Data Polling to Verify Erasure Standby Compare Output to FFH Start Write Erase Command Sequence (See Below) A Data Poll or Toggle Bit Successfully Completed Erasure Completed Chip Erase Command Sequence (Address/Command) Individual Sector/Multiple Sector Erase Command Sequence (Address/Command) 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/80H 5555H/80H 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/10H Sector Address/30H Sector Address/30H Additional Sector Erase Commands are Optional Sector Address/30H Note 1. To Ensure the command has been accepted, the system software should check the status of D3 prior to and following each subsequent sector erase command. If D3 were high on the second status check, the command may not have been accepted. Aeroflex Circuit Technology 11 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 Figure 5 Toggle Bit Algorithm Figure 6 Data Polling Algorithm Start Read Byte D0-D7 Address = VA D6 = Toggle ? Start VA = Byte Address for Programming = Any of the Sector Addresses within the sector being erased during sector erase operation = XXXXH during Chip Erase Read Byte D0-D7 Address = VA No D7 = Data ? No D5 = 1 ? D5 = 1 ? Yes Yes Read Byte D0-D7 Address = VA D7 = Toggle? (Note 1) No Pass No Fail Yes Pass Fail Note 1. D6 is rechecked even if D5 = "1" because D6 may stop toggling at the same time as D5 changes to "1". Aeroflex Circuit Technology A Yes Read Byte D0-D7 Address = VA D6 = Toggle? (Note 1) Yes No Yes No VA = Byte Address for Programming = Any of the Sector Addresses within the sector being erased during sector erase operation = XXXXH during Chip Erase Note 1. D7 is rechecked even if D 5 = "1" because D7 may change simultaneously with D5. 12 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 Figure 7 AC Waveforms for Read Operations tRC Addresses Addresses Stable tACC CE tDF OE tOE WE tCE tOH High Z Outputs Output Valid A High Z Figure 8 Write/Erase/Program Operation, WE Controlled Data Polling Addresses 5555H PA tWC tAS PA tRC tAH CE tGHWL OE tWP tWHWH1 tWPH WE tCE tDF tOE tDH AOH Data PD D7 DOUT tDS tOH 5.0V tCE Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the 0utput of the complement of the data written to the deviced. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Aeroflex Circuit Technology 13 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 Figure 9 AC Waveforms Chip/Sector Erase Operations Data Polling tAH 5555H Addresses 2AAAH 5555H 5555H 2AAAH SA tAS CE tGHWL OE tWP WE tCE tWPH tDH A AAH Data 55H 80H AAH 55H 10H/30H tDS VCC tVCE Notes: 1. SA is the sector address for sector erase. Figure 10 AC Waveforms for Data Polling During Embedded Algorithm Operations tCH CE tDF t OE OE tOEH WE tCE tOH * D7 D7 D7= Valid Data High Z tWHWH1 or 2 D0-D6 D0-D6 Valid Data D0-D6=Invalid tOE * D7=Valid Data (The device has completed the Embedded operation). Aeroflex Circuit Technology 14 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 Figure 11 Sector Protection Algorithm Start Set Up Sector Address (A16 , A15, A14) PLSCNT = 1 OE = VID A9 = V ID, CE = VIL A Activate WE Pulse Time Out 100s Increment PLSCNT Power Down OE WE = V IH CE = OE = V IH A9 Should Remain VID Read From Sector Address = SA, A0 = 0, A1 = 1, A6 = 0 No No Data = 01H ? PLSCNT = 25 ? Yes Yes Device Failure Protect Another Sector? Yes No Remove VID from A9 Write Reset Command Sector Protection Complete Aeroflex Circuit Technology 15 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 Figure 12 Sector Unprotect Algorithm Start Set VCC = 5.0 V Protect All Sectors PLSCNT = 1 Set Up Sector Address Unprotected Mode (A12 = A7 = VIH, A6 = VIL) Set VCC = 5.0 V A Set OE = CE = A9 = VID Activate WE Pulse Increment PLSCNT Time Out 10ms Set OE = CE = V IL Remove VID from A9 Set VCC = 4.25 V Write Autoselect Command Sequence Setup Sector Address SA0 Set A1 = 1, A0 = 0 Read Data From Device No Increment Sector Address No Data = 00H ? Yes Write Reset Command PLSCNT = 1000 ? Yes Device Failure No Sector Address = SA7 ? Yes Set VCC = 5.0 V Notes: SA0 = Sector Address for initial sector SA7 = Sector Address for last sector Please refer to Table 2 Write Reset Command Sector Unprotect Completed Aeroflex Circuit Technology 16 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 Figure 13 Write/Erase/Program Operation, CE Controlled Data Polling Addresses 5555H PA t WC tAS PA tAH WE t GHEL OE tCP CE tWHWH1 t CPH tWS tDH AOH Data A PD D7 DOUT tDS 5.0V Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the 0utput of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Aeroflex Circuit Technology 17 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 Pin Numbers & Functions 66 Pins -- PGA Pin# Function Pin# Function Pin# Function Pin# Function 1 I/O8 18 A15 35 I/O25 52 WE3 2 I/O9 19 Vcc 36 I/O26 53 CE3 3 I/O10 20 CE1 37 A7 54 GND 4 A14 21 NC 38 A12 55 I/O19 5 A16 22 I/O3 39 NC 56 I/O31 6 A11 23 I/O15 40 A13 57 I/O30 7 A0 24 I/O14 41 A8 58 I/O29 8 NC 25 I/O13 42 I/O16 59 I/O28 9 I/O0 26 I/O12 43 I/O17 60 A1 10 I/O1 27 OE 44 I/O18 61 A2 11 I/O2 28 NC 45 VCC 62 A3 12 WE2 29 WE1 46 CE4 63 I/O23 13 CE2 30 I/O7 47 WE4 64 I/O22 A 14 GND 31 I/O6 48 I/O27 65 I/O21 15 I/O11 32 I/O5 49 A4 66 I/O20 16 A10 33 I/O4 50 A5 17 A9 34 I/O24 51 A6 "P3" -- 1.08" SQ PGA Type (without shoulder) Package "P7" -- 1.08" SQ PGA Type (with shoulder) Package Bottom View (P7 & P3) Side View (P7) Side View (P3) 1.085 SQ MAX 1.000 .185 MAX .600 .025 .035 Pin 56 .050 1.030 1.040 .100 Pin 1 1.030 1.040 .100 .020 .016 1.000 .020 .016 Pin 66 .180 TYP Pin 11 .180 TYP .100 .160 MAX All dimensions in inches Aeroflex Circuit Technology 18 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 Pin Numbers & Functions 68 Pins -- CQFP Package Pin# Function Pin# Function Pin# Function Pin# Function 1 GND 18 GND 35 OE 52 GND 2 CE3 19 I/O8 36 CE2 53 I/O23 3 A5 20 I/O9 37 NC 54 I/O22 4 A4 21 I/O10 38 WE2 55 I/O21 5 A3 22 I/O11 39 WE3 56 I/O20 6 A2 23 I/O12 40 WE4 57 I/O19 7 A1 24 I/O13 41 NC 58 I/O18 8 A0 25 I/O14 42 NC 59 I/O17 9 NC 26 I/O15 43 NC 60 I/O16 10 I/O0 27 VCC 44 I/O31 61 VCC 11 I/O1 28 A11 45 I/O30 62 A10 12 I/O2 29 A12 46 I/O29 63 A9 13 I/O3 30 A13 47 I/O28 64 A8 14 I/O4 31 A14 48 I/O27 65 A7 15 I/O5 32 A15 49 I/O26 66 A6 16 I/O6 33 A16 50 I/O25 67 WE1 17 I/O7 34 CE1 51 I/O24 68 CE4 "F5" -- Single-Cavity CQFP Top View Pin 9 .990 SQ .010 .880 SQ .010 Pin 10 Side View .160 MAX Pin 61 Pin 60 .010 REF .015 .010 .946 .010 .010 R 1- 7 .040 Detail "A" .050 TYP Pin 26 Pin 27 .010 .005 Pin 44 .800 REF Pin 43 See Detail "A" All dimensions in inches Aeroflex Circuit Technology 19 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 A CIRCUIT TECHNOLOGY Ordering Information Model Number DESC Drawing Number Speed Package ACT-F128K32N-060P3Q 5962-9471605HZX 60 ns PGA ACT-F128K32N-070P3Q 5962-9471604HZC 70 ns PGA ACT-F128K32N-090P3Q 5962-9471603HZC 90 ns PGA ACT-F128K32N-120P3Q 5962-9471602HZC 120 ns PGA ACT-F128K32N-150P3Q 5962-9471601HZC 150 ns PGA ACT-F128K32N-060P7Q 5962-9471605H8X 60 ns PGA ACT-F128K32N-070P7Q 5962-9471604H8C 70 ns PGA ACT-F128K32N-090P7Q 5962-9471603H8C 90 ns PGA ACT-F128K32N-120P7Q 5962-9471602H8C 120 ns PGA ACT-F128K32N-150P7Q 5962-9471601H8C 150 ns PGA ACT-F128K32N-060F5Q 5962-9471605HNX 60 ns CQFP ACT-F128K32N-070F5Q 5962-9471604HNC 70 ns CQFP ACT-F128K32N-090F5Q 5962-9471603HNC 90 ns CQFP ACT-F128K32N-120F5Q 5962-9471602HNC 120 ns CQFP ACT-F128K32N-150F5Q 5962-9471601HNC 150 ns CQFP Part Number Breakdown ACT- F 128K 32 N- 060 F5 Q Aeroflex Circuit Technology Screening C = Commercial Temp, 0C to +70C I = Industrial Temp, -40C to +85C T = Military Temp, -55C to +125C M = Military Temp, -55C to +125C, Screened * Q = MIL-PRF-38534 Compliant / SMD if applicable Memory Type F = FLASH EEPROM Memory Depth Memory Width, Bits Package Type & Size Surface Mount Packages Thru-Hole Packages F5 = .88"SQ 68 Lead P3 = 1.075"SQ PGA 66 Pins W/O Shoulder Single-Cavity CQFP P7 = 1.075"SQ PGA 66 Pins With Shoulder Options N = None Memory Speed, ns * Screened to the individual test methods of MIL-STD-883 Specifications subject to change without notice Aeroflex Circuit Technology 35 South Service Road Plainview New York 11803 www.aeroflex.com Aeroflex Circuit Technology Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: (800) 843-1553 E-Mail: sales-act@aeroflex.com 20 SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700 A