1
CD4510BMS, CD4516BMS
CMOS Presettable Up/Down Counters
CD4510BMS Presettable BCD Up/Down Counter and the
CD4516BMS Presettable Binary Up/Down counter consist of
four synchronously clocked D-type flip-flops (with a gating
structure to provide T-type flip-flop capability) connected as
counters. These counters can be cleared by a high level on
the RESET line, and can be preset to any binary number
present on the jam inputs by a high level on the PRESET
ENABLE line. The CD4510BMS will count out of non-BCD
counter states in a maximum of two clock pulses in the up
mode, and a maximum of four clock pulses in the down mode.
If the CARRY IN input is held low, the counter advances up or
down on each positive-going clock transition. Synchronous
cascading is accomplished by connecting all clock inputs in
parallel and connecting the CARRY OUT of a less significant
stage to the CARRY IN of a more significant stage .
The CD4510BMS and CD4516BMS can be cascaded in the
ripple mode by connecting the CARRY OUT to the clock of
the next stage. If the UP/DOWN input changes during a ter-
minal count, the CARRY OUT must be gated with the clock,
and the UP/DOWN input must change while the clock is
high. This method provides a clean clock signal to the sub-
sequent counting stage. (See Figures 13, 14.)
These devices are similar to types MC14510 and MC14516.
The CD4510BMS and CD4516BMS are supplied in these
16-lead outline packages:
Features
• High Voltage Types (20V Rating)
• CD4510BMS - BCD Type
• CD4516BMS - Binary Type
• Medium Speed Operation
- fCL = 8MHz Typ. at 10V
• Synchronous Internal Carry Propagation
• Reset and Preset Capability
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Up/Down Difference Counting
• Multistage Synchronous Counting
• Multistage Ripple Counting
• Synchronous Frequency Dividers
Pinout
CD4510BMS, CD4516BMS
TOP VIEW
Functional Diagram
Braze Seal DIP *H4W †H45
Frit Seal DIP *FBF †H1F
Ceramic Flatpack H6W
*CD4510B Only †CD4516B Only
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
PRESET ENABLE
Q4
P4
P1
CARRY IN
Q1
VSS
CARRY OUT
VDD
Q3
P3
P2
Q2
UP/DOWN
RESET
CLOCK
Q1
Q2
Q3
Q4
6
11
14
2
P1
P2
P3
P4
4
12
13
3
CARRY OUT
7
CARRY IN 5
RESET
CLOCK
UP/DOWN 10
15
PRESET ENABLE
VDD = 16
VSS = 8
1
9
Data Sheet December 1992 File Number 3338
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
2
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . .-0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ±1/32 Inch (1.59mm ±0.79mm) from case for
10s Maximum
Thermal Resistance. . . . . . . . . . . . . . . . θja θjc
Ceramic DIP and FRIT Package . . . . 80oC/W 20oC/W
Flatpack Package. . . . . . . . . . . . . . . . 70oC/W 20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . .500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-10µA
2 +125oC - 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55oC-10µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low
(Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
Input Voltage High
(Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
Input Voltage Low
(Note 2) VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC- 4 V
Input Voltage High
(Note 2) VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC11 - V
NOTES: 1. All voltages referenced to device GND, 100% testing being im-
plemented.
2. Go/No Go test with limits applied to inputs.
3. Foraccuracy,voltage is measureddifferentially to VDD.Limitis
0.050V max.
CD4510BMS, CD4516BMS
3
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Propagation Delay
Clock to Q Output TPHL1
TPLH1 VDD = 5V, VIN = VDD or GND 9 +25oC - 400 ns
10, 11 +125oC, -55oC - 540 ns
Propagation Delay
Preset or Reset to Q TPHL2
TPLH2 VDD = 5V, VIN = VDD or GND 9 +25oC - 420 ns
10, 11 +125oC, -55oC - 567 ns
Propagation Delay
Clock to Carry Out TPHL3
TPLH3 VDD = 5V, VIN = VDD or GND 9 +25oC - 480 ns
10, 11 +125oC, -55oC - 648 ns
Propagation Delay
Carry In to Carry Out TPHL4
TPLH4 VDD = 5V, VIN = VDD or GND 9 +25oC - 250 ns
10, 11 +125oC, -55oC - 338 ns
Propagation Delay
Preset or Reset to Carry
Out
TPHL5
TPLH5 VDD = 5V, VIN = VDD or GND
(Note 3) 9 +25oC - 640 ns
10, 11 +125oC, -55oC - 864 ns
Transition Time TTHL
TTLH VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
10, 11 +125oC, -55oC - 270 ns
Maximum Clock Input Fre-
quency FCL VDD = 5V, VIN = VDD or GND 9 +25oC 2 - MHz
10, 11 +125oC, -55oC 1.48 - MHz
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
3. Reset to Carry Out (TPLH) only.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA
+125oC - 150 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA
+125oC - 300 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA
+125oC - 600 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -
55oC-50mV
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -
55oC-50mV
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -
55oC4.95 - V
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -
55oC9.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA
CD4510BMS, CD4516BMS
4
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -1.6 mA
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
-55oC - -4.2 mA
Input Voltage Low VIL VDD = 10V, VOH > 9V, V OL < 1V 1, 2 +25oC, +125oC, -
55oC-3V
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -
55oC+7 - V
Propagation Delay
Clock to Q Output TPHL1
TPLH1 VDD = 10V 1, 2, 3 +25oC - 200 ns
VDD = 15V 1, 2, 3 +25oC - 150 ns
Propagation Delay
Preset or Reset to Q TPHL2
TPLH2 VDD = 10V 1, 2, 3 +25oC - 210 ns
VDD = 15V 1, 2, 3 +25oC - 160 ns
Propagation Delay
Clock to Carry Out TPHL3
TPLH3 VDD = 10V 1, 2, 3 +25oC - 240 ns
VDD = 15V 1, 2, 3 +25oC - 180 ns
Propagation Delay
Carry In to Carry Out TPHL4
TPLH4 VDD = 10V 1, 2, 3 +25oC - 120 ns
VDD = 15V 1, 2, 3 +25oC - 100 ns
Propagation Delay Preset
or Reset to Carry Out TPHL5
TPLH5 VDD = 10V 1, 2, 3, 4 +25oC - 320 ns
VDD = 15V 1, 2, 3, 4 +25oC - 250 ns
Transition Time TTLH
TTHL VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns
Maximum Clock Input Fre-
quency FCL VDD = 10V 1, 2 +25oC 4 - MHz
VDD = 15V 1, 2 +25oC 5.5 - MHz
Minimum Hold Time
Preset Enable to JN TH VDD = 5V 1, 2, 3 +25oC - 70 ns
VDD = 10V 1, 2, 3 +25oC - 40 ns
VDD = 15V 1, 2, 3 +25oC - 40 ns
MinimumDataSetup Time
Preset Enable to JN TS VDD = 5V 1, 2, 3 +25oC - 25 ns
VDD = 10V 1, 2, 3 +25oC - 10 ns
VDD = 15V 1, 2, 3 +25oC - 10 ns
Minimum Data Hold Time
Clock to Carry In TH VDD = 5V 1, 2, 3 +25oC - 60 ns
VDD = 10V 1, 2, 3 +25oC - 30 ns
VDD = 15V 1, 2, 3 +25oC - 30 ns
Minimum Clock Hold Time
Clock to Up/Down TH VDD = 5V 1, 2, 3 +25oC - 30 ns
VDD = 10V 1, 2, 3 +25oC - 30 ns
VDD = 15V 1, 2, 3 +25oC - 30 ns
Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial
design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Reset to Carry Out (TPLH) only.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
CD4510BMS, CD4516BMS
5
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage
Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage
Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL
TPLH VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x
+25oC
Limit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER SYMBOL DELTA LIMIT
Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP MIL-STD-883
METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS MIL-STD-883
METHOD
TEST READ AND RECORD
PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4
CD4510BMS, CD4516BMS
6
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION OPEN GROUND VDD 9V ± -0.5V
OSCILLATOR
50kHz 25kHz
CD4510BMS
Static Burn-In 1
(Note 1) 2, 6, 7, 11, 14 1,3-5,8-10, 12, 13,
15 16
Static Burn-In 2
(Note 1) 2, 6, 7, 11, 14 8 1, 3-5,9,10, 12,13,
15, 16
Dynamic Burn-
In (Note 1) - 1, 3, 4, 8, 9, 12, 13 10, 16 2, 6, 7, 11, 14 15 5
Irradiation
(Note 2) 2, 6, 7, 11, 14 8 1, 3-5,9,10, 12,13,
15, 16
NOTES:
1. Each pin except VDD and GND will ha ve a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagrams
FIGURE 1. CD4510BMS
P
Q
QPE
C
T
P1*
4Q1
6
9
RESET*
P
Q
QPE
C
T
P2*
12 Q2
11
P
Q
QPE
C
T
P3*
13 Q3
14
P
Q
QPE
C
T
P4*
3Q4
2
PRESET*
ENABLE
1
15
CLOCK*7
CARRY OUT
U/D Q4 Q3Q4
U/D Q2
U/D Q3 U/D U/D
Q2
Q3U/D
Q2
Q3Q3 Q4
Q4
Q4Q3Q3Q2Q2Q1
5
CARRY IN*
10
UP/DOWN*
Q1
U/D
U/D
VDD
VSS
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
U/D Q4Q2Q2
CD4510BMS, CD4516BMS
7
FIGURE 2. CD4516BMS
TRUTH TABLE
CL CI U/D PE R ACTION
X 1 X 0 0 NO COUNT
0100COUNT UP
0000COUNT DOWN
X X X 1 0 PRESET
XXXX1RESET
X = DON’T CARE
Logic Diagrams (Continued)
P
Q
QPE
C
T
P1*
4Q1
6
9
RESET*
P
Q
QPE
C
T
P2*
12 Q2
11
P
Q
QPE
C
T
P3*
13 Q3
14
P
Q
QPE
C
T
P4*
3Q4
2
PRESET*
ENABLE
1
15
CLOCK*7
CARRY OUT
U/D Q3Q4
U/D U/D U/D
Q2
Q3U/D
Q2
Q3
Q4
Q4Q3Q3Q2Q2Q1
5
CARRY IN*
10
UP/DOWN*
Q1
U/D
U/D
VDD
VSS
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
U/D Q2Q2Q2
Q3Q4Q2
CD4510BMS, CD4516BMS
8
Typical Performance Characteristics
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 7. TYPICAL TRANSITION TIME vs LOAD
CAPACITANCE FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE FOR CLOCK-TO-Q OUTPUTS
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE V OLTAGE (VGS) = 15V
0 5 10 15
15
10
5
20
25
30
DRAIN-T O-SOURCE V OLTAGE (VDS) (V)
OUTPUT LO W (SINK) CURRENT (IOL) (mA)
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE V OLTAGE (VGS) = 15V
0 5 10 15
7.5
5.0
2.5
10.0
12.5
15.0
DRAIN-T O-SOURCE V OLTAGE (VDS) (V)
OUTPUT LO W (SINK) CURRENT (IOL) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE V OLTAGE (VGS) = -5V
0
-5
-10
-15
DRAIN-T O-SOURCE V OLTAGE (VDS) (V)
-20
-25
-30
0-5-10-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T A) = +25oC0
-5
-10
-15
DRAIN-T O-SOURCE V OLTAGE (VDS) (V) 0-5-10-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
GATE-TO-SOURCE V OLTAGE (VGS) = -5V
AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) (pF)
0 40 60 80 10020
0
50
100
150
200
SUPPLY V OLTAGE (VDD) = 5V
10V
15V
TRANSITION TIME (tTLH) (ns)
250
200
150
100
50
0 20 40 60 80 100
LOAD CAPACITANCE (CL) (pF)
PROPAGATION DELAY TIME (tPLH, tPHL) (ns)
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
CD4510BMS, CD4516BMS
9
FIGURE 9. TYPICALMAXIMUMCLOCKINPUTFREQUENCYvs
SUPPLY VOLTAGE FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION vs
FREQUENCY
Typical Performance Characteristics (Continued)
0
5
SUPPLY V OLTAGE (VDD)
AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) = 50pF
10
15
MAXIMUM CLOCK INPUT FREQUENCY
(fCL MAX) (MHz)
5101520
10V
5V
10V
8
6
4
2
8
6
4
2
104
103
10
POWER DISSIPATION PER GATE (PD) (µW)
SUPPLY VOLTS (VDD) = 15V
AMBIENT TEMPERATURE (TA)
tr, tf = 20ns
= +25oC
8
6
4
2
102
8642
INPUT FREQUENCY (fCL) (kHz)
01 1 8642 10 8642 1028642 1038642 104
CL = 15pF
CL = 50pF
Test Circuit and Waveform
FIGURE 11. PO WER DISSIPATION TEST CIRCUIT AND INPUT WAVEFORM
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CL
CL
CL
CL
CL
100µFID 500µF
PULSE
GENERATOR
50% 10%
90%
20ns
VDD
20ns
VARIABLE
WIDTH
VSS
Acquisition System
FIGURE 12. TYPICAL 16 CHANNEL, 10 BIT DATA ACQUISITION SYSTEM
16 CHANNEL
MULTIPLEXER
CD4067
SELECT
INPUTS
SAMPLE
AND
HOLD 10 BIT
A/D
CONVERTER
CONVERSION
LOGIC
Q1 Q4
CD4516BMS
AMPLI-
FIER
CLOCK PRESET ENABLE
END
CLOCK
START
ANALOG
DATA
INPUTS
PARALLEL
DATA
OUTPUTS
PRESET
INPUTS
NOTE:
This acquisition system can be operated in the random access mode by
jamming in the channel number at the present inputs, or in the sequential
mode by clocking the CD4516BMS.
CD4510BMS, CD4516BMS
10
Timing Diagrams
FIGURE 13. CD4510BMS
FIGURE 14. CD4516BMS
01234567898765432100967
CLOCK
CARRY IN
UP/DOWN
PE
P1
P2
P3
P4
Q1
Q2
Q3
Q4
CARRY OUT
COUNT 0
RESET
567891011121314159876543210015
CLOCK
CARRY IN
UP/DOWN
PE
P1
P2
P3
P4
Q1
Q2
Q3
Q4
CARRY OUT
COUNT 0
RESET
VDD
VSS
CD4510BMS, CD4516BMS
11
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
FIGURE 15. CASCADING COUNTER PACKAGES
* CARRY OUT lines at the 2nd, 3rd, etc., stages may have a negative-going glitch pulse resulting from differential delays of different CD4010/16BMS
IC’S. These negative going glitches do not affect proper CD4029BMS operation. However, if the CARRY OUT signals are used to trigger other edge-
sensitive logic devices, such as FF’S or counters, the CARRY OUT signals should be gated with the clock signal using a 2-input OR gate such as
CD4071BMS.
UP/D
R
PE
CL Q1 Q2 Q3 Q4
CI CO
J1 J2 J3 J4
CD4510/16BMS
UP/D
R
PE
CL Q1 Q2 Q3 Q4
CI CO
J1 J2 J3 J4 UP/D
R
PE
CL Q1 Q2 Q3 Q4
CI CO
J1 J2 J3 J4 *
UP/DOWN
PRESET
ENABLE
CLOCK
RESET
PARALLEL CLOCKING
CD4510/16BMS CD4510/16BMS
Ripple Clocking Mode: The up/down control can be changed at any count. The only restriction on changing the up/down control is that the
clock input to the first counting stage must be high. For cascading counters operating in a fixed up-count or down-count mode, the OR gates
are not required between stages, and CO is connected directly to the CL input of the next stage with CI grounded.
UP/D
R
PE
CL Q1 Q2 Q3 Q4
CI CO
J1 J2 J3 J4 UP/D
R
PE
CL Q1 Q2 Q3 Q4
CI CO
J1 J2 J3 J4 UP/D
R
PE
CL Q1 Q2 Q3 Q4
CI CO
J1 J2 J3 J4
UP/DOWN
PRESET
ENABLE
CLOCK
RESET
1/4 CD4071B
RIPPLE CLOCKING
CD4510/16BMS CD4510/16BMS CD4510/16BMS
CD4510BMS, CD4516BMS
