ADC081S101CISD/NOPB - NATIONAL SEMICONDUCTOR

ADC081S101

ADC081S101 Single Channel, 0.5 to 1 Msps, 8-Bit A/D Converter

Literature Number: SNAS310B

ADC081S101

January 13, 2010

Single Channel, 0.5 to 1 Msps, 8-Bit A/D Converter

General Description

The ADC081S101 is a low-power, single channel CMOS 8-

bit analog-to-digital converter with a high-speed serial inter-

face. Unlike the conventional practice of specifying perfor-

mance at a single sample rate only, the ADC081S101 is fully

specified over a sample rate range of 500 ksps to 1 Msps. The

converter is based upon a successive-approximation register

architecture with an internal track-and-hold circuit.

The output serial data is straight binary, and is compatible with

several standards, such as SPI™, QSPI™, MICROWIRE,

and many common DSP serial interfaces.

The ADC081S101 operates with a single supply that can

range from +2.7V to +5.25V. Normal power consumption us-

ing a +3V or +5V supply is 2.0 mW and 10.0 mW, respectively.

The power-down feature reduces the power consumption to

just 2.5 µW using a +5V supply.

The ADC081S101 is packaged in an 6-lead LLP and SOT-23

packages. Operation over the industrial temperature range of

−40°C to +85°C is guaranteed.

Features

■Specified over a range of sample rates.

■6-lead LLP and SOT-23 packages

■Variable power management

■Single power supply with 2.7V - 5.25V range

■SPI™/QSPI™/MICROWIRE/DSP compatible

Key Specifications

■DNL ± 0.07 LSB (typ)

■INL ± 0.05 LSB (typ)

■SNR 49.7 dB (typ)

■Power Consumption

■—3V Supply 2.0 mW (typ)

—5V Supply 10.0 mW (typ)

Applications

■Portable Systems

■Remote Data Aquisitions

■Instrumentation and Control Systems

Pin-Compatible Alternatives by Resolution and Speed

All devices are fully pin and function compatible.

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC121S021 ADC121S051 ADC121S101

10-bit ADC101S021 ADC101S051 ADC101S101

8-bit ADC081S021 ADC081S051 ADC081S101

Connection Diagram

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Ordering Information

Order Code Temperature Range Description Top Mark

ADC081S101CISD −40°C to +85°C 6-Lead LLP Package X3C

ADC081S101CISDX −40°C to +85°C 6-Lead LLP Package, Tape & Reel X3C

ADC081S101CIMF −40°C to +85°C 6-Lead SOT-23 Package X03C

ADC081S101CIMF −40°C to +85°C 6-Lead SOT-23 Package, Tape and Reel X03C

ADC081S101EVAL SOT-23 Evaluation Board

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

ADC081S101 Single Channel, 0.5 to 1 Msps, 8-Bit A/D Converter

Block Diagram

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Pin Descriptions and Equivalent Circuits

Pin No. Symbol Description

ANALOG I/O

3VIN Analog input. This signal can range from 0V to VA.

DIGITAL I/O

4 SCLK Digital clock input. This clock directly controls the conversion and readout processes.

5 SDATA Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin.

6 CS Chip select. On the falling edge of CS, a conversion process begins.

POWER SUPPLY

1VA

Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to

GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin.

2 GND The ground return for the supply and signals.

PAD GND For package suffix CISD(X) only, it is recommended that the center pad should be connected to ground.

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ADC081S101

Absolute Maximum Ratings (Note 1, Note

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Analog Supply Voltage VA−0.3V to 6.5V

Voltage on Any Pin to GND −0.3V to (VA +0.3)V

Input Current at Any Pin (Note 3) ±10 mA

Package Input Current (Note 3) ±20 mA

Power Consumption at TA = 25°C See (Note 4)

ESD Susceptibility (Note 5)

Human Body Model

Machine Model

3500V

300V

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

Operating Ratings (Note 1, Note 2)

Operating Temperature Range −40°C ≤ TA ≤ +85°C

VA Supply Voltage +2.7V to +5.25V

Digital Input Pins Voltage Range

(regardless of supply voltage) −0.3V to +5.25V

Clock Frequency 25 kHz to 20 MHz

Sample Rate Up to 1 Msps

Analog Input Voltage 0V to VA

Package Thermal Resistance

Package θJA

6-lead LLP 94°C / W

6-lead SOT-23 265°C / W

Soldering process must comply with National

Semiconductor's Reflow Temperature Profile specifications.

Refer to www.national.com/packaging. (Note 6)

ADC081S101 Converter Electrical Characteristics (Note 7, Note 9)

The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 10 MHz to 20 MHz, CL = 15 pF,

fSAMPLE = 500 ksps to 1 Msps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.

Symbol Parameter Conditions Typical Limits

(Note 9)Units

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 8Bits

INL Integral Non-Linearity VA = +2.7V to +5.25V ±0.05 ±0.3 LSB (max)

DNL Differential Non-Linearity VA = +2.7V to +5.25V ±0.07 ±0.3 LSB (max)

VOFF Offset Error VA = +2.7V to +5.25V ±0.03 ±0.3 LSB (max)

GE Gain Error VA = +2.7V to +5.25V ±0.08 ±0.4 LSB (max)

TUE Total Unadjusted Error VA = +2.7V to +5.25V ±0.07 ±0.3 LSB (max)

DYNAMIC CONVERTER CHARACTERISTICS

SINAD Signal-to-Noise Plus Distortion

Ratio

VA = +2.7 to 5.25V

fIN = 100 kHz, −0.02 dBFS 49.7 49 dB (min)

SNR Signal-to-Noise Ratio VA = +2.7 to 5.25V

fIN = 100 kHz, −0.02 dBFS 49.7 dB (min)

THD Total Harmonic Distortion VA = +2.7 to 5.25V

fIN = 100 kHz, −0.02 dBFS −77 −65 dB (max)

SFDR Spurious-Free Dynamic Range VA = +2.7 to 5.25V

fIN = 100 kHz, −0.02 dBFS 68 65 dB (min)

ENOB Effective Number of Bits VA = +2.7 to 5.25V

fIN = 100 kHz, −0.02 dBFS 7.9 7.8 Bits (min)

IMD

Intermodulation Distortion, Second

Order Terms

VA = +5.25V

fa = 103.5 kHz, fb = 113.5 kHz −68 dB

Intermodulation Distortion, Third

Order Terms

VA = +5.25V

fa = 103.5 kHz, fb = 113.5 kHz −68 dB

FPBW -3 dB Full Power Bandwidth VA = +5V 11 MHz

VA = +3V 8 MHz

ANALOG INPUT CHARACTERISTICS

VIN Input Range 0 to VAV

IDCL DC Leakage Current ±1 µA (max)

CINA Input Capacitance Track Mode 30 pF

Hold Mode 4 pF

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ADC081S101

Symbol Parameter Conditions Typical Limits

(Note 9)Units

DIGITAL INPUT CHARACTERISTICS

VIH Input High Voltage VA = +5.25V 2.4 V (min)

VA = +3.6V 2.1

VIL Input Low Voltage VA = +5V 0.8 V (max)

VA = +3V 0.4 V (max)

IIN Input Current VIN = 0V or VA±10 nA ±1 µA (max)

CIND Digital Input Capacitance 2 4pF (max)

DIGITAL OUTPUT CHARACTERISTICS

VOH Output High Voltage ISOURCE = 200 µA VA − 0.07 VA − 0.2 V (min)

ISOURCE = 1 mA VA − 0.1 V

VOL Output Low Voltage ISINK = 200 µA 0.03 0.4 V (max)

ISINK = 1 mA 0.1 V

IOZL, IOZH TRI-STATE® Leakage Current ±0.1 ±10 µA (max)

COUT TRI-STATE® Output Capacitance 2 4pF (max)

Output Coding Straight (Natural) Binary

POWER SUPPLY CHARACTERISTICS

VASupply Voltage 2.7 V (min)

5.25 V (max)

Supply Current, Normal Mode

(Operational, CS low)

VA = +5.25V, fSAMPLE = 1 Msps SOT-23 2.0 3.2 mA (max)

LLP 2.6

VA = +3.6V, fSAMPLE = 1 Msps SOT-23 0.6 1.5 mA (max)

LLP 1.1

Supply Current, Shutdown (CS high)

VA = +5.25V, fSCLK = 0 MHz, fSAMPLE = 0

ksps 500 nA

VA = +5.25V, fSCLK = 20 MHz,

fSAMPLE = 0 ksps 60 µA

Power Consumption, Normal Mode

(Operational, CS low)

VA = +5V SOT-23 10 16 mW (max)

LLP 13

VA = +3V SOT-23 2.0 4.5 mW (max)

LLP 3.3

Power Consumption, Shutdown

(CS high)

VA = +5V, fSCLK = 0 MHz,

fSAMPLE = 0 ksps 2.5 µW

VA = +5V, fSCLK = 20 MHz,

fSAMPLE = 0 ksps 300 µW

AC ELECTRICAL CHARACTERISTICS

fSCLK Clock Frequency (Note 8) 10 MHz (min)

20 MHz (max)

fSSample Rate (Note 8)50 500 ksps (min)

1Msps (max)

tHOLD Hold Time 13 SCLk Falling

Edges

DC SCLK Duty Cycle fSCLK = 20 MHz 50 40 % (min)

60 % (max)

tACQ

Minimum Time Required for

Acquisition 350 ns (max)

tQUIET (Note 11) 50 ns (min)

tAD Aperture Delay 3 ns

tAJ Aperture Jitter 30 ps

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ADC081S101

ADC081S101 Timing Specifications

The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 10.0 MHz to 20.0 MHz, CL = 25 pF,

fSAMPLE = 500 ksps to 1 Msps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.

Symbol Parameter Conditions Typical Limits Units

tCS Minimum CS Pulse Width 10 ns (min)

tSU CS to SCLK Setup Time 10 ns (min)

tEN

Delay from CS Until SDATA TRI-STATE® Disabled

(Note 12) 20 ns (max)

tACC Data Access Time after SCLK Falling Edge (Note 13)VA = +2.7 to +3.6 40 ns (max)

VA = +4.75 to +5.25 20 ns (max)

tCL SCLK Low Pulse Width 0.4 x tSCLK ns (min)

tCH SCLK High Pulse Width 0.4 x tSCLK ns (min)

tHSCLK to Data Valid Hold Time VA = +2.7 to +3.6 7ns (min)

VA = +4.75 to +5.25 5ns (min)

tDIS

SCLK Falling Edge to SDATA High Impedance (Note

14)

VA = +2.7 to +3.6 25 ns (max)

6ns (min)

VA = +4.75 to +5.25 25 ns (max)

5ns (min)

tPOWER-UP Power-Up Time from Full Power-Down 1 µs

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 20

mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute

Maximum Rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the

junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDmax = (TJmax − TA) / θJA. The values

for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven

beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms.

Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.

Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under

Operating Ratings.

Note 9: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Note 10: This condition is for fSCLK = 20 MHz.

Note 11: Minimum Quiet Time required by bus relinquish and the start of the next conversion.

Note 12: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V.

Note 13: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V or 2.0V.

Note 14: tDIS is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 1. The measured number is then adjusted

to remove the effects of charging or discharging the output capacitance. This means that tDIS is the true bus relinquish time, independent of the bus loading.

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ADC081S101

Timing Diagrams

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FIGURE 1. Timing Test Circuit

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FIGURE 2. ADC081S101 Serial Timing Diagram

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ADC081S101

Specification Definitions

ACQUISITION TIME is the time required to acquire the input

voltage. That is, it is time required for the hold capacitor to

charge up to the input voltage. Acquisition time is measured

backwards from the falling edge of CS when the signal is

sampled and the part moves from track to hold. The start of

the time interval that contains TACQ is the 13th rising edge of

SCLK of the previous conversion when the part moves from

hold to track. The user must ensure that the time between the

13th rising edge of SCLK and the falling edge of the next

CS is not less than TACQ to meet performance specifications.

APERTURE DELAYis the time after the falling edge of CS

when the input signal is acquired or held for conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the

variation in aperture delay from sample to sample. Aperture

jitter manifests itself as noise in the output.

CONVERSION TIME is the time required, after the input volt-

age is acquired, for the ADC to convert the input voltage to a

digital word. This is from the falling edge of CS when the input

signal is sampled to the 16th falling edge of SCLK when the

SDATA output goes into TRI-STATE.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital

waveform is high to the total time of one period. The specifi-

cation here refers to the SCLK.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion or SINAD. ENOB is defined as

(SINAD − 1.76) / 6.02 and says that the converter is equiva-

lent to a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input.

GAIN ERROR is the deviation of the last code transition

(111...110) to (111...111) from the ideal (VREF − 1 LSB), after

adjusting for offset error.

INTEGRAL NON-LINEARITY (INL) is a measure of the de-

viation of each individual code from a line drawn from negative

full scale (½ LSB below the first code transition) through pos-

itive full scale (½ LSB above the last code transition). The

deviation of any given code from this straight line is measured

from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of

additional spectral components as a result of two sinusoidal

frequencies being applied to the ADC input at the same time.

It is defined as the ratio of the power in the second and third

order intermodulation products to the sum of the power in both

of the original frequencies. IMD is usually expressed in dB.

MISSING CODES are those output codes that will never ap-

pear at the ADC outputs. The ADC081S101 is guaranteed not

to have any missing codes.

OFFSET ERROR is the deviation of the first code transition

(000...000) to (000...001) from the ideal (i.e. GND + 1 LSB).

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal to the rms value of the

sum of all other spectral components below one-half the sam-

pling frequency, not including harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or

SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral com-

ponents below half the clock frequency, including harmonics

but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the desired signal amplitude

to the amplitude of the peak spurious spectral component,

where a spurious spectral component is any signal present in

the output spectrum that is not present at the input and may

or may not be a harmonic.

TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-

pressed in dB or dBc, of the rms total of the first five harmonic

components at the output to the rms level of the input signal

frequency as seen at the output. THD is calculated as

where Af1 is the RMS power of the input frequency at the out-

put and Af2 through Af6 are the RMS power in the first 5

harmonic frequencies.

TOTAL UNADJUSTED ERROR is the worst deviation found

from the ideal transfer function. As such, it is a comprehensive

specification which includes full scale error, linearity error,

and offset error.

THROUGHPUT TIME is the minimum time required between

the start of two successive conversion. It is the acquisition

time plus the conversion time.

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ADC081S101

Typical Performance Characteristics

TA = +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 10 MHz to 20 MHz, fIN = 100 kHz unless otherwise stated.

DNL

fSCLK = 10 MHz

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INL

fSCLK = 10 MHz

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DNL

fSCLK = 20 MHz

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INL

fSCLK = 20 MHz

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DNL vs Clock Frequency

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INL vs Clock Frequency

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ADC081S101

Total Unadjusted Error vs Clock Frequency

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SNR vs Clock Frequency

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SINAD vs. Clock Frequency

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THD vs. Clock Frequency

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SFDR vs. Clock Frequency

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Spectral Response, VA = 5V

fSCLK = 10 MHz

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ADC081S101

Spectral Response, VA = 5V

fSCLK = 20 MHz

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Power Consumption vs. Throughput,

fSCLK = 20 MHz

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ADC081S101

Applications Information

1.0 ADC081S101 OPERATION

The ADC081S101 is a successive-approximation analog-to-

digital converter designed around a charge-redistribution dig-

ital-to-analog converter core. Simplified schematics of the

ADC081S101 in both track and hold operation are shown in

Figures 3 and 4, respectively. In Figure 3, the device is in track

mode: switch SW1 connects the sampling capacitor to the in-

put, and SW2 balances the comparator inputs. The device is

in this state until CS is brought low, at which point the device

moves to hold mode.

Figure 4 shows the device in hold mode: switch SW1 con-

nects the sampling capacitor to ground, maintaining the sam-

pled voltage, and switch SW2 unbalances the comparator.

The control logic then instructs the charge-redistribution DAC

to add or subtract fixed amounts of charge from the sampling

capacitor until the comparator is balanced. When the com-

parator is balanced, the digital word supplied to the DAC is

the digital representation of the analog input voltage. The de-

vice moves from hold mode to track mode on the 13th rising

edge of SCLK.

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FIGURE 3. ADC081S101 in Track Mode

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FIGURE 4. ADC081S101 in Hold Mode

2.0 USING THE ADC081S101

The serial interface timing diagram for the ADC is shown in

Figure 2. CS is chip select, which initiates conversions on the

ADC and frames the serial data transfers. SCLK (serial clock)

controls both the conversion process and the timing of serial

data. SDATA is the serial data out pin, where a conversion

result is found as a serial data stream.

Basic operation of the ADC begins with CS going low, which

initiates a conversion process and data transfer. Subsequent

rising and falling edges of SCLK will be labelled with reference

to the falling edge of CS; for example, "the third falling edge

of SCLK" shall refer to the third falling edge of SCLK after

CS goes low.

At the fall of CS, the SDATA pin comes out of TRI-STATE,

and the converter moves from track mode to hold mode. The

input signal is sampled and held for conversion on the falling

edge of CS. The converter moves from hold mode to track

mode on the 13th rising edge of SCLK (see Figure 2). It is at

this point that the interval for the TACQ specification begins. In

the worst case, 350 ns must pass between the 13th rising

edge and the next falling edge of SCLK. The SDATA pin will

be placed back into TRI-STATE after the 16th falling edge of

SCLK, or at the rising edge of CS, whichever occurs first. After

a conversion is completed, the quiet time tQUIET must be sat-

isfied before bringing CS low again to begin another conver-

sion.

Sixteen SCLK cycles are required to read a complete sample

from the ADC. The sample bits (including leading or trailing

zeroes) are clocked out on falling edges of SCLK, and are

intended to be clocked in by a receiver on subsequent falling

edges of SCLK. The ADC will produce three leading zero bits

on SDATA, followed by eight data bits, most significant first.

After the data bits, the ADC will clock out four trailing zeros.

If CS goes low before the rising edge of SCLK, an additional

(fourth) zero bit may be captured by the next falling edge of

SCLK.

2.1 Determining Throughput

Throughput depends on the frequency of SCLK and how

much time is allowed to elapse between the end of one con-

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ADC081S101

version and the start of another. At the maximum specified

SCLK frequency, the maximum guaranteed throughput is ob-

tained by using a 20 SCLK frame. As shown in Figure 2, the

minimum allowed time between CS falling edges is deter-

mined by 1) 12.5 SCLKs for Hold mode, 2) the larger of two

quantities: either the minimum required time for Track mode

(tACQ) or 2.5 SCLKs to finish reading the result and 3) 0, 1/2

or 1 SCLK padding to ensure an even number of SCLK cycles

so there is a falling SCLK edge when CS next falls. For ex-

ample, at the fastest rate for this family of parts, SCLK is

20MHz and 2.5 SCLKs are 125ns, so the minimum time be-

tween CS falling edges is calculated by:

12.5*50ns + 350ns + 0.5*50ns = 1000ns

(12.5 SCLKs + tACQ + 1/2 SCLK) which corresponds to a

maximum throughput of 1MSPS. At the slowest rate for this

family, SCLK is 1MHz. Using a 20-cycle conversion frame as

shown in Figure 2 yields a 20μs time between CS falling

edges for a throughput of 50KSPS.

It is possible, however, to use fewer than 20 clock cycles pro-

vided the timing parameters are met. With a 1MHz SCLK,

there are 2500ns in 2.5 SCLK cycles, which is greater than

tACQ. After the last data bit has come out, the clock will need

one full cycle to return to a falling edge. Thus the total time

between falling edges of CS is 12.5*1μs +2.5*1μs

+1*1μs=16μs which is a throughput of 62.5KSPS.

3.0 ADC081S101 TRANSFER FUNCTION

The output format of the ADC is straight binary. Code transi-

tions occur midway between successive integer LSB values.

The LSB width for the ADC is VA/256. The ideal transfer char-

acteristic is shown in Figure 5. The transition from an output

code of 0000 0000 to a code of 0000 0001 is at 1/2 LSB, or a

voltage of VA/512. Other code transitions occur at steps of one

LSB.

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FIGURE 5. Ideal Transfer Characteristic

4.0 TYPICAL APPLICATION CIRCUIT

A typical application of the ADC is shown in Figure 6. Power

is provided in this example by the National Semiconductor

LP2950 low-dropout voltage regulator, available in a variety

of fixed and adjustable output voltages. The power supply pin

is bypassed with a capacitor network located close to the

ADC. Because the reference for the ADC is the supply volt-

age, any noise on the supply will degrade device noise per-

formance. To keep noise off the supply, use a dedicated linear

regulator for this device, or provide sufficient decoupling from

other circuitry to keep noise off the ADC supply pin. Because

of the ADC's low power requirements, it is also possible to

use a precision reference as a power supply to maximize per-

formance. The four-wire interface is also shown connected to

a microprocessor or DSP.

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ADC081S101

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FIGURE 6. Typical Application Circuit

5.0 ANALOG INPUT

An equivalent circuit for the ADC's input channel is shown in

Figure 7. Diodes D1 and D2 provide ESD protection for the

analog inputs. At no time should any input go beyond (VA +

300 mV) or (GND − 300 mV), as these ESD diodes will begin

conducting, which could result in erratic operation. For this

reason, the ESD diodes should not be used to clamp the input

signal.

The capacitor C1 in Figure 7 has a typical value of 4 pF, and

is mainly the package pin capacitance. Resistor R1 is the on

resistance of the multiplexer and track / hold switch, and is

typically 500Ω. Capacitor C2 is the ADC sampling capacitor

and is typically 26 pF. The ADC will deliver best performance

when driven by a low-impedance source to eliminate distor-

tion caused by the charging of the sampling capacitance. This

is especially important when using the ADC to sample AC

signals. Also important when sampling dynamic signals is an

anti-aliasing filter.

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FIGURE 7. Equivalent Input Circuit

6.0 DIGITAL INPUTS AND OUTPUTS

The ADC digital inputs (SCLK and CS) are not limited by the

same absolute maximum ratings as the analog inputs. The

digital input pins are instead limited to +5.25V with respect to

GND, regardless of VA, the supply voltage. This allows the

ADC to be interfaced with a wide range of logic levels, inde-

pendent of the supply voltage.

7.0 MODES OF OPERATION

The ADC has two possible modes of operation: normal mode,

and shutdown mode. The ADC enters normal mode (and a

conversion process is begun) when CS is pulled low. The de-

vice will enter shutdown mode if CS is pulled high before the

tenth falling edge of SCLK after CS is pulled low, or will stay

in normal mode if CS remains low. Once in shutdown mode,

the device will stay there until CS is brought low again. By

varying the ratio of time spent in the normal and shutdown

modes, a system may trade-off throughput for power con-

sumption, with a sample rate as low as zero.

7.1 Normal Mode

The fastest possible throughput is obtained by leaving the

ADC in normal mode at all times, so there are no power-up

delays. To keep the device in normal mode continuously,

CS must be kept low until after the 10th falling edge of SCLK

after the start of a conversion (remember that a conversion is

initiated by bringing CS low).

If CS is brought high after the 10th falling edge, but before the

16th falling edge, the device will remain in normal mode, but

the current conversion will be aborted, and SDATA will return

to TRI-STATE (truncating the output word).

Sixteen SCLK cycles are required to read all of a conversion

word from the device. After sixteen SCLK cycles have

elapsed, CS may be idled either high or low until the next

conversion. If CS is idled low, it must be brought high again

before the start of the next conversion, which begins when

CS is again brought low.

After sixteen SCLK cycles, SDATA returns to TRI-STATE.

Another conversion may be started, after tQUIET has elapsed,

by bringing CS low again.

7.2 Shutdown Mode

Shutdown mode is appropriate for applications that either do

not sample continuously, or it is acceptable to trade through-

put for power consumption. When the ADC is in shutdown

mode, all of the analog circuitry is turned off.

To enter shutdown mode, a conversion must be interrupted

by bringing CS back high anytime between the second and

tenth falling edges of SCLK, as shown in Figure 8. Once CS

has been brought high in this manner, the device will enter

shutdown mode; the current conversion will be aborted and

SDATA will enter TRI-STATE. If CS is brought high before the

second falling edge of SCLK, the device will not change

mode; this is to avoid accidentally changing mode as a result

of noise on the CS line.

13 www.national.com

ADC081S101

20145716

FIGURE 8. Entering Shutdown Mode

20145717

FIGURE 9. Entering Normal Mode

To exit shutdown mode, bring CS back low. Upon bringing

CS low, the ADC will begin powering up (power-up time is

specified in the Timing Specifications table). This power-up

delay results in the first conversion result being unusable. The

second conversion performed after power-up, however, is

valid, as shown in Figure 9.

If CS is brought back high before the 10th falling edge of

SCLK, the device will return to shutdown mode. This is done

to avoid accidentally entering normal mode as a result of

noise on the CS line. To exit shutdown mode and remain in

normal mode, CS must be kept low until after the 10th falling

edge of SCLK. The ADC will be fully powered-up after 16

SCLK cycles.

8.0 POWER MANAGEMENT

The ADC takes time to power-up, either after first applying

VA, or after returning to normal mode from shutdown mode.

This corresponds to one "dummy" conversion for any SCLK

frequency within the specifications in this document. After this

first dummy conversion, the ADC will perform conversions

properly. Note that the tQUIET time must still be included be-

tween the first dummy conversion and the second valid con-

version.

When the VA supply is first applied, the ADC may power up

in either of the two modes: normal or shutdown. As such, one

dummy conversion should be performed after start-up, as de-

scribed in the previous paragraph. The part may then be

placed into either normal mode or the shutdown mode, as

described in Sections 7.1 and 7.2.

When the ADC is operated continuously in normal mode, the

maximum guaranteed throughput is fSCLK / 20 at the maximum

specified fSCLK. Throughput may be traded for power con-

sumption by running fSCLK at its maximum specified rate and

performing fewer conversions per unit time, raising the ADC

CS line after the 10th and before the 15th fall of SCLK of each

conversion. A plot of typical power consumption versus

throughput is shown in the Typical Performance Curves sec-

tion. To calculate the power consumption for a given through-

put, multiply the fraction of time spent in the normal mode by

the normal mode power consumption and add the fraction of

time spent in shutdown mode multiplied by the shutdown

mode power consumption. Note that the curve of power con-

sumption vs. throughput is essentially linear. This is because

the power consumption in the shutdown mode is so small that

it can be ignored for all practical purposes.

9.0 POWER SUPPLY NOISE CONSIDERATIONS

The charging of any output load capacitance requires current

from the power supply, VA. The current pulses required from

the supply to charge the output capacitance will cause voltage

variations on the supply. If these variations are large enough,

they could degrade SNR and SINAD performance of the ADC.

Furthermore, discharging the output capacitance when the

digital output goes from a logic high to a logic low will dump

current into the die substrate, which is resistive. Load dis-

charge currents will cause "ground bounce" noise in the sub-

strate that will degrade noise performance if that current is

large enough. The larger the output capacitance, the more

current flows through the die substrate and the greater is the

noise coupled into the analog channel, degrading noise per-

formance.

To keep noise out of the power supply, keep the output load

capacitance as small as practical. It is good practice to use a

100Ω series resistor at the ADC output, located as close to

the ADC output pin as practical. This will limit the charge and

discharge current of the output capacitance and improve

noise performance.

www.national.com 14

ADC081S101

Physical Dimensions inches (millimeters) unless otherwise noted

6-Lead LLP

Order Number ADC081S101CISD or ADC081S101CISDX

NS Package Number SDB06A

6-Lead SOT-23

Order Number ADC081S101CIMF, ADC081S101CIMFX

NS Package Number MF06A

15 www.national.com

ADC081S101

Notes

ADC081S101 Single Channel, 0.5 to 1 Msps, 8-Bit A/D Converter

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