ANALOG DEVICES CMOS 220 MHz Pseudo-Color Graphics Triple 10-Bit Video RAM-DAC FEATURES 220 MHz, 10-Bit (30-Bit Gamma Corrected) Pseudo Color (Indexed-Color) Triple 10-Bit Gamma Correcting D/A Converters Triple 256 x 10 (256 x 30) Color Palette RAM (256 Colors out of 1 Billion) On-Chip Clock Control Circuit Palette Priority Select Registers RS-343A/RS-170 Compatible Analog Outputs TTL Compatible Digital Inputs Standard MPU I/O Interface 10-Bit Parallel Structure 8+2 Byte Structure Multiplexed Pixel Input Ports; 1:1, 2:1, 4:1 +5 V CMOS Monolithic Construction 100-Lead Plastic Quad Flatpack (QFP) Thermally Enhanced to Achieve 9), < 1.0C/W MODES OF OPERATION 8-Bit Pseudo Color @ 220 MHz @ 170 MHz @ 135 MHz @ 110 MHz @ 85 MHz APPLICATIONS High Resolution Graphics ADV7151 The ADV7151 (ADV*) is a complete analog output, Video RAM-DAC on a single CMOS monolithic chip. The part is spe- cifically designed for use in high performance, color graphics workstations. The ADV7151 integrates a number of graphic functions onto one device allowing 8-bit Pseudo-Color (Indexed- Color) operation at the maximum screen update rate of 220 MHz. The device consists of three, high speed, 10-bit, video D/A con- verters (RGB), three 256 x 10 (one 256 x 30) color look-up tables, palette priority selects, a pixel input data multiplexer/ serializer and a clock generator/divider circuit. The ADV7151 is capable of 1:1, 2:1 and 4:1 multiplexing. The on-board palette priority select inputs enable multiple palette devices to be con- nected together for use in multipalette and window applications. The part is controlled and programmed through the micropro- cessor (MPU) port. The part also contains a number of on-board test registers, associated with self diagnostic testing of the device. *ADV is a registered trademark of Analog Devices, Inc. (Continued on page 12) FUNCTIONAL BLOCK DIAGRAM Vaa 5 256-COLOR/GAMMA 8 PALETTE RAM ADV7151 | RED 10) _10-BIT loR 8 Pp 256 x 10 fe] RED DAC OR RED (R7-RO), ray | Jao 8 GREEN (G7-Go), x muxl 8, 8, GREEN 10. 10-BIT 10G BLUE (B7-B0) 8 L a a, Fr) 256 x 10 | GREEN DAC 0G COLOR DATA EY 7 | e ore ei 10). 10-BIT 10B aN pees 7?) BLUE DAC >I ioB ty PALETTE t S-NMux| 2 8 L a) a 7 SYNC I! P50, PS!) OUTPUT PLL (PSO, PS1) CONTROL REGISTERS SYNCOUT CLOCK CONTROL VOLTAGE Vrer LOADIN REGISTER commann |] DATATO | REFERENCE Reger LOADOUT CLOCK DIVIDE ee PALETTES CIRCUIT Comp & ADDRESS REGISTERS _ PRGCKOUT syncurowzation | AORESS oe 30 COLOR REGISTERS REVISION SCKIN CIRCUIT ADDR] REGISTER RED GREEN BLUE SCKOUT 132 =16, 8, -4, +2 (A7-A0) REGISTER | | REGISTER | | REGISTER SYNC eR CLOCK CLOCK MPU PORT | | ECL To CMOS $0 (@+2) GE Rw CO Ct D9 Do GND REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703C, = 10 pF); 10R, 106, ADV715 SPECIFICATIONS (Vy! = 45 V Voy = 41.28 ND. All specifications Tyiy to Tyax unless otherwise noted.) Rser = 280 . IOR, 106, 10B (R, = 37.5 Q, Parameter All Versions Unit Test Conditions/Comments STATIC PERFORMANCE Resolution (Each DAC) 10 Bits Accuracy (Each DAC) Integral Nonlinearity 1 LSB max Differential Nonlinearity +1 LSB max Guaranteed Monotonic Gray Scale Error +5 % Gray Scale max Coding Binary DIGITAL INPUTS (Excluding CLOCK, CLOCK) Input High Voltage, Vixyy 2 V min Input Low Voltage, Via 0.8 V max Input Current, Ip, +10 pA max Vin = 0.4 V or 2.4 V Input Capacitance, Cy; 10 pF typ CLOCK INPUTS (CLOCK, CLOCK) Input High Voltage, Ving Vaa 1.0 V min Input Low Voltage, Vin AA V max Input Current, Ipy +10 pA max Vin = 0.4 V or 2.4 V Input Capacitance, Cp, 10 pF typ DIGITAL OUTPUTS Output High Voltage, Vou 2.4 V min Ikource = 400 pA Output Low Voltage, Vor. 0.4 V max Ion = 3.2 mA Floating-State Leakage Current 20 pA max Floating-State Output Capacitance 20 pF typ ANALOG OUTPUTS Gray Scale Current Range 15 mA min 22 mA max Output Current White Level Relative to Blank 17.69 mA min Typically 19.05 mA 20.40 mA max White Level Relative to Black 16.74 mA min Typically 17.62 mA 18.50 mA max Black Level Relative to Blank 0.95 mA min Typically 1.44 mA 1.90 mA max Blank Level on IOR, IOB 0 pA min Typically 5 pA 50 pA max Blank Level on IOG 6.29 mA min Typically 7.62 mA : 8.96 mA max Sync Level on IOG 0 uA min Typically 5 pA 50 pA max LSB Size 17.22 pA typ DAC-to-DAC Matching 2 % max Typically 1% Output Compliance, Voc 0 V min +1.4 V max Output Impedance, Rour 100 kQ typ Output Capacitance, Copy 30 pF max Iour = OmA VOLTAGE REFERENCE Voltage Reference Range, Varr 1.14/1.26 V min/V max Vrrr = 1.235 V for Specified Performance Input Current, Ivper +5 pA typ POWER REQUIREMENTS Vaa 5 V nom I,a3 400 mA max 220 MHz Parts Tay 370 mA max 170 MHz Parts Tay 350 mA max 135 MHz Parts AA 330 mA max 110 MHz Parts AA 315 mA max 85 MHz Parts Power Supply Rejection Ratio 0.5 %/% max Typically 0.12%/%: COMP = 0.1 wF DYNAMIC PERFORMANCE Clock and Data Feedthrough* 30 dB typ Glitch Impulse 50 pV secs typ DAC-to-DAC Crosstalk 23 dB typ NOTES '+5% for all versions. Temperature range (T yyy to Tyax): 0C to +70C; T, (Silicon Junction Temperature) = 100C. Pixel Port is continuously clocked with data corresponding to a linear ramp. T, = 100C. *Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. *TTL input values are 0 to 3 volts, with input rise/fall times =3 ns, measured the 10% and 90% points. Timing reference points at 50% for inputs and outputs. *DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions. Specifications subject to change without notice. REV.AADV7151 TIMING CHARACTERISTICS! (v,2 = +5 ; Veer = +1.235 V; Reg, = 280 . JOR, 106, 108 (R, = 37.5 , 6, = 10 pF), (OR, 106, [0B = GND. All specifications Tyyiy to Tyay? unless otherwise noted.) CLOCK CONTROL AND PIXEL PORT* 220 MHz | 170 MHz | 135 MHz | 110 MHz | 85 MHz Parameter Version Version Version Version Version | Units Conditions/Comments feLocK 220 170 135 110 85 MHz max | Pixel CLOCK Rate t 4.55 5.88 7.4 9.1 11.77 ns min Pixel CLOCK Cycle Time tb 2 2.5 3.2 4 4 ns min Pixel CLOCK High Time ts 2 2.5 3 4 4 ns min Pixel CLOCK Low Time ty 10 10 10 10 10 ns max Pixel CLOCK to LOADOUT Delay fLoapin LOADIN Clocking Rate 1:1 Multiplexing | 110 110 110 110 85 MHz max 2:1 Multiplexing | 110 85 67.5 55 42.5 MHz max 4:1 Multiplexing | 55 42.5 42.5 33.75 27.5 21.25 MHz max ts LOADIN Cycle Time 1:1 Multiplexing | 9.1 9.1 9.1 9.1 11.76 ns min 2:1 Multiplexing | 9.1 11.76 14.8 18.18 23.53 ns min 4:1 Multiplexing | 18.18 23.53 29.63 36.36 47.1 ns min ly LOADIN High Time 1:1 Multiplexing | 4 4 4 4 4 ns min 2:1 Multiplexing | 4 5 6 8 9 ns min 4:1 Multiplexing | 8 9 12 15 18 ns min ty LOADIN Low Time 1:1 Multiplexing | 4 4 4 4 4 ns min 2:1 Multiplexing | 4 5 6 8 9 ns min 4:1 Multiplexing | 8 9 12 15 18 ns min ts 0 0 0 0 0 ns min Pixel Data Setup Time ty 5 5 5 5 5 ns min Pixel Data Hold Time to 0 0 0 0 0 ns min LOADOUT to LOADIN Delay Tty, 1-5 1-5 1-5 7-5 1-4 ns max LOADOUT to LOADIN Delay tpp Pipeline Delay 1:1 Multiplexing | 5 5 5 5 5 CLOCKs | (1 x CLOCK = 1,) 2:1 Multiplexing | 6 6 6 6 6 CLOCKs 4:1 Multiplexing | 8 8 8 8 8 CLOCKs tho 10 10 10 10 10 ns max Pixel CLOCK to PRGCKOUT Delay ty; 5 5 5 5 5 ns max SCKIN to SCKOUT Delay tis 5 5 5 5 5 ns min BLANK to SCKIN Setup Time ts 1 1 l 1 1 ns min BLANK to SCKIN Hold Time ANALOG OUTPUTS 220 MHz | 170 MHz | 135 MHz | 110 MHz | 85 MHz Parameter Version Version Version Version Version | Units Conditions/Comments tie 15 15 15 15 15 ns typ Analog Output Delay tiz 1 1 1 1 1 ns typ Analog Output Rise/Fall Time lis 15 15 15 15 15 ns typ Analog Output Transition Time ton 2 2 2 2 2 ns max Analog Output Skew (IOR, IOG, IOB) 0 0 0 0 0 ns typ MPU PORT 220 MHz | 170 MHz | 135 MHz | 110 MHz | 85 MHz Parameter Version Version Version Version Version | Units Conditions/Comments tio 3 3 3 3 3 ns min R/W, CO, Cl to CE Setup Time too 10 10 10 10 10 ns min R/W, C0, Cl to CE Hold Time toy 45 45 45 45 45 ns min CE Low Time ty 25 25 25 25 25 ns min CE High Time to3 5 5 5 5 5 ns min CE Asserted to Databus Driven to4 45 45 45 45 45 ns max CE Asserted to Data Valid tos 20 20 20 20 20 ns max CE Disabled to Databus Three-Stated 5 5 5 5 5 ns min tos 20 20 20 20 20 ns min Write Data (D0-D9) Setup Time tos 5 5 5 5 5 ns min Write Data (D0-D9) Hold Time REV.A 3-ADV7151 NOTES ITTL input values are 0 to 3 volts, with input rise/fall times = 3 ns, measured between the 10% and 90% points. ECL inputs (CLOCK, CLOCK) are V,4-0.8 V to Va,-1.8 V, with input rise/fall times < 2 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out- puts. Analog output load <= 10 pF. Databus (D0-D9) loaded as shown in Figure 1. Digital output load for LOADOUT, PRGCKOUT and SCKOUT = 30 pF. ?+5% for all versions. *Temperature range (Tyyjn to Trax); OC to +70C; T, (Silicon Junction Temperature) = 100C. *Pixel Port consists of the following inputs: Pixel Inputs: PO-P7 [A, B, C, D]; Palette Selects: PSO [A, B, C, D] PS1 [A, B, C, D]; Pixel Controls: SYNC, BLANK; Clock Inputs: CLOCK, CLOCK, LOADIN, SCKIN; Clock Outputs: LOADOUT, PRGCKOUT, SCKOUT. 5+ is the LOADOUT Cycle Time and is a function of the Pixel CLOCK Rate and the Multiplexing Mode: 1:1 multiplexing; 7 = CLOCK = t, ns: 2:1 multiplexing; t = CLOCK x 2 = 2 X t, ns: 4:1 multiplexing; 7 = CLOCK x 4 = 4 x t, ns. These fixed values for Pipeline Delay are valid under conditions where t,, and t-t,, are met. If either t,) or t-t,, are not met, the part will operate but the Pipeline Delay is increased by an additional 2 Clock Cycles for 2:1 Mode and is increased by an additional 4 Clock Cycles for 4:1 Mode, after calibration is performed. 7Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Output rise/fall time measured between the 10% and 90% points of full-scale transition. Transition time measured from the 50% point of full-scale transition to the output remaining within +] LSB. (Transition time does not include clock and data feedthrough.) *t), and t,, are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V. t,< is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging the 100 pF capacitor. This means that the time, t,,, quoted in the Timing Characteristics is the true value for the device and as such is independent of external databus loading capacitances. Specifications subject to change without notice. TO OUTPUT PIN lsource Figure 1. Load Circuit for Databus Access and Relinquish Times -| t, >| ts CLOCK Sf 308 YIN VIN VDDD DDS > wt, LOADOUT (1:1 MULTIPLEXING) Nf Nf Figure 2. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK} LOADOUT (2:1 MULTIPLEXING) LOADOUT {4:1 MULTIPLEXING) Sy NNN 4- REV.AADV7151 A LOADIN tgs > ty PIXEL INPUT VALID VALID VALID DATA* DATA DATA DATA *INCLUDES PIXEL DATA (P0-P7); PALETTE SELECT INPUTS (PSO-PS1); SYNC; BLANK Figure 3. LOADIN vs. Pixel Input Data non AU LL jq tro tenor | Lf LA LS LS LS bono f LJ WLI LL PIXEL INPUT Wf Ay By ues Bu fustnsy DATA* f\_nOn CusaDnat fy,20 | ANALOG IOR, ioR OUTPUT 0G, ioG Anat A Bnet A Cnet A Ont Cup DATA !OB, ioB_ sik lpL, SYNCOUT < tep _ | *INCLUDES PIXEL DATA (P0-P7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK Figure 4. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (4:1 Multiplex Mode) a VA LOADOUT \ \ _ LOADIN PIXEL INPUT DATA* Kosowh XY XY YY YY IOR, OR mnice | (eriee lela el) OUTPUT 1OB. i0B DATA lp__ SYNCOUT + t,, ___| *INCLUDES PIXEL DATA (PO0-P7); PALETTE SELECT INPUTS (PSO-PS1); SYNC; BLANK Figure 5. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (4:1 Multiplex Mode) REV.A 5-ADV7151 oe PLP PAP APP LOADOUT LOADIN 4 PIXEL INPUT DATA* 4 ANALOG 1OR, 108 10G, lOG OUTPUT IO, iOB _{ Ay I By } An I By Y AN { Bust ( Asa { By.2 DATA SYNCOUT Ip_L, SYNCOUT at. at teo > *INCLUDES PIXEL DATA (P0-P7); PALETTE SELECT INPUTS (PSO-PS1); SYNC; BLANK Figure 6. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (2:1 Multiplex Mode) 2% PDI NAP PPP APPR PPP LOADOUT LOADIN re. eu inom XY YY Yk | IOR, IOR [ If lJ | ANALOG IDG OUTPUT ion ioe Ana \ But Ay { By ( Aue ( Bust \ hu I Bus2 } DATA lpi SYNCOUT wr vy top *INCLUDES PIXEL DATA (P0-P7); PALETTE SELECT INPUTS (PSO-PS1); SYNC; BLANK Figure 7. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (2:1 Multiplex Mode) 6- REV.AADV7151 ee FSA ILI LIL TA PRGCKOUT (CLOCK/8) PRGCKOUT (CLOCK/16) PRGCKOUT (CLOCK/32) > tt ts ee >| BLANKING PERIOD S 6__ scan | \ | xa rk 4 mon | {VI . {\ END OF SCAN START OF LINE (N) SCAN LINE {N+1) Figure 9. Video Data Shift Clock Input (SCKIN) and BLANK vs. Video Data Shift Clock Output (SCKOUT) CLOCK t.>| t,, __> /\ Ln cc WHITE LEVEL YS 43- 90 % IOR, OR ANALOG i0G, iG OUTPUTS 10B, OB FULL-SCALE Ipit SYNCOUT 50% TRANSITION 10% (6 ?? t BLACK LEVEL >| "7 note: THIS DIAGRAM IS NOT TO SCALE. FOR THE PURPOSES OF CLARITY, THE ANALOG OUTPUT WAVEFORM IS MAGNIFIED IN TIME AND AMPLITUDE W.R.T. THE CLOCK WAVEFORM. lp, AND SYNCOUT ARE DIGITAL VIDEO OUTPUT SIGNALS. t,, IS THE ONLY RELEVANT OUTPUT TIMING SPECIFICATION FOR Ip,, AND SYNCOUT. Figure 10. Analog Output Response vs. CLOCK REV.A ayADV7151 tre p+ tiny = VALID RW, CO, C1 CONTROL DATA 7" tay > CE h t, + t,, ___| }< t,, | ht bes Do-D9 (READ MODE) \ RW =1 ) DOo-D9 (WRITE MODE) RW = 0 tog > to Figure 11. Microprocessor Port (MPU) Interface Timing RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Units Power Supply Vaa 4.75 5.00 5.25 Volts Ambient Operating Temperature Ta 0 +70 C Reference Voltage Veer 1.14 1.235 1.26 Volts Output Load R, 37.5 Q CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; WARNING! es however, permanent damage may occur on unconnected devices subject to high energy electro- static fields. Unused devices must be stored in conductive foam or shunts. The protective foam idle ae should be discharged to the destination socket before devices are inserted. ES a Eels es ABSOLUTE MAXIMUM RATINGS* VaastoGND ....... 000.000 00 ee 7V Voltage on Any Digital Pin ... GND 0.5 V to Vag + 0.5 V Ambient Operating Temperature (T,) ..... 55C to +125C Storage Temperature (Ts) ............. 65C to + 150C Junction Temperature (T))...............00.. + 150C Lead Temperature (Soldering, 10 secs) ........... + 260C Vapor Phase Soldering (1 minute) .............. +220C Analog Outputs toGND ........... GND 0.5 to Vaa NOTES *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration. ORDERING GUIDE? : 3 Speed 220 MHz 170 MHz 135 MHz 110 MHz 85 MHz ADV7151LS8220 ADV7151LS170 ADV7151LS135 ADV7151LS110 ADV7151LS85 NOTES ADV7151 is packaged in a 100-pin plastic quad flatpack, QFP. ?All devices are specified for 0C to +70C operation. *Contact sales office for latest information on package design. 38- REV.AADV7151 ADV7151 PIN ASSIGNMENTS Pin Pin Pin No. | Mnemonic No. | Mnemonic No. | Mnemonic 1 Vaa 41 | SYNCOUT [| 81 Vaa 2 SYNC 42 GND 82 D6 3 BLANK 43 NC 83 D7 4 | NC 44 | GND 84 | D8 5 NC 45 GND 85 D9 6 | NC 46 | NC 86 | GND 7 | Po, 47 | NC 87 | GND 8 | PO, 48 | PSO, 88 | IOB 9 | PO, 49 PSO, 89 | IOR 10 | PO, 50 | PSO. 90 | IOG ll Pla 51 PSO, 91 IOB 12 | Pl, 52 PSla 92 I0G 13. | Ple 53 PSlz 93 | Vag 14 | Pl, 54 | PSI. 94 | Vag 15 NC 55 PS15 95 IOR 16 | P2, 56 | PS, 96 | COMP 17 | P2, 57 | PS, 97 | Ver 18 P2, 58 PS. 98 Rser 19 | P2, 59 | PS, 99 | Ips. 20 | NC 60 | P6, 100 | GND 21 NC 61 P6, 22 P34 62 | Poe 23 P3, 63. | P6, 24 | P3, 64 | NC 25 P3,, 65 P7, 26 | NC 66 | P7, 27 =| NC 67 | P76 28 P4, 68 | P7, 29 | P4, 69 | NC 30 | P4. 70 | CE 31 P4, 71 RW 32 CLOCK 72 CO 33. | CLOCK 73 | Cl 34. | LOADIN 74 | DO 35 LOADOUT | 75 D1 36 | Vag 76 b2 37, | Vaa 77. | GND 38. | PRGCKOUT J 78 D3 39 SCKIN 79 D4 40 SCKOUT 80 D5 NC = NO CONNECT. REV.A 100-Lead QFP Configuration ROWA PIN NO. 1 IDENTIFIER ADV7151 PQFP TOP VIEW (Not to Scale) Te a =a o OoADV7151 PIN FUNCTION DESCRIPTION Mnemonic Function PO... . POy-P7,... P7p PSO, ... PS0y; PSI, .. . PSlp LOADIN LOADOUT PRGCKOUT SCKIN SCKOUT CLOCK, CLOCK BLANK SYNC SYNCOUT DO0-D9 Pixel Port (TTL Compatible Inputs). There are 32 pixel select inputs on the ADV7151. Each bit is multiplexed [AD] 4:1, 2:1 or 1:1. Pixel Data is latched into the device on a rising LOADIN signal rising edge. Palette Priority Selects (TTL Compatible Inputs). These pixel port select inputs determine whether or not the devices pixel data port is selected on a pixel by pixel basis. The palette selects allow switching between multiple palette devices. The device can be preprogrammed to completely shut off the DAC analog outputs. If the values of PSO and PS1 match the values programmed into bits MR16 and MR17 of the Mode Register, then the device is selected. Each bit is multiplexed [A-D] 4:1, 2:1 or 1:1. PSO and PS1 are latched into the device on a rising LOADIN signal rising edge. Pixel Data Load Input (TTL Compatible Input). This input latches the serialized pixel data, including PSO-PS1, BLANK and SYNC into the device. Pixel Data Load Output (TTL Compatible Output). This output control signal runs at a divided down frequency of the pixel CLOCK input. Its frequency is a function of the multiplex rate. It can be used to directly or indirectly drive LOADIN froapout = ferock/M where (M = 1 for 1:1 Multiplex Mode) (M = 2 for 2:1 Multiplex Mode) (M = 4 for 4:1 Multiplex Mode). Programmable Clock Output (TTL Compatible Output). This output control signal runs at a divided down frequency of the pixel CLOCK input. Its frequency is user programmable and is determined by bits CR30 and CR31 of Command Register 3 feRGCKOUT = forocr/N where N = 4, 8, 16 and 32. Video Shift Clock Input (TTL Compatible Input). The signal on this input is internally gated synchronously with the BLANK signal. The resultant output, SCKOUT, is a video clocking signal that is stopped during video blanking periods. Video Shift Clock Output (TTL Compatible Output). This output is a synchronously gated version of SCKIN and BLANK. SCKOUT, is a video clocking signal that is stopped during video blanking periods. Clock Inputs (ECL Compatible Inputs). These differential clock inputs are designed to be driven by ECL logic levels configured for single supply (+5 V) operation. The clock rate is normally the pixel clock rate of the system. Composite Blank (TTL Compatible Input). This video control signal drives the analog outputs to the blanking level. Composite-Sync Input (TTL Compatible Input). This video control signal drives the IOG analog output to the SYNC level. It is only asserted during the blanking period. CR22 in Command Register 2 must be set if SYNC is to be decoded onto the analog output, otherwise the SYNC input is ignored. Composite SYNC O/P (TTL Compatible Output). This video output is a delayed version of SYNC. The delay corresponds to the number of pipeline stages of the device. Databus (TTL Compatible Input/Output Bus). Data, including color palette values and device control information is written to and read from the device over this 10-bit, bidirectional databus. 10-bit data or 8-bit data can be used. The databus can be configured for either 10-bit parallel data or byte data (8+2) as well as standard 8-bit data. Any unused bits of the databus should be terminated through a resistor to either the digital power plane (V.,) or GND. Chip Enable (TTL Compatible Input). This input must be at Logic 0 when writing to or reading from the device over the databus (D0D9). Internally, data is latched on the rising edge of CE. Read/Write Control (TTL Compatible Input). This input determines whether data is written to or read from the devices registers and color palette RAM. R/W and CE must be at Logic 0 to write data to the part. R/W must be at Logic 1 and CE at Logic 0 to read from the device. 10 REV.AADV7151 Mnemonic Function co, Cl IOR; IOR, IOG; IOG, IOB; IOB VREF Rser COMP Tpit Vaa GND Command Controls (TTL Compatible Inputs). These inputs determine the type of read or write operation being performed on the device over the databus (see Interface Truth Table). Data on these inputs is latched on the falling edge of CE. Red, Green and Blue Current Outputs (High Impedance Current Sources). These RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into doubly terminated 75 loads. IOR, IOG and IOB are the complementary outputs of IOR, IOG and IOB. These outputs can be tied to GND if it is not required to use differential outputs. Voltage Reference Input (Analog Input). An external 1.235 V voltage reference is required to drive this input. An AD589 (2-terminal voltage reference) or equivalent is recommended. (Note: It is not recommended to use a resistor network to generate the voltage reference.) Output Full-Scale Adjust Control (Analog Input). A resistor connected between this pin and analog ground controls the absolute amplitude of the output video signal. The value of Rg; is derived from the full-scale output current on IOG according to the following equations: Repr (Q) = Cl X Reg AIOG (mA); SYNC on GREEN Rey (Q) = C2 X Rpg AllOG (mA); No SYNC on GREEN. Full-Scale output currents on IOR and IOB for a particular value of Rg; are given by: IOR (mA)= C2 x Regp (VRspr Q) and IOB (mA) = C2 X Reger (VRser (Q) where Cl] = 6,050: PEDESTAL = 7.5 IRE = 5,723: PEDESTAL = 0 IRE and C2 = 4,323: PEDESTAL = 7.5 IRE 3,996: PEDESTAL = 0 IRE. Compensation Pin. A 0.1 JF capacitor should be connected between this pin and Vag. ll Phase Lock Loop Output Current (High Impedance Current Source). This output is used to enable multiple ADV7151s along with ADV7150/ADV7152s to be synchronized together with subpixel resolution when using an external PLL. This output is triggered either from the falling edge of SYNC or BLANK as determined by bit CR21 of Command Register 2. When activated, it supplies a current corresponding to Tppt (MA) = 1,728 X Rpe(V/Rser (2). When not using the I,,, function, this output pin should be tied to GND. Power Supply (+5 V + 5%). The part contains multiple power supply pins, all should be connected together to one common +5 V filtered analog power supply. Analog Ground. The part contains multiple ground pins, all should be connected together to the systems ground plane. REV.A -11-ADV7151 (Continued from page 1) Indexed-Color image rendition, at speeds of up to 220 MHz, is achieved through the use of the on-board data multiplexer/ serializer. The pixel input ports flexibility allows for direct interface to most standard frame buffer memory configurations. The 30 bits of resolution, associated with the color look-up table and triple 10-bit DAC, realizes 8-bit Indexed-Color resolution, while also allowing for the on-board implementation of lineariza- tion algorithms, such as Gamma-Correction. This allows effec- tive 10-bit Indexed-Color operation. The on-chip video clock controller circuit generates all the inter- nal clocking and some additional external clocking signals. An external ECL oscillator source with differential outputs is all that is required to drive the CLOCK and CLOCK inputs of the ADV7151. The part can also be driven by an external clock gen- erator chip circuit, such as the AD730. The ADV7151 is capable of generating RGB video output sig- nals which are compatible with RS-343A and RS-170 video stan- dards, without requiring external buffering. Test diagnostic circuitry has been included to complement the users system level debugging. The ADV7151 is fabricated in a +5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with low power dissipation. The ADV7151 is packaged in a plastic 100-pin quad flatpack (QFP). Superior thermal dissipation is achieved by inclusion of a copper heatslug, within the standard package outline to which the die is attached. CIRCUIT DETAILS AND OPERATION OVERVIEW Digital video or pixel data is latched into the ADV7151 over the devices Pixel Port. This data acts as a pointer to the on-board Color Palette RAM. The data at the RAM address pointed to is latched into the digital-to-analog converters (DACs) and output as an RGB analog video signal. For the purposes of clarity of description, the ADV7151 is bro- ken down into three separate functional blocks. These are: 1. Pixel port and clock control circuit 2. MPU port, registers and color palette 3. Digital-to-analog converters and video outputs Table I. Architectural and Packaging Differences of the ADV715x Series Description ADV7150*/ADV7151/ADV7152* 24-Bit Gamma True Color 24-Bit Standard True Color 8-Bit Gamma Pseudo Color 8-Bit Standard Pseudo Color 15-Bit True Color 220 MHzTrue Color 220 MHzPseudo Color Triple 10-Bit DACs 4:1 Multiplexing 2:1 Multiplexing 1:1 Multiplexing 160-Lead QFP 100-Lead QFP e e *See the relevant data sheet for more information on these parts. Table I shows the architectural and packaging differences between the ADV7151 and the associated ADV7150/ADV7152. (For more details on the ADV7150 or the ADV7152, please con- sult the relevant data sheet). Pixel Port and Clock Control Circuit The Pixel Port of the ADV7151 is directly interfaced to the video/graphics pipeline of a computer graphics subsystem. It is connected directly or through a gate array to the video RAM of the systems Frame-Buffer (video memory). The pixel port on the device consists of: -12- POA-P7A . . . POD-P7D SYNC, BLANK PSO-PS1 The associated clocking signals for the pixel port include: CLOCK, CLOCK, LOADIN, SCKIN LOADOUT, PRGCKOUT, SCKOUT These on-board clock control signals are included to simplify interfacing between the part and the frame buffer. Only two control input signals are necessary to get the part operational, CLOCK and CLOCK (ECL Levels). No additional signals or external glue logic are required to get the Pixel Port and Clock Control Circuit of the part operational. Pixel Port (Color Data) The ADV7151 has 32 pixel data inputs. These are organized as four (for 4:1 multiplexing) 8-bit wide indexed color data inputs. The part supports 8-bit Pseudo Color in 4:1, 2:1 and 1:1 multi- plex modes. Color Data Pixel Controls Palette Selects Clock Inputs Clock Outputs ADV7151 MULTIPLEXER Figure 12. Multiplexed Color Inputs for the ADV7151 Color data is latched into the parts pixel port on every rising edge of LOADIN (see Timing Waveform Figure 3). The required frequency of LOADIN is determined by the multiplex rate, where floapin = fe.ock/4 4:1 Multiplex Mode floapin = fcrocKk/2 2:1 Multiplex Mode floapin = fetocKk 1:1 Multiplex Mode Other pixel data signals latched into the device by LOADIN include SYNC, BLANK and PSO-PS1. Internally, data is pipelined through the part by the differential pixel clock inputs, CLOCK and CLOCK. The LOADIN con- trol signal does not need to have a relationship to the pixel CLOCK (see Pipeline Delay section). A completely asynchro- nous LOADIN signal can be used with the ADV7151. REV.AADV7151 Alternatively, the LOADOUT signal of the ADV7151 can be used. LOADOUT can be connected either directly or indirectly to LOADIN. Its frequency is automatically set to the correct LOADIN requirement. SYNC, BLANK The BLANK and composite SYNC video control signals drive the analog outputs to the blanking and sync levels respectively. These signals are latched into the part on the rising edge of LOADIN. The SYNC information is encoded onto the IOG analog signal when Bit CR22 of Command Register 2 is set to a Logic 1. The SYNC input is ignored if CR22 is set to 0. SYNCOUT In some applications where it is not permissible to encode SYNC on green (IOG), SYNCOUT can be used as a separate TTL digital SYNC output. This has the advantage over an inde- pendent (of the ADV7151) SYNC in that it does not necessitate knowing the absolute pipeline delay of the part. This allows complete independence between LOADIN/Pixel Data and CLOCK. The SYNC input is connected to the device as normal with Bit CR22 of Command Register 2 set to 0 thereby pre- venting SYNC from being encoded onto IOG. Bit CR12 of Command Register 1 is set to 1, enabling SYNCOUT. The output signal generates a TTL SYNCOUT with correct pipeline delay which is capable of directly driving the composite SYNC signal of a computer monitor. PS0-PS1 (Palette Priority Select Inputs) These pixel port select inputs determine whether or not the device is selected. This is determined on a pixel by pixel basis as the PSO-PS1 inputs are multiplexed in exactly the same format as the pixel port data. These controls allow for switching between multiple devices (see Appendix 4). If values of PSO and PS1 dont match the values programmed into bits MR16 and MR17 of the mode register, then the outputs of the device are forced to 0 mA regardless of the state of the pixel and control data inputs. Otherwise the device is selected and acts as normal. Multiplexing The on-board multiplexers of the ADV7151 eliminate the need for external data serializer circuits. Multiple video memory devices can be connected, in parallel, directly to the device. Fig- ure 13 shows four memory banks of 33 MHz memory connected to the ADV7151, running in 4:1 multiplex mode, giving a resultant pixel or dot clock rate of 132 MHz. As mentioned in the previous section, the ADV7151 supports a number of color data formats in 4:1, 2:1 and 1:1 multiplex modes. VIDEO MEMORY/ FRAME BUFFER ADV7151 VRAM (BANK A) VRAM (BANK B) VRAM (BANK C) VRAM (BANK D) | | | | I \ 132 MHz (4x 33 MHz) Figure 13. Direct Interfacing of Video Memory to ADV7151 In 1:1 multiplex mode, the ADV7151 is clocked using the LOADIN signal. This means that there is no requirement for differential ECL inputs on CLOCK and CLOCK. The pixel REV.A clock is connected directly to LOADIN. (Note the ECL CLOCK can still be used to generate LOADOUT, PRGCKOUT, etc.) CLOCK CONTROL CIRCUIT The ADV7151 has an integrated Clock Control Circuit (Figure 14). This circuit is capable of both generating the ADV7151s internal clocking signals as well as external graphics subsystem clocking signals. Total system synchronization can be attained by using the parts output clocking signals to drive the control- ling graphics processors master clock as well as the video frame buffers shift clock signals. CLOCK, CLOCK Inputs The Clock Control Circuit is driven by the pixel clock inputs, CLOCK and CLOCK. These inputs can be driven by a differ- ential ECL oscillator running from a +5 V supply. Alternatively, the ADV7151 CLOCK inputs can be driven by a Programmable Clock Generator (Figure 15), such as the IC$1562. The ICS$1562 is a monolithic, phase-locked-loop, clock generator chip capable of synthesizing differential ECL output frequencies of up to 220 MHz from a single low frequency refer- ence crystal. cLOck -_______@____}> CLOCK a y t y Y PRGCKOUT DIVIDE BY DIVIDE BY N(N) M (=. M) LOADOUT SCKOUT LATCH ENABLE A SCKIN LOADIN TO COLOR DATA MULTIPLEXER ADV7151 MIS A FUNCTION OF MULTIPLEX RATE M = 4 IN 4:1 MULTIPLEX MODE M = 2 IN 2:1 MULTIPLEX MODE M =11N 1:1 MULTIPLEX MODE N IS INDEPENDENTLY PROGRAMMABLE N= (4, 8, 16, 32) Figure 14. Clock Control Circuit of the ADV7151 LOW FREQUENCY OSCILLATOR Vaa Vetock I Voc Vec O +5V 2202 22002 3 tiene 2 CLOCK our ? CLOCK -, ~ Vv CLOCK 33002 33002 AA GENERATOR = Z L ADV7151 Vout GND GND 0.4 uF REF ) Vacr DO-D3. CS R/W GND Cy L GND Figure 15. PLL Clock Generator Driving the ECL Clock Inputs of the ADV7151 13-ADV7151 CLOCK CONTROL SIGNALS LOADOUT The ADV7151 generates a LOADOUT control signal which runs at a divided down frequency of the pixel CLOCK. The frequency is automatically set to the programmed multiplex rate, controlled by CR37 and CR36 of Command Register 3. froapout = ferock/4 4:1 Multiplex Mode floapout = ferock/2 2:1 Multiplex Mode froapoutr = ferock 1:1 Multiplex Mode The LOADOUT signal is used to directly drive the LOADIN pixel latch signal of the ADV7151. This is most simply achieved by tying the LOADOUT and LOADIN pins together. Alterna- tively, the LOADOUT signal can be used to drive the frame buffers shift clock signals, returning to the LOADIN input delayed with respect to LOADOUT. LOADOUT VIDEO ADV7151 VIDEO ADV7151 FRAME FRAME |LOADOUT(2) BUFFER LOADIN BUFFER }/+?9 LOADIN PIXEL PIXEL 7 DATA 1 DATA | I LOADOUT f LOADOUT(1) y I | DELAY I | foo | as I | LOADIN LOADOUT(2) f | Figure 16. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK) If it is not necessary to have a known fixed number of pipeline delays, then there is no limitation on the delay between LOAD- OUT and LOADIN (LOADOUT(1) and LOADOUT(2)). LOADIN and Pixel Data must conform to the setup and hold times t, and tg). If however, it is required that the ADV7151 has a fixed number of pipeline delays (tp), LOADOUT and LOADIN must con- form to timing specifications t,9 and 7-t,, as illustrated in Fig- ures 4 to 7. PRGCKOUT The PRGCKOUT control signal outputs a user programmable clock frequency. It is a divided down frequency of the pixel CLOCK (see Figure 8). The rising edge of PRGCKOUT is syn- chronous with the rising edge of LOADOUT. fprocxout = ferocK!/N where N = 4, 8, 16 or 32 One application of the PRGCKOUT is to use it as the master clock frequency of the graphics subsystems processor or controller. SCKIN, SCKOUT These video memory signals are used to minimize external sup- port chips. Figure 17 illustrates the function that is provided. An input signal applied to SCKIN is AND-ed with the video blanking signal (BLANK). The resulting signal is output on SCKOUT. Figure 9 of the Timing Waveform section shows the relationship between SCKOUT, SCKIN and BLANK. 14- SCKOUT BLANK ENABLE A , SYNC SCKIN Figure 17. SCKOUT Generation Circuit The SCKOUT signal is essentially the video memory shift con- trol signal. It is stopped during the screen retrace. Figure 18 shows a suggested frame buffer to ADV7151 interface. This is a minimum chip solution and allows the ADV7151 control the overall graphics system clocking and synchronization. LOADOUT LOADIN SCKIN ADV7151 VIDEO FRAME BUFFER __ BLANK SCKOUT PIXEL C | DATA Figure 18. ADV7151 Interface Using SCKIN and SCKOUT otal Pipeline Delay and On-Board Calibration The ADV7151 has a fixed number of pipeline delays (tpp), so long as timings ty and t-t,, are met. However, if a fixed pipe- line delay is not a requirement, timings t,) and 7-t,, can be ignored, a calibration cycle must be run and there is no restric- tion on LOADIN to LOADOUT timing. If timings t,, and 7-t,, are met the part will function correctly though with an increased number of pipeline delays: tp, + N CLOCKS (for 4:1 Mode N = 4, for 2:1 Mode N = 2, for 1:1 Mode N = 0). The ADV7151 has on-board calibration circuitry which synchro- nizes pixel data and LOADIN with the internal ADV7151 clocking signals. Calibration is performed in two ways. During the devices initialization sequence by toggling two bits of the Mode Register, MR10 followed by MR15 or by writing a 1 to Bit CR10 of Command Register 1 which executes a calibration on every vertical sync. COLOR VIDEO MODES The ADV7151 supports two color video modes all at the maxi- mum video rate. Command bits CR24-CR27 of Command Register 2 along with bit MR11 of Mode Register 1 determine the color mode. 8-Bit Gamma Pseudo Color (CR24, CR25, CR26, CR27 = X, X, 0, 0 and MR11 = 1) This mode sets the part into 8-bit Pseudo-Color operation. The pixel port accepts 8-bits of pixel data which indexes a 30-bit word in the Look-Up Table RAM. The Look-Up Table is con- figured as a 256 location by 30 bits deep RAM (10 bits each for Red, Green and Blue). The output of the RAM drives the DACs with 30-bit data (10 bits each for Red, Green and Blue). REV.AADV7151 30-BiT ANALOG VIDEO COLOR DATA OUTPUTS. _<_~ 8-BIT TO 30-BIT 8-BIT PIXEL DATA LOOK-UP TABLE ___- 8, RED 10, | 10-BIT RED 256 x 10 "1 RED DAC OUT L__| GREEN 10, . 10-BIT GREEN WP) 256 x 10 7#"|GREEN DAC OUT Ly BLUE 10, | 10-BIT BLUE je | 256 x 10 7#| BLUE DAC OUT Figure 19. 8-Bit to 30-Bit Pseudo-Color Configuration This mode allows for the display of 256 simultaneous colors out of a total palette of millions of addressable colors 8-Bit Standard Pseudo Color (CR24, CR25, CR26, CR27 = X,X,0,0 and MR11 = 0) This mode sets the part into 8-bit Pseudo-Color operation. The pixel port accepts 8-bits of pixel data which indexes a 24-bit word in the Look-Up Table RAM. The Look-Up Table is con- figured as a 256 location by 24 bits deep RAM (10 bits each for Red, Green and Blue). The output of the RAM drives the DACs with 24-bit data (8 bits each for Red, Green and Blue). 8-BIT PIXEL DATA B-BIT TO 24-BIT on a ourbUTs a LOOK-UP TABLE COLOR DATA OUTPUTS __ 8, [ RED 8, |) 8 BIT RED 256 x 8 "1 RED DAC OUT GREEN 8, 8-BIT GREEN 256 x 8 + GREEN DAC ouT BLUE 8, . | 8BIT BLUE pe) 256x8 7#"| BLUE DAC OUT Uti Figure 20. 8-Bit to 24-Bit Pseudo-Color Configuration This mode allows for the display of 256 simultaneous colors out of a total palette of millions of addressable colors. MICROPROCESSOR (MPU) PORT The ADV7151 supports a standard MPU Interface. All the functions of the part are controlled via this MPU port. Direct access is gained to the Address Register, Mode Register and all the Control Registers as well as the Color Palette. The following sections describe the setup for reading and writing to all of the devices registers. MPU Interface The MPU interface (Figure 21) consists of a bidirectional, 10-bit wide databus and interface control signals CE, C0, C1 and R/W. The 10-bit wide databus is user configurable as illustrated. Table II. Databus Width Register Mapping The ADV7151 contains a number of on-board registers includ- ing the Mode Register (MR1I7-MR10), Address Register (A7- AO) and nine Control Registers as well as Red (R9-RO), Green (G9-G0) and Blue (B9-B0) Color Registers. These registers con- trol the entire operation of the part. Figure 22 shows the inter- nal register configuration. Control lines Cl and CO determine which register the MPU is accessing. Cl and CO also determine whether the Address Regis- ter is pointing to the color registers and look-up table RAM or the control registers. If C1, CO = 1, 0, the MPU has access to whatever control register is pointed to by the Address Register (A7-A0). If C1, CO = 0, 1, the MPU has access to the Look-Up Table RAM (Color Palette) through the associated color regis- ters. The CE input latches data to or from the part. Databus RAM/DAC Read/Write az . . . Width Resolution Mode The R/W control input determines between read or write accesses. The Truth Tables III and IV show all modes of access to the 10-Bit 10-Bit 10-Bit Parallel various registers and color palette for both the 8-bit wide data- 10-Bit 8-Bit 8-Bit Parallel bus configuration and 10-bit wide databus configuration. It 8-Bit 10-Bit 8+2 Byte should be noted that after power-up, the devices MPU port is 8-Bit 8-Bit 8-Bit Parallel automatically set to 10-bit wide operation (see Power-On Reset section). CONTROL REGISTERS PIXEL MASK REGISTER COMMAND aaa TO ven] Hreasren? ADDRESS REGISTERS 30. COLOR REGISTERS REGISTER MODE SODA) REGISTER iD REVISION REGISTER RED GREEN BLUE (A7-A0) | (MR1) REGISTER REGISTER | | REGISTER | | REGISTER MPU PORT TH CE rR/w co C1 f 0 (8+2) D9-Do Figure 21. MPU Port and Register Configuration REV.A 15-ADV7151 Color Palette Accesses Data is written to the color palette by first writing to the address register, the address of the color palette location to be modified. The MPU performs three successive write cycles for each of the red, green and blue registers (10-bit or 8-bit). An internal pointer moves from red to green to blue after each write is completed. This pointer is reset to red after a blue write or whenever the address register is written. During the blue write cycle, the three bytes of red green and blue are concatenated into a single 30-bit/24-bit word and written to the RAM location as specified in the address register (A7-A0). The address regis- ter then automatically increments to point to the next RAM location and a similar red, green and blue palette write sequence is performed. The address register resets to 00H following a blue write cycle to color palette RAM location FFH. Data is read from the color palette by first writing to the address register the address of the color palette location to be read. The MPU performs three successive read cycles from each of the red, green and blue locations (10-bit or 8-bit) of the RAM. An internal pointer moves from red to green to blue after each read is completed. This pointer is reset to red after a blue read or whenever the address register is written. The address register then automatically increments to point to the next RAM location and a similar red, green and blue palette read sequence is performed. The address register resets to 00H following a blue read cycle of color palette RAM location FFH. Register Accesses The MPU can write to or read from all of the ADV7151s regis- ters. CO and Cl determine whether the Mode Register or Address Register is being accessed. Access to these registers is direct. The Control Registers are accessed indirectly. The Address Register must point to the desired Control Register. MODE REGISTER (MR17-MR10) C1=1 co=1 c1=1 ADDRESS REGISTER c1=0 . (A7-A0) co =0 co=0 C1= ADDRESS CONTROL Y co=1 REGISTER REGISTERS (A7-A0) Y Y Y 00H PIXEL TEST REGISTER fot RED GREEN BLUE rR_|[| c [| 6 REGISTER REGISTER REGISTER O1H DAC TEST REGISTER (R9-RO) (G9-Go) (B9-Bo) 02H SYNC, BLANK & Ip), TEST REGISTER 03H _| ID REGISTER (READ ONLY) 04H PIXEL MASK REGISTER 05H COMMAND REGISTER 1 06H COMMAND REGISTER 2 07H COMMAND REGISTER 3 08H RESERVED* (READ ONLY) 09H RESERVED* (READ ONLY) OAH RESERVED* (READ ONLY) OBH REVISION REGISTER AAAT * THIS REGISTER IS READ ONLY. A READ CYCLE WILL RETURN ZEROS "00." | LOOK-UP TABLE RAM a (256 x 30) ADDRESS REG = ADDRESS REG + 1 POINTS TO LOCATION CORRESPONDING TO ADDRESS REG (A7-A0) Figure 22. Internal Register Configuration and Address Decoding Table III. Truth Table (10-Bit Databus Mode) R/W Cl Co Databus (D9-D0) Operation Result 0 1 1 DB7-DB0 Write to Mode Register DB7-DB0 MR17-MR10 0 0 DB7-DB0 Write to Address Register DB7-DB0 A7-A0 0 1 0 DB7-DB0 Write to Control Registers DB7-DBO0 Control Registers (Particular Control Register Determined by Address Register) 0 0 1 DB9-DBO Write to RED Register DB9-DB0 R9-RO 0 0 1 DB9-DBO Write to GREEN Register DB9-DBO G9-G0 0 0 1 DB9-DBO Write to BLUE Register DB9-DBO B9-BO Write RGB Data to RAM Location Pointed to by Address Register (A7-A0) Address Register = Address Register + 1 1 1 1 DB7-DBO Read Mode Register MR17-MR10 DB7-DBO 1 0 0 DB7-DBO Read Address Register A7-A0 DB7-DBO 1 1 0 DB7-DBO Read Control Registers Register Data DB7-DBO (Particular Control Register Determined by Address Register) 1 0 1 DB9-DBO Read RED RAM Location R9-RO DB9-DBO 1 0 1 DB9-DB0 Read GREEN RAM Location G9-G0 DB9-DBO 1 0 1 DB9-DBO Read BLUE RAM Location B9-B0 DB9-DBO (RAM Location Pointed to by Address Register (A7-AO) Address Register = Address Register + 1 | DB = Data Bit. ~16 REV.AADV7151 Table IV. Truth Table (8-Bit Databus Mode)* Databus R/W Cl co (D7-D0) Operation Result 0 1 1 DB7-DBO Write to Mode Register DB7-DB0 MR17-MR10 0 0 DB7-DB0 Write to Address Register DB7-DB0 A7-A0 0 1 0 DB7-DBO Write to Control Registers DB7-DBO Control Registers (Particular Control Register Determined by Address Register (A7AO)) 0 0 1 DB9-DB2 Write to RED Register DB9-DB2 R9-R2 0 0 1 DB1-DBO Write to RED Register DB1-DB0 R1-RO 0 0 1 DB9-DB2 Write to GREEN Register DB9-DB2 G9-G2 0 0 1 DB1-DBO Write to GREEN Register DB1-DB0 G1-G0 0 0 1 DB9-DB2 Write to BLUE Register DB9-DB2 B9-B2 0 0 1 DB1-DBO0 Write to BLUE Register DB1-DBO0 B1-B0 Write RGB Data to RAM Location Pointed to by Address Register (A7A0) Address Register = Address Register + 1 1 1 1 DB7-DBO Read Mode Register MR17-MR10 DB7-DBO 1 0 0 DB7-DB0 Read Address Register A7-A0 DB7-DBO0 1 1 0 DB7-DBO Read Control Registers Register Data DB7-DBO (Particular Control Register Determined by Address Register) 1 0 1 DB9-DB2 Read RED RAM Location R9-R2 DB9-DB2 1 0 1 DB1-DBO Read RED RAM Location R1-RO DBI-DBO 1 0 1 DB9-DB2 Read GREEN RAM Location G9-G2 DB9-DB2 1 0 1 DB1-DBO Read GREEN RAM Location G1-G0 DB1-DBO 1 0 1 DB9-DB2 Read BLUE RAM Location B9-B2 DB9-DB2 1 0 1 DB1-DBO Read BLUE RAM Location B1-B0 DB1-DB0 (RAM Location Pointed to by Address Register (A7-AO)) Address Register = Address Register + 1 DB = Data Bit. *Writing or reading 10-bit data (DB9-DBO0) over an 8-bit databus (D7~D0) requires two write or two read cycles. DB9-DB2 is mapped to D7-D0 on the first cycle. DB1-DBO is mapped to D1-D0 on the second cycle with D7-D2 ignored. Power-On Reset On power-up, the ADV7151 executes a power-on reset sequence. This initializes the pixel port such that the pixel sequence ABCD starts at A. The Mode Register (MR17MR10), Command Register 2 (CR27-CR20) and Command Register 3 (CR37CR30) have all bits set to a Logic 1. The output clocking signals are also set during this reset period. PRGCKOUT = CLOCK/32 LOADOUT = CLOCK/4 The power-on reset is activated when V,, goes from 0 V to 5 V. This reset is active for 1 ys. The ADV7151 should not be accessed during this reset period. The pixel clock should be applied at power-up. REGISTER PROGRAMMING The following section describes each register, including Address Register, Mode Register and each of the nine Control Registers in terms of its configuration. REV.A Address Register (A7-A0) As illustrated in the previous tables, the CO and Cl control inputs, in conjunction with this address register specify which control register, or color palette location is accessed by the MPU port. The address register is 8 bits wide and can be read from as well as written to. When writing to or reading from the color palette on a sequential basis, only the start address needs to be written. After a red, green and blue write sequence, the address register is automatically incremented. MODE REGISTER MR1 (MR19-MR10) The mode register is a 10-bit wide register. However, for pro- gramming purposes, it may be considered as an 8-bit wide regis- ter (MR18 and MR19 are both reserved). It is denoted as MR17-MR1O0 for simplification purposes. -17ADV7151 nmap Cwr17 | mrie )|(mRis)|( mrt MR13 )( MRi2)|(MR11) |(MRio ) RESERVED* MPU DATABUS LOADIN R12 PALETTE SELECT ris | f] MATCH BITS CONTROL 0 8-BIT (D7-Do) 1 10-BIT (D9-Do) MR16 Pso MR17 PS1 RAM-DAC RESOLUTION CONTROL OPERATIONAL MODE CONTROL MR11 MR14 MR13 o 8-BIT 1 10-BIT 0 0 RESERVED 0 1 NORMAL OPERATION 1 0 RESERVED RESET CONTROL 1 1 RESERVED MR10 * THESE BITS ARE READ-ONLY RESERVED BITS. LT A READ CYCLE WILL RETURN ZEROS "00." Mode Register 1 (MR1) (MR19-MR10) The diagram shows the various operations under the control of the mode register. This register can be read from as well written to. In read mode, if MR18 and MR19 are read back, they are both returned as zeros. MODE REGISTER (MR17-MR10) BIT DESCRIPTION Reset Control (MR10) This bit is used to reset the pixel port sampling sequence. This ensures that the pixel sequence ABCD starts at A. It is reset by writing a 1 followed by a 0 followed by a 1. This bit must be run through this cycle during the initialization sequence. RAM-DAC Resolution Control (MR11) When this is programmed with a 1, the RAM is 30-bits deep (10 bits each for red, green and blue) and each of the three DACs is configured for 10-bit resolution. When MR11 is pro- grammed with a 0, the RAM is 24 bits deep (8 bits each for red, green and blue) and the DACs are configured for 8-bit res- olution. The two LSBs of the 10-bit DACs are pulled down to zero in 8-bit RAM-DAC mode. MPU Databus Width (MR12) This bit determines the width of the MPU port. It is configured as either a 10-bit wide (D9-D0) or 8-bit wide (D7D0) bus. 10-bit data can be written to the device when configured in 8-bit wide mode. The 8 MSBs are first written on D7D0, then the two LSBs are written over D1-D0. Bits D9-D8 are zeros in 8-bit mode. Operational Mode Control (MR14-MR13) When MR14 is 0 and MR13 if 11, the port operates in nor- mal mode. Calibrate LOADIN (MR15) This bit automatically calibrates the on-board LOADIN/ LOADOUT synchronization circuit. A 0 to 1 transition initiates calibration. This bit is set to 0 in normal operation. See Pipeline Delay and Calibration section. This bit must be run through this cycle during the initialization sequence. _~18 Palette Select Match Bits Control (MR17-MR16) These bits allow multiple palette devices to work together. When bits PS1 and PSO match MR17 and MR16 respectively, the device is selected. If these bits do not match, the device is not selected and the analog video outputs drive 0 mA. See Appendix 4, Multiple Palette Applications. CONTROL REGISTERS The ADV7151 has 9 control registers. To access each register, two write operations must be performed. The first write to the address register specifies which of the 9 registers is to be accessed. The second access determines the value written to that particular control register. Pixel Test Register (Address Reg (A7-A0) = 00H) This register is used when the device is in test/diagnostic mode. It is an 8-bit wide read-only register which allows the MPU to read data on the pixel port (see Appendix 6, Test Diagnostics). DAC Test Register (Address Reg (A7-A0) = 01H) This register is used when the device is in test/diagnostic mode. It is a 30-bit (10 bits each for RED, GREEN and BLUE) wide read-only register which allows MPU access to the DAC port (see Appendix 6, Test Diagnostics). SYNC, BLANK and Ip, Test Register (Address Reg (A7-A0) = 02H) This register is used when the device is in test/diagnostic mode. It is a 3-bit wide (3 LSBs) read/write register which allows MPU access to these particular pixel control bits (see Appendix 6, Test Diagnostics). ID Register (Address Reg (A7-A0) = 03H) This is an 8-bit wide Identification read-only register. For the ADV7151 it will always return the hexadecimal value 8FH. REV.AADV7151 Pixel Mask Register (Address Reg (A7A0) = 04H) The contents of the pixel mask register are individually bit-wise logically AND-ed with the Red, Green and Blue pixel input stream of data. It is an 8-bit read/write register with DO corre- sponding to RO, GO and BO. For normal operation, this register is set with FFH. COMMAND REGISTER 1 (CR1) (Address Reg (A7-A0) = 05H) This register contains a number of control bits as shown in the diagram. CR1 is a 10-bit wide register. However for program- ming purposes, it may be considered as an 8-bit wide register (CR18 and CR19 are reserved). The diagram below shows the various operations under the con- trol of CR1. This register can be read from as well as written to. In write mode, zero should be written to CR11 and CR13 to CR17. In read mode, CR11 and CR13 to CR19 are all returned as zeros. COMMAND REGISTER 1 BIT DESCRIPTION Calibration Control (CR10): This bit automatically calibrates the on-board LOADIN/ LOADOUT synchronization circuit. MR15 of Mode Register MRI must be set to 0. SYNCOUT Control (CR12): This bit specified whether the video SYNCOUT signal is to be enabled. On power up a 0 is written to the bit and SYNCOUT is set three state. i i CN Mca cue cue | CR12 | cA11 | cRio L oo | RESERVED* | CR17-CR13 CR11 (00000) (0) *THESE BITS ARE THESE BITS THIS BIT READ-ONLY SHOULD BE SHOULD BE RESERVED BITS. SET TO ZERO SET TO ZERO A READ CYCLE WILL RETURN ZEROS "00." SYNCOUT CONTROL CRI2 CALIBRATION 0 DISABLE CONTROL 1 ENABLE SYNCOUT cR10 0 DISABLE 1 CALIBRATES ON EVERY VERTICAL SYNC (MR15=0) Command Register 1 (CR1) (CR19-CR10) REV.A 19ADV7151 COMMAND REGISTER 2 (CR2) (Address Reg (A7-A0) = 06H) This register contains a number of control bits as shown in the diagram. CR2 is a 10-bit wide register. However for program- ming purposes, it may be considered as an 8-bit wide register (CR28 and CR29 are both reserved). The diagram shows the various operations under the control of CR2. This register can be read from as well written to. In read mode, CR28 and CR29 are both returned as zeros. COMMAND REGISTER 2 BIT DESCRIPTION P2 Trigger Polarity Control (CR20) This bit is used when the device is in test/diagnostic mode. It determines whether the pixel data is latched into the test regis- ters in the rising or falling edge of P2 (see Appendix 6, Test Diagnostics). Ip... Trigger Control (CR21) This bit specifies whether the I,,, output is triggered from BLANK or SYNC. SYNC Recognition Control (CR22) This bit specifies whether the video SYNC input is to be encoded onto the IOG analog output or ignored. Pedestal Enable Control (CR23) This bit specifies whether a 0 IRE or a 7.5 IRE blanking pedes- tal is to be generated on the video outputs. Color Mode Control (CR27-CR24) These 4 bits specify the color mode. To ensure compatibility with future products in the ADV715x product family, it is rec- ommended that all these bits be set to a logical zero. CR29 |CR28 (cr27 CR26 | CR25 cR24 ) CR23 )|\ CR22 )] (CR21 )|(CR20 RESERVED* PEDESTAL ENABLE SYNC RECOGNITION CONTROL CONTROL * THESE BITS ARE READ-ONLY CR23 CR22 RESERVED BITS. A READ CYCLE OIRE 0 IGNORE WILL RETURN 1 7.5 IRE 1 DECODE ZEROS "00." lp__L TRIGGER COLOR MODE CONTROL CONTROL CR21 CR27 CR26 CR25 CR24 | COLOR MODE 0 SYNC 0 0 0 0 8-BIT PSEUDO COLOR 1 BLANK P2 TRIGGER POLARITY CONTROL cR20 0 4 1 LL Command Register 2 (CR2) (CR29-CR20) 20- REV.AADV7151 GEE | (cra7 [crss )|(crss | casa | crass [crs2)|(crst | crso ) RESERVED* EXTRA BLANK PIPELINE DELAY CONTROL RESERVED BITS. _ A READ CYCLE WILL RETURN CR35 CR34 CR33 CR32 BLANK PIPELINE DELAY ZEROS "00." 0 0 0 0 tpp 0 Q 0 1 tpp + 1x LOADOUT 0 0 1 0 tpp + 2x LOADOUT 1 1 1 1 tpp+ 15 x LOADOUT PIXEL MULTIPLEX CONTROL PRGCKOUT caay Onae FREQUENCY CONTROL CR31 CR30 0 0 1:1 MUXING: LOADOUT = CLOCK +1 0 1 2:1 MUXING: LOADOUT = CLOCK +2 0 0 CLOCK +4 1 0 RESERVED 0 1 CLOCK +8 1 1 4:1 MUXING: LOADOUT = CLOCK +4 1 0 CLOCK .16 1 1 CLOCK +32 Command Register 3 (CR3) (CR39-CR30) COMMAND REGISTER 3 (CR3) (Address Reg (A7-A0) = 07H) This register contains a number of control bits as shown in the diagram. CR3 is a 10-bit wide register. However for program- ming purposes, it may be considered as an 8-bit wide register (CR38 and CR39 are both reserved). The diagram shows the various operations under the control of CR3. This register can be read from as well written to. In read mode, CR38 and CR39 are both returned as zeros. COMMAND REGISTER 3 BIT DESCRIPTION PRGCKOUT Frequency Control (CR31-CR30) These bits specify the output frequency of the PRGCKOUT output. PRGCKOUT is a divided down version of the pixel CLOCK. BLANK Pipeline Delay Control (CR35-CR32) These bits specify the additional pipeline delay that can be added to the BLANK function, relative to the overall device pipeline delay (tp). As the BLANK control normally enters the video DAC from a shorter pipeline than the video pixel data, this control is useful in deskewing the pipeline differential. Pixel Multiplex Control (CR37-CR36) These bits specify the devices multiplex mode. It, therefore, also determines the frequency of the LOADOUT signal. LOADOUT is a divided down version of the pixel CLOCK. Revision Register (Address reg (A7-A0) = OBH): This register is a read only register containing the revision of silicon. DIGITAL-TO-ANALOG CONVERTERS (DACS) AND VIDEO OUTPUTS The ADV7151 contains three high speed video DACs. The DAC outputs are represented as the three primary analog color signals IOR (red video), IOG (green video) and JOB (blue video). Other analog signals on the part include Ip,, and RegF as well as complementary video outputs IOR, IOG, IOB. These complementary outputs can be used to drive differentially termi- nated video loads, they will have equal but opposite output lev- els to IOR, IOG and IOB when loaded with a resistive load similar to IOR, IOG and IOB. REV.A DACs and Analog Outputs The part contains three matched 10-bit digital to analog convert- ers. The DACs are designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each digital input are routed to either IOR, IOG, IOB (bit = 1) or IOR, IOG, IOB (bit = 0). (Normally IOR, [OG, IOB = GND.) The analog video outputs are high impedance current sources. Each of the these three RGB current outputs are specified to directly drive a 37.5 2 load (doubly terminated 75 Q). -21-ADV7151 1OR, 1OG, |OB Zo =7502 (CABLE) Z, =7522 (MONITOR) Zs, =75Q (SOURCE TERMINATION) Figure 23. DAC Output Termination (Doubly Terminated 75 9) Load) IOR, |OB 10G mA Vv mA Vv Reference Input and Rog An external 1.23 V voltage reference is required to drive the analog outputs of the ADV7151. The reference voltage is con- nected to the Vper input. A resistor Rez is connected between the Rgzyz input of the part and ground. For specified performance, Rg_- has a value of 280 Q. This corresponds to the generation of RS-343A video levels (with SYNC on IOG and Pedestal = 7.5 IRE) into a dou- bly terminated 75 load. Figure 24 illustrates the resulting video waveform and the Video Output Truth Table shows the corresponding control input stimuli. WHITE 19.05 | 0.714 | 26.67 | 1.000 WHITE & BS $ o 92.5 IRE Sy BLACK 1.44 | 0.054 | 9.05 | 0.340 : PEVEL 7.5 IRE 5 7.62 | 0.286 y LANK 6 t LEVEL 40 IRE _ 0 0 SYNC LEVEL Figure 24. Composite Video Waveform SYNC Decoded on |OG; Pedestal = IRE; Rser 280 1) Table V. Video Output Truth Table Description IOG (mA) IOR, IOB (mA) SYNC BLANK DAC Input Data WHITE LEVEL 26.67 19.05 1 1 3FFH VIDEO Video + 9.05 Video + 1.44 1 1 Data VIDEO to BLANK Video + 1.44 Video + 1.44 0 1 Data BLACK LEVEL 9.05 1.44 1 1 000H BLACK to BLANK 1.44 1.44 0 1 000H BLANK LEVEL 7.62 0 1 0 xxxH SYNC LEVEL 0 0 0 0 xxxH 22- REV.AADV7151 Variations on RS-343A Various other video output configurations can be implemented by the ADV7151, including RS-170. Values of Rgp-7 for particu- lar output video formats/levels are calculated by using the equa- tions for Rg; given in the Pin Configuration section. The table shows calculated values of Rg; for some of the most com- mon variants on the RS-343A standard. The associated wave- forms are shown in the diagrams. Table VI. Roper (O ) Video Signal 265 SYNC Decoded on IOG: Pedestal = 0 IRE 280 No SYNC Decoded: Pedestal = 7.5 IRE 259 No SYNC Decoded: Pedestal = 0 IRE 1OR, 1OB 10oG mA Vv. mA Vv 18.62 | 0.698 | 26.67 | 1.000 q vee % C 100 IRE ey & BLACK/ 0 0 8.05 | 0.302 BLANK LEVEL 43 IRE _- 0 o + SYNG LEVEL Figure 25. Composite Video Waveform SYNC Decoded on !0G; Pedestal = 0 IRE; Reger = 265 02 (OR, OB, 10G ma |v 19.05 | 0.714 WHITE LEVEL Y & S 92.5 IRE s Sa S 1.44 | 0.054 - BLACK LEVEL 7.5 IRE o o + BLANK LEVEL Figure 26. Composite Video Waveform; Pedestal = 7.5 IRE; Roser = 2800 REV.A IOR, OB, 1OG mA Vv 19.05 | 0.714 WHITE LEVEL yy 100 IRE S = & | BLACK/ BLANK 0 0 x LEVEL Figure 27. Composite Video Waveform; Pedestal = 0 IRE; Reer = 2592 Ipiy Synchronization Output Control This output synchronization signal is used in applications where it is necessary to synchronize multiple palette devices (ADV7150 + ADV7151) to subpixel resolution. The Ip, output from each device is in phase with its analog RGB output signal. If multi- ple devices have differing output delays, the time difference can be measured from the Ip; , signals. This time difference is then used to phase shift the CLOCK inputs on one or other of the device inputs. The I; signal is internally triggered by either the falling edge of SYNC or BLANK as determined by CR21 of Command Register 2. ~23ADV7151 APPENDIX 1 BOARD DESIGN and LAYOUT CONSIDERATIONS The ADV7151 is a highly integrated circuit containing both pre- cision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is impera- tive that these same design and layout techniques be applied to the system level design such that high speed, accurate perfor- mance is achieved. The Recommended Analog Circuit Layout shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7151 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of V,, and GND pins should by minimized so as to minimize inductive ringing. Ground Planes The ground plane should encompass all ADV7151 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7151, the analog output traces, and all the digital signal traces leading up to the ADV7151. The ground plane is the graphics boards common ground plane. POWER SUPPLY DECOUPLING (0.14F AND 0.011 F CAPACITOR FOR EACH V,, GROUP) tL tL L ad Ge yo uu Gor Power Planes The ADV7151 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (Vaa). This power plane should be connected to the regular PCB power plane (V,) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7151. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7151 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode. a 7 tT Gu ge +5V (Vaa) +5V (Voc) ee O.1uF ]0.01KF 1) ANALOG POWER PLANE U1 (FERRITE BEAD) v v +5V (Van) +5V (Vaa) O.4uF t Van (1% METAL} O.4NE L COMP Veer Rset (1.2 REF) MONITOR ADV7151 COAXIAL CABLE (eR) 1OR 10G > > i i 7502 75Q COMPLEMENTARY OUTPUTS 10B ioR 10G (752) 7502 752 75Q2 4 BNC CONNECTORS NOTES: 1. ALL RESISTORS ARE 1% METAL FILM. 2. 0.1uF AND 0.01u.F CAPACITORS ARE CERAMIC. 3. ADDITIONAL DIGITAL CIRCUITRY OMITTED FOR CLARITY. Recommended Analog Circuit Layout ~24~- REV.AADV7151 Supply Decoupling For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable opera- tion, to reduce the lead inductance. Best performance is obtained with 0.1 pF ceramic capacitor decoupling. Each group of V,q pins on the ADV7151 must have at least one 0.1 pF decoupling capacitor to GND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV7151 contains cir- cuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power sup- ply noise and consider using a three terminal voltage regulator for supplying power to the analog power plane. Digital Signal Interconnect The digital inputs to the ADV7151 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7151 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (V,), and not the analog power plane. Analog Signal Interconnect The ADV7151 should be located as close as possible to the out- put connectors to minimize noise pick-up and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. Digital Inputs, especially Pixel Data Inputs and clocking signals (CLOCK, LOADOUT, LOADIN etc.) should never overlay any of the analog signal circuitry and should be kept as far away as possible. For best performance, the analog outputs (IOR, IOG, IOB) should each have a 75 () load resistor connected to GND. These resistors should be placed as close as possible to the ADV7151 so as to minimize reflections. Normally, the differential analog outputs (IOR, IOG, IOB) are connected directly to GND. In some applications, improvements in performance are achieved by terminating these differential outputs with a resistive load similar in value to the video load. For a doubly terminated 75 0 load, this means that IOR, IOG, IOB are each terminated with a 37.5 QO resistor. APPENDIX 2 TYPICAL FRAME BUFFER INTERFACE CLOCK ECL /}-~@_@____ CLOCK GENERATOR CLOCK To TTL > Y 1 mil PRGCKOUT _ DIVIDE BY N DIVIDE BY M (= N) (<M) LOADOUT SCKOUT CLOCK __ BLANK GRAPHICS ~ sank > PROCESSOR/ SYNC _ ENABLE CONTROLLER SYNC - A SCKIN LOADIN y VRAM [aaun, | (BANK ay L33MHz FRAME VRAM BUFFER/ (BANK B) VIDEO MEMORY (BANK C) VRAM (BANK D) | 33MHz | REV.A ADV7151 TO PALETTE/RAM & DAC ~25ADV7151 APPENDIX 3 10-BIT DACS AND GAMMA CORRECTION 10-Bit DACs 10-bit RAM-DAC resolution allows for nonlinear video correc- tion, in particular Gamma Correction. The ADV7151 allows for an increase in color resolution from 8-bit to 10-bit effective color without the necessity of a 10-bit deep frame buffer. The part operates as an 8-bit to 10-bit color look-up table. Up to now we have assumed that there exists a linear relation- ship between the actual RGB values input to a monitor and the intensity produced on the screen. This, however, is not the case. Half scale digital input (1000 0000) might correspond to only 20% output intensity on the CRT (Cathode Ray Tube). The intensity (I-p7) produced on a CRT by an input value [I,y, is given by: Torr = inh where yx ranges from 2.0 to 2.8. If the individual values of x for red, green and blue are known, then so called Gamma Correction can be applied to each of the three video input signals (I,,) therefore: Lcorected: = RU py)" (k = 1, normally) Traditionally, there has been a tradeoff between implementing a nonlinear graphics function, such as gamma correction, and color dynamic range. The ADV7151 overcomes this by increas- ing the individual color resolution of each of the red, green and blue primary colors from 8 bits per color channel to 10 bits per channel (24 bits to 30 bits), Gamma Correction 8 Bits vs. 10 Bits Gamma Corrected Quantized to Quantized to 8-Bit Data (2.7) 8 Bits 10 Bits 240 0.977797 250 1001 241 0.979304 250 1002 242 0.980807 251 1004 243 0.982306 251 1005 244 0.983801 251 1007 245 0.985292 252 1008 246 0.986780 252 1010 247 0.988264 252 1011 248 0.989744 253 1013 249 0.991220 253 1015 250 0.992693 254 1016 251 0.994161 254 1018 252 0.995626 254 1019 253 0.997088 255 1021 254 0.998546 255 1022 255 1.000000 255 1023 ~26 The table highlights the loss of resolution when 8-bit data is gamma-corrected to a value of 2.7 and quantized in a traditional 8-bit system. Note that there is no change in the 8-bit quantized data for linear changes in the input data over much of the trans- fer function. On the other hand, when quantized to 10 bits via the 10-bit RAMs and 10-bit DACs of the ADV7151, all changes on the input 8-bit data are reflected in corresponding changes in the 10-bit data. The graph shows a typical gamma curve corresponding to a gamma value of 2.7. This is programmed to the red, green and blue RAMs of the color look-up table instead of the more tradi- tional linear function. Different curves corresponding to any particular gamma value can be independently programmed to each of the red, green and blue RAMs. Other applications of the 10-bit RAM-DAC include closed-loop monitor color calibration. 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 DAC OUTPUT Normalized to 1 0.20 0.10 0.00 0 32 64 96 128 160 192 224 256 INPUT CODE - Decimal Gamma Correction Curve (Gamma Value = 2.7) REV.AADV7151 APPENDIX 4 MULTIPLE PALETTE APPLICATIONS Palette Priority Select Inputs The palette priority selection inputs allow up to four separate palette devices to be used in a single system to drive a single monitor. The IOR, IOG and IOB analog video output signals of each device are connected together, as shown. Signal inputs (PSO, PS1) determine on a pixel by pixel basis which palette device drives the monitor. This allows for implementation of multiple windows applications with each device acting as an independent palette. During initialization, each device is assigned two match bits, MR16 (PSO) and MR17 (PSI) in Mode Register MR1. PSO and PS1 inputs will select one of the pre- programmed devices at any instant when PSO, PS1 matches MR16, MRI17 respectively. PSO and PS1 are multiplexed similar to the pixel data, thus allowing for subpixel resolution. The dia- grams show an example of one ADV7150 (true-color RAM- DAC) operating in conjunction with three ADV7151s. Each dis- played window on the monitor is driven by one of the four devices. Each devices analog output signals are connected together as shown. Note: Only one palette device is selected at any particular instant. The analog output levels of the unselected devices will be 0 mA. Other applications for the palette priority function using a mini- mum of two devices (one ADV7150 and one ADV7151) include: Cursor Overlay on 24-Bit Graphics Active Live Video Overlay (from Frame Grabber) Text/Character Generation and Overlay (DENICE) _IOR, 10G, |OB - ADV7150 (DEVICE: 1) Zo =752 RO-R7 RGB Go-G7 256 x 30 ANALOG RAM VIDEO Bo-67 (CABLE) = -(()) Zyg =752 2, =752 (MONITOR) L (SOURCE PALETTE SELECT BITS | ~ _ TERMINATION) MR16 | MR17 ~ Pso, PS1 @ 0 0 ~J se Multiple Devices Termination for a Single Monitor ~ ~ ~ ~ ~ ADV7151 (1) an ~ RGB S PO-P7 256 x 30 ANALOG sO PALETTE VIDEO SS MONITOR eee TRUE-COLOR BACKGROUND e MR16 | MR17 PSO = 0: PS1=0 0 1 WINDOW 1 (Pseudo-Color) PSO=0: PS1=1 WINDOW 3 =e (Pseudo-Color) WINDOW 2 PS0=1: PS1=1 ADV7151 (2 (2) {Pseudo-Color) RGB PS0=1: PS1-0 r 256 x 30 ANALOG PALETTE VIDEO PALETTE SELECT BITS e MR16 | MR17 1 0 ADV7151 (3) Lc - RGB 256 x 30 ANALOG PALETTE VIDEO PALETTE SELECT BITS MR16 | MR17 1 1 Multiple Devices Driving a Multiwindow Application REV.A -27-ADV7151 APPENDIX 5 INITIALIZATION AND PROGRAMMING ADV7151 Initialization After power has been supplied, the ADV7151 must be initialized. The Mode Register and Control Registers must be set. The values written to the various registers will be determined by the desired operating mode of the part, i.e., 4:1 Muxing/2:1 Muxing, etc. The following sections give examples of initialization for the ADV7151. Example 1 Color Mode: 8-Bit Pseudo Color Multiplexing: 4:1] Databus 8-Bit RAM-DAC Resolution 8-Bit SYNC Enabled on GREEN OUT Pedestal 7.5 TRE Register Initialization C1 CO R/W~ Comment Write 09H to Mode Register (MR1) 1 1 0 Resets to Normal Operation, 8-Bit Bus/RAM-DAC Write 08H to Mode Register (MR1) 1 1 0 *(Initializes Pipelining Write 09H to Mode Register (MR1) 1 1 0 a Write 29H to Mode Register (MR1) 1 1 0 *(Calibrates LOADOUT/LOADIN Timing Write 09H to Mode Register (MR1) 1 1 0 a Write 04H to Address Register 0 0 0 Address Register Points to Pixel Mask Register Write FFH to Pixel Mask register 1 0 0 Sets the Pixel Mask to All 1s Write 05H to Address Register (A7A0) 0 0 0 Address Register Points to Command Register 1 Write 00H to Command Reg 1 (CR1) 1 0 0 Write 06H to Address Register (A7A0) 0 0 0 Address Register Points to Command Register 2 Write OCH to Command Reg 2 (CR2) 1 0 0 Sets 8-Bit Pseudo Color, 7.5 IRE, SYNC on Green Write 07H to Address Register (A7A0) 0 0 0 Address Register Points to Command Register 3 Write COH to Command Reg 3 (CR3) 1 0 0 Sets 4:1 Multiplexing, PRGCKOUT = CLOCK/4 Color Palette RAM Initialization Cl CO R/W Comment Write 00H to Address Register (A7A0) 0 0 0 Address Register Points to Color Palette RAM Write 00H (Red Data) to RAM Location (00H) 0 1 0 (Initializes Palette RAM Write 00H (Green Data) to RAM Location (00H) 0 1 0 ( toa Linear Ramp** Write OOH (Blue Data) to RAM Location (00H) 0 1 0 Write 01H (Red Data) to RAM Location (01H) 0 1 0 ( Write 01H (Green Data) to RAM Location (01H) 0 1 0 ( Write 01H (Blue Data) to RAM Location (01H) 0 1 0 ( . . . . . ( . . . . * . . . ( Write FFH (Red Data) to RAM Location (FFH) 0 1 0 ( Write FFH (Green Data) to RAM Location (FFH) 0 1 0 ( Write FFH (Blue Data) to RAM Location (FFH) 0 1 0 (RAM Initialization Complete *These four command lines reset the ADV7151. The pipelines for each of the Red, Green and Blue pixel inputs are synchronously reset to the Multiplexers A input. Mode Register Bit MR10 is written by a 1 followed by 0 followed by 1. LOADIN/LOADOUT timing is internally synchronized by writing a 0 followed by a 1 followed by a 0 to Mode Register MR15. The initialization must be performed in this order. These four command lines cannot be condensed into two command lines that initialize pipelining and calibrate the LOADIN/LOADOUT timing simultaneously. **This sequence of instructions would, of course, normally be coded using some form of loop instruction. _28- REV. AADV7151 Example 2 Color Mode: 8-Bit Gamma Corrected Pseudo Color (10 Bits) Multiplexing: 4:1 Databus 10-Bit RAM-DAC Resolution 10-Bit SYNC Ignored Pedestal 0 IRE Calibration Every Vertical Sync = o Register Initialization Write OFH to Mode Register (MR1) Write OEH to Mode Register (MR1) Write OFH to Mode Register (MR1) Write 2FH to Mode Register (MR1) Write OFH to Mode Register (MRI) Write 04H to Address Register (A7A0) Write FH to Pixel Mask register Write 05H to Address Register (A7A0) Write 00H to Command Reg 1 (CR1) Write 06H to Address Register (A7-A0) Write 00H to Command Reg 2 (CR2) Write 07H to Address Register (A7A0) Write Cl1H to Command Reg 3 (CR2) Color Palette RAM Initialization Write 00H to Address Register (A7A0) Write 000H (Red Data) to RAM Location (00H) Write 000H (Green Data) to RAM Location (00H) Write 000H (Blue Data) to RAM Location (00H) Write xxxH (Red Data) to RAM Location (01H) Write xxxH (Green Data) to RAM Location (01H) Write xxxH (Blue Data) to RAM Location (01H) _ . mer OR ooooooocorrrr fb Oo , OoecoeCCA OF OF OF CGH Pe HEFrA 3FFH (Red Data) to RAM Location (FFH) 0 1 3FFH (Green Data) to RAM Location (FFH) 0 1 3FFH (Blue Data) to RAM Location (FFH) 0 1 Write Write Write R/W Comment Resets to Normal Operation, 10-Bit Bus/RAM-DAC *(Initializes Pipelining *( 6c *(Calibrates LOADOUT/LOADIN Timing *( Address Register Points to Pixel Mask Register Sets the Pixel Mask to All ls Address Register Points to Command Register 1 Calibrates every Vertical Sync Address Register Points to Command Register 2 Sets Pseudo-Color, 0 IRE, No SYNC Address Register Points to Command Register 3 Sets 4:1 Multiplexing, PRGCKOUT = CLOCK/8 , oooocooR ccoeoceocoooceooo.o /W Comment Address Register Points to Color Palette RAM (Initializes Palette RAM ( to a Gamma Ramp ( ( ( ( ( ( 0 ( 0 ( 0 (RAM Initialization Complete *These four command lines reset the ADV7151. The pipelines for each of the Red, Green and Blue pixel inputs are synchronously reset to the Multiplexers A input. Mode Register Bit MR1O is written by a 1 followed by 0 followed by 1. LOADIN/LOADOUT timing is internally synchronized by writing a 0 followed by a 1 followed by a 0 to Mode Register MR15. The initialization must be performed in this order. These four command lines cannot be condensed into two command lines that initialize pipelining and calibrate the LOADIN/LOADOUT timing simultaneously. REGISTER DIAGNOSTIC TESTING The previous examples show the register initialization sequence for the ADV7151. These show control data going to the regis- ters and palette RAM. As well as this writing function, it may also be necessary, due to system diagnostic requirements, to confirm that correct data has been transferred to each register and palette RAM location. There are two ways to incorporate register value/ RAM value checking. 1. READ after each WRITE. After data is written to a particu- lar register, it can be read back immediately. The following table shows an example with Command Registers CR2 and CR3. Cl CO R/W DOD7 Comment 0 0 0 06H Select Command Register 2 (CR2) 1 0 0 00H Sets 8-Bit Pseudo-Color, No Pedestal, SYNC Not Recognized 1 0 1 00H Command Reg 2 Value Read-Back 0 0 0 07H Select Command Register 3 (CR3) 1 0 0 40H Set 2:1 Mux Mode 1 0 1 40H Command Reg 3 Value Read-Back REV.A 2. READ after all WRITEs completed. All registers and the color palette RAM are written to and set. Once this is com- plete, all registers are again accessed but this time in Read- Only mode. The table below shows this method for Command Registers CR2 and CR3. Cl CO R/W > D0-D7 Comment 0 0 0 06H Select Command Register 2 (CR2) 1 0 0 00H Sets 8-Bit Pseudo-Color, No Pedestal, SYNC Not Recognized 0 0 0 07H Select Command Register 3 (CR3) 1 0 0 40H Set 2:1 Mux Mode 0 0 0 06H Select CR2 1 0 1 00H CR2 Value Read-Back 0 0 0 07H Select CR3 1 0 1 40H CR3 Value Read-Back It is clear that this latter case requires more command lines than the previous READ after each WRITE case. ~29ADV7151 TEST DIAGNOSTICS SYNC BLANK _ v vy pel GRAPHICS PIPELINE COLOR GRAPHICS PIPELINE pata PALETTE wm) DACs - RAM = Ga TRIGGER wocpe DECODE YY COLOR SYNC BLANK | PIXEL TEST DAC TEST le, TEST > REGISTER REGISTERS REGISTERS [> A REGISTER | | I MPU PORT rit CE RW Co C1 v De-Do Test/Diagnostic Block Diagram The ADV7151 contains on-board circuitry which enables both device and system level test diagnostics. The test circuitry can be used to test the frame buffer memory as well as the function- ality of the ADV7151. A number of test registers are integrated into the part which effectively allow for monitoring of the graphics pipeline. Pixel data is read from the graphics pipeline independent of the pixel CLOCK. The pixel data itself contains the triggering information that latches data into the test regis- ters. This allows for system diagnostics in a continuously clocked graphics system. The test register data is then read by the microprocessor over the MPU. Access to the test registers is as described in the Microproces- sor (MPU) Port section. This section also gives the address decode locations for the various test registers. Test Trigger (P2) The test trigger is decoded from the pixel data stream. Bit P2 [A-D] is assigned the task of latching pixel data into the test registers. A 0 to 1 or a 1 to 0 (as determined by bit CR20 of Command Register 2) transition on P2, fills the test register with the corresponding pixel data. This effectively means that a sequence of data travels along the graphics pipe- line, with the test registers taking a sample only when there is a transition on bit P2. The following example shows a sequence with the ADV7151 preset to sample the graphics pipeline on a low to high transition of P2. PixelO: .... 0000 Pixel l: ww. 0000 Pixel 2: ..... 0000 Pixel 3: www. 0100 Pixel 3 Latched to Test Register Pixel 4: ..... 0000 Pixel n-l1: ww we, 1011 Pixeln: wwe. 1111; Pixel n Latched to Test Register Pixeln+1i: ..... 1111 In the above sequence of pixels, there is a rising edge on P2 on Pixel 3. The data for Pixel 3 therefore gets latched into the Pixel Test Register. Pixel 3 continues down the graphics pipeline and 30- after a number of clocks gets latched into the DAC Test Regis- ter. This data can then be read from the Pixel Test Register and the DAC Test Registers over the MPU Port. This data will remain in the Pixel Test Registers and the DAC Test Registers until the next rising edge of P2 causes new data to be latched in. In the above example, the next rising edge of P2 occurs on the Pixel n input. Therefore the data in the Pixel Test Registers and DAC Test Registers must be read over the MPU before the Pixel n data is applied, otherwise they will be overwritten by the Pixel n data and the Pixel 3 data will be lost. Pixel Test Register The read-only Pixel Test Register is 8 bits wide. It is situated directly after the Pixel Mask Register. After data is latched into this register by a transition on P2, it is read in three cycles over the MPU Port as described in the Microprocessor (MPU) Port section. DAC Test Register The DAC Test Register is latched with data some CLOCKs after the Pixel Test Register. The DAC Test Register is a 30-bit wide read-only register, corresponding to 10 bits each for red, green and blue data. It is located after the Color Palette RAM. If the RAM-DAC is in 8-bit resolution mode, the upper two bits of the red green and blue data will be zero. After data is latched into the DAC Test Register by a transition on P2, it is read in three or six cycles over the MPU Port as described in the Microprocessor (MPU) Port section. SYNC, BLANK and I), , Test Register This is an 8-bit wide register but with only three effective bits. The three lower bits correspond to SYNC, BLANK and Ip; 7 respectively. The upper bits should be masked in software. This register 1s at the same position in the graphics pipeline as the DAC Test Register. When pixel data is latched into the DAC Test Register, the corresponding status of SYNC, BLANK and Ipzz is latched into this register. It is read over the MPU Port as described in the Microprocessor (MPU) Port section. (Note: If BLANK is low, the corresponding pixel data to the DAC Test Register will be all Os.) REV.AADV7151 APPENDIX 7 THERMAL AND ENVIRONMENTAL CONSIDERATIONS The ADV7151 is a very highly integrated monolithic silicon device. This high level of integration, in such a small package, inevitably leads to consideration of thermal and environmental conditions in which the ADV7151 must operate. Reliability of the device is significantly enhanced by keeping it as cool as pos- sible. In order to avoid destructive damage to the device, the absolute maximum junction temperature of 150C must never be exceeded. Certain applications, depending on pixel data rates, may require forced air cooling or external heatsinks. The follow- ing data is intended as a guide in evaluating the operating condi- tions of a particular application so that optimum device and system performance is achieved. It should be noted that information on package characteristics pub- lished herein may not be the most up to date at the time of reading this. Advances in package compounds and manufacture will inevita- bly lead to improvements in the thermal data. Please contact your local sales office for the most up-to-date information. Power Dissipation The diagram shows graphs of power dissipation in watts versus pixel clock frequency for the ADV7151. 1.50 ] | Vaa = 5V Vaer = 1.2V 2 125 Ty = 425C o = I z a 60 1 ee a a a a a g 3 0.75 a 0.50 60 80 100 120 140 160 180 200 220 PIXEL CLOCK FREQUENCY MHz * THE "WORST CASE ON-SCREEN PATTERN CORRESPONDS TO FULL SCALE TRANSITION ON EACH PIXEL VALUE FOR EVERY CLOCK EDGE (00H, FFH, OOH,....). THE "TYPICAL ON-SCREEN PATTERN CORRESPONDS TO LINEAR CHANGES IN THE PIXEL INPUT (1.E., A BLACK TO WHITE RAMP). IN GENERAL, COLOR IMAGES TEND TO APPROXIMATE THIS CHARACTERISTIC. Typical Power Dissipation vs. Pixel Rate Package Characteristics The table of thermal characteristics shows typical information for the ADV7151 (100-Lead Plastic Power QFP) using various values of airflow. Junction to Case (@,,). Thermal resistance for this particular part is: ; (100-Lead Plastic Power QFP) = 1.0 C/W (Note: Qy is independent of airflow. ) REV.A Table A. Thermal Characteristics vs. Airflow Air Velocity 0 50 100 | 200 (Linear feet/min) (Still Air) 874 CCW) No Heatsink 35 31 | 28 25 EG&G D10100-28 Heatsink | 32 28 | 25 22 Thermalloy 2290 Heatsink 25 21 18 15 The junction temperature of the device in a specific application is given by: Ty = Ta + Pp (jc + Oca) (1) or T, =Ta + Pp (8y4) (2) where: T, = Junction Temperature of Silicon (C) T, = Ambient Temperature C) P,, = Power Dissipation (W) ;- = Junction to Case Thermal Resistance C/W) ca = Case to Ambient Thermal Resistance C/W) ;, = Junction to Ambient Thermal Resistance (C/W) Package Enhancements The standard QFP package has been enhanced to a PowerQuad2 package. This supports an improved thermal performance com- pared to standard QFP. In this case, the die is attached to a heatslug so that the power that is dissipated can be conducted to the external surface of the package. This provides a highly effi- cient path for the transfer of heat to the package surface. The package configuration also provides an efficient thermal path from the ADV7151 to the Printed Circuit Board via the leads. Heatsinks The maximum silicon junction temperature should be limited to 100C. Temperatures greater than this will reduce long term device reliability. To ensure that the silicon junction tempera- ture stays within prescribed limits, the addition of an external heatsink may be necessary. Heatsinks, will reduce 8;, as shown in the Thermal Characteristics vs. Airflow table. 31-ADV7151 APPENDIX 8 PACKAGE OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 100-Lead Plastic Quad Flatpack S-100 0.952 (24.15) 0.932 (23.65) 0.792 (20.10) 0.784 (19.90) A r 0.715 (18.15) 0.696 (17.65) TOP VIEW 0.556 (14.10) 0.548 (13.90) (0.102) | ae >| MAX 0.014 (0.35) 0.030 (0.75) 0.054 (1.37) 0.011 (0.27) 0.022 (0.55) 0.046 (1.17) 0.134 _. 0.116 (2.94) (3.40) = a OO 19 da) MAX t i 0.096 (2.44) el be 0.037 (0.95) 0.054 (1.37) 0.026 (0.65) 0.046 (1.17) 32 REV.A C1694a7.5-1/94 PRINTED IN U.S.A.