8D132(X), MT16D232 us x 32 DRAM MODU 1 MEG, 2 MEG x 32 4, 8 MEGABYTE, 5V, FAST PAGE OR EDO PAGE MODE leet Ts) eater DRAM MODULE FEATURES * JEDEC- and industry-standard pinout in a 72-pin, single-in-line memory module (SIMM) PIN ASSIGNMENT (Front View) * High-performance CMOS silicon-gate process. 72-Pin SIMM * Single +5V +10% power supply . All device pins are TTL-compatible (DD-3) 1 Meg x 32 Low power, 48mW standby; 1,824mW active, typical (DD-4) 2 Meg X 32 (8MB) * Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR) and HIDDEN " Multiple RAS lines allow x16 or x32 width * 1,024-cycle refresh distributed across 16ms * FAST PAGE MODE (FPM) operating mode or Extended Data-Out (EDO) PAGE MODE operating mode OPTIONS Timing 60ns access -6 70ns access (FAST PAGE MODE only) 7 MARKING Packages 72-pin SIMM 72-pin SIMM (gold) Operating Modes FAST PAGE MODE Blank EDO PAGE MODE X KEY TIMING PARAMETERS EDO Operating Mode M G SPEED | RC tRAC 'pc 'cac | cas -6 110ns | 60ns 26ns 17ns 13ns FPM Operating Mode SPEED 'Re 'Rac 'pc tcac 'RP 6 110ns | 60ns 35ns 15ns 40ns 7 130ns | 70ns 40ns 20ns 50ns *4MB version only MT8D192(X), MT16D232(X) DMS3.pm6 - Rev. 12/95 5-17 -Micron Technology, Inc., reserves the right to change products or specifications without notice. 1995, Micron Technology, Inc. WWIS NVHd iWIS NVua i | MT8D132(X), MT16D232(X) 1 MEG, 2 MEG x 32 DRAM MODULES PART NUMBERS EDO Operating Mode PART NUMBER MT8D132G-xx X MT8D132M-xx X MT16D232G-xx X MT16D232M-xx X xx = speed DESCRIPTION 1 Meg x 32, EDO, Gold 1 Meg x 32, EDO, Tin/Lead 2 Meg x 32, EDO, Gold 2 Meg x 32, EDO, Tin/Lead FPM Operating Mode PART NUMBER DESCRIPTION MT8D132G-xx 1 Meg x 32, Gold MT8D132M-xx 1 Meg x 32, Tin/Lead MT16D232G-xx MT16D232M-xx xx = speed GENERAL DESCRIPTION The MT8D132(X) and MT16D232(X) are randomly ac- cessed 4MB and 8MB solid-state memories organized in a x32 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits; which are entered 10bits (A0-A9) ata time. RASis used to latch the first 10 bits and CAS the latter 10 bits. A READ or WRITE 2 Meg x 32, Gold 2 Meg x 32, Tin/Lead cycle is selected with the WE input. A logic HIGH on WE dictates READ mode while a logic LOW on WE dictates WRITE mode. During a WRITE cycle, data-in(D) is latched by the falling edge of WE or CAS, whichever occurs last. EARLY WRITE occurs when WE goes LOW prior to CAS going LOW, the output pin(s) remain open (High-Z) until the next CAS cycle. FAST PAGE MODE FAST PAGE MODE operations allow faster data o opera- tions (READ or WRITE) within a row-address-defined (A0-A9) page boundary. The FAST PAGE MODE cycle is always initiated with a row-address strobed-in by RAS followed by a column-address strobed-in by-CAS. CAS may be toggled-in by holding RAS LOW and strobing-in different column-addresses, thus executing faster memory cycles. Returning RAS HIGH terminates the FAST PAGE MODE operation. EDO PAGE MODE EDO PAGE MODE, designated by the X version, is an accelerated FAST PAGE MODE cycle. The primary advan- tage of EDO is the availability of data-out even after CAS goes back HIGH. EDO provides for CAS precharge time (CP) to occur without the output data going invalid. This elimination of CAS output control provides for pipeline READs. FAST PAGE MODE modules have traditionally turned the output buffers off (High-Z) with the rising edge of CAS. EDO operates as any DRAM READ or FAST-PAGE- MODE READ, except data will be held valid after CAS goes HIGH, as long as RAS and OE are held LOW and WE is held HIGH (reference MT4C4007] DRAM data sheet for additional information on EDO functionality). REFRESH Returning RAS and CAS HIGH terminates a memory cycle and decreases chip current toa reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS HIGH time. Memory cell data is retained in its correct state by maintaining power and executing any RAS cycle (READ, WRITE) or RAS refresh cycle (RAS ONLY, CBR or HIDDEN) so that all 1,024 combination of RAS addresses (A0-A9) are executed at least every 16ms, regardless of sequence. x16 CONFIGURATION For x16 applications, the corresponding DQ and CAS pins must be connected together (DQ1 to DQ17, DQ2 to DQI18 and so forth, and CASO to CAS2 and CAS] to CAS3). Each RAS is then a bank select for the x16 memory organization. . MT8D132(x), MT16D232(X} DMS53.pmi5 Rev. 12/95. . Micron Technology, Inc., reserves the right to change products or specifications without notice. 1995, Micron Technology, Inc.MR PaET NOME ePKrlne) 1 MEG, 2 MEG x 32 DRAM MODULES FUNCTIONAL BLOCK DIAGRAM MT8D132(X) (4MB) pat - 4 DQI-4 Dai -4 WE WE WE ut u2 us CASO CAS Cas CAS RASO RAS RAS RAS [ OE A0-Ag GE A0-A9 OE A0-A9 CAST WE -? CAS2 RAS2 OE A0-Ag OE Ac-A9 CAS A0-AQ FAST PAGE MODE U1-U8 = MT4C4001 JDJ EDO PAGE MODE U1-U8 = MT4C4007JNDJ MT8D192(X), MT160232(X) DMS3.pm5 Rev. 12/95 WIS NVC i 5-19 Micron Technology, Inc., reserves the right to change products or specilications without noice. 1995, Micron Technology, Ine.WWIS NVA | MICRON a MT8D132(X), MT16D232(X) 1 MEG, 2 MEG x 32 DRAM MODULES FUNCTIONAL BLOCK DIAGRAM MT16D232(X) (8MB) DQ1 crrserrersensccetsetsenss bos DOQ -rresreecreseeersesetceee DQI6 DQi-4 11 - 4 DQ1-4 Dai-4 WE WE WE WE a Ui __ 2 __ us U4 CASO CAS cas cas CAS RASO RAS RAS RAS RAS - OE AC-A9 LD OE Ao-Ag rr OE Av-A9 = GE A0-A9 CAST DONT seneeeseeeeeescceesees paz4 DQ25 sreeneseccetceetsceeece DaQs2 DQ1-4 DQi-4 DQi-4 ba1-4 WE WE WE We WE Us ve u7 __ us CAS2 CAS TAS TAS CAS RAS2 RAS RAS RAS RAS L OE A0-Ad Lr OE AO-Ag Lr OE A0-Ag 2 OE Ad-Ag Cass AQ-Ag DOA --ssrsvsrencencesetcstcnee Das DOQQ vvenrereseeetttsctcresee DaI6 DQ -4 DQi-4 DQi -4 DQ1-4 WE WE WE WE ug __ U0 uy ute CAS CAS TAS CAS RAS RAS -| RAS | RAS RAS GE A0-Ag L GE Ao-Ae LC OE Ao-aa Cc OE aA0-Ag DQU7 wnreereeeesenteceseeese Daz4 DQ25 v---erororeeerencesceece pa32 DQ1-4 DQ1-4 DQI-4 DQ1-4 WE WE WE We _ UIs __ U4 Ui6 __ U6 CAS TAS TAS CAS RASS RAS RAS RAS RAS LC OE _A0-A9 i OE A0-A9 = OE A0-Ag LC OE A0-Ag FAST PAGE MODE Ut-U16 = MT4C4001J EDO PAGE MODE U1-U16 = MT4C4007JDJ * MTaD192(x), MT16D232(X) 5 20 Micron Technology, Inc., reservas the right to change products or specifications without notice. = Rev. 12/95 Ot 1995, Micron Technology, Inc,MT8D132(X), MT16D232(X) 1 MEG, 2 MEG x 32 DRAM MODULES TRUTH TABLE ADDRESSES DATA-IN/OUT FUNCTION RAS CAS WE 'R tc DQ1-DQ32 Standby H HX xX x x ~ High-Z READ L L H ROW COL Data-Out EARLY WRITE L L L ROW COL Data-In EDO/FAST-PAGE- ist Cycle L H>L H ROW GOL Data-Out MODE READ 2nd Cycle L H>L H n/a COL Data-Out Any Cycle L L-H H n/a n/a Data-Out . (X version) EDO/FAST-PAGE- ist Cycle L H>L L ROW COL Data-In MODE EARLY.WRITE | 2nd Cycle L H>L L na COL Data-in RAS-ONLY REFRESH L H xX ROW na _ High-Z HIDDEN READ L>H=L L H ROW COL Data-Out REFRESH WRITE L>H>L L L ROW COL Data-In CBR REFRESH H=L L H X X High-Z JEDEC DEFINED PRESENCE-DETECT - MT8D132(X) (4MB) SYMBOL PIN # 6 7 PRD1 67 Vss Vss PRD2 68 Vss Vss PRD3 69 NC Vss PRD4 70 NC NG JEDEC DEFINED PRESENCE-DETECT - MT16D232(X) (8MB) SYMBOL PIN # 6 -7 PRD1 67 NC NC PRD2 68 NC NC PRD3 69 NC Vss PRD4 70 NC NC MT8D132(X), MT16D232(X) 5 2 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. DMS53.pm85 - Rev. 12/95 = 1995, Micron Technol Ing. logy, WIWNIS NVHa iea Lee [om MT8D132(X), MT16D232(X) 1 MEG, 2 MEG x 32 DRAM MODULES ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss Operating Temperature, T, (ambient) Storage Temperature (plastic) Power Dissipation 0... Short Circuit Output Current *Stresses greater than those listed under Absolute Maxi- mum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (Notes: 1, 3, 6) (Vcc = +5V +10%) PARAMETER/CONDITION SYMBOL | MIN MAX | UNITS NOTES Supply Voltage Voc 45 5.5 Vv . | Input High (Logic 1) Voltage, all inputs Vin 24 |Vec+t] V 0 Input Low (Logic 0) Voltage, all inputs . Vit -1.0 0.8 Vv Vv INPUT LEAKAGE CURRENT CAS0-CAS3 In -8 8 HA > Any input OV < Vin < Vcc +1.0V A0-A9, WE te -32 32 DA 25 (All other pins not under test = QV) RASO-RAS3 lis -8 8 LA 25 = OUTPUT LEAKAGE CURRENT DQ1-DQ32 loz -20 20 pA 25 wo (Q is disabled; OV < Vout < 5.5V) aay | OUTPUT LEVELS VoH 24 Vv = High Voltage (lout = -5mA) VoL 0.4 Vv = Low Voltage (lout = 4.2mA) MAX PARAMETER/CONDITION SYMBOL| SIZE 6 -T | UNITS| NOTES STANDBY CURRENT: (TTL) Icci | 4MB 16 16 mA (RAS = CAS = Vin) 8MB 32 32 STANDBY CURRENT: (CMOS) Icc2 | 4MB 8 8 mA (RAS = CAS = other inputs = Vcc -0.2V) ; 8MB 16 16 OPERATING CURRENT: Random READ/WRITE 4MB 880 800 mA | 2.24 Average power supply current loca sMB | 896 816 , (RAS, CAS, address cycling: RC = 'RC [MIN]) OPERATING CURRENT: FAST PAGE MODE amp | 640 560 ma | 2.24 Average power supply current / Ieca 8MB | 656 576 , (RAS = Vit, CAS, address cycling: PC = PC [MIN]) OPERATING CURRENT: EDO PAGE MODE Iecs 4mB | 640 _ mA 9 Average power supply current (X only) 8MB | 656 _ (RAS = Vir, CAS, address cycling: PC = PC [MIN]) REFRESH CURRENT: RAS ONLY Average power supply current Icce aM ao are mA | 2, 24 (RAS cycling, CAS = Vin: *RC = 'RC [MIN]) , REFRESH CURRENT: CBR Average power supply current loc7 ove a ate mA | 2,19 (RAS, CAS, address cycling: RC ='RC [MIN]) MT8D132(X), MT16D232(X) OMS3.pm5 Rev. 12/95. 5-22 Micron Technology, inc., reserves the right to change products or specifications without notice. 1995, Micron Technology, Inc. MH 6131549 00235b3 Te4 =emt Te] MIR b REPT Ab8 Teewrs.aov.ne 1 MEG, 2 MEG x 32 DRAM MODULES CAPACITANCE . . MAX PARAMETER SYMBOL | 4MB | 8MB_ | UNITS | NOTES Input Capacitance: AO-A9 Cn 48 95 pF 17 Input Capacitance: WE Cre 64 127 pF 17 Input Capacitance: RASO-RAS3- oe Ci 32 32 pF 17 Input Capacitance: CASO-CAS3 . . Cis 16 32 pF 17. Input/Output Capacitance: DQ1-DQ32 Cio 10 18 pF 17 FAST PAGE MODE ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS. (Notes: 3, 4, 5, 6, 7, 10, 11, 16) (Voc = +5V +10%) AC CHARACTERISTICS - FAST PAGE MODE OPTION . 6 7 . PARAMETER SYM MIN MAX MIN MAX UNITS NOTES Access time from column-address AA 30 35 ns Column-address hold time (referenced to RAS) aR 45 50 ns Column-address setup time tasC 0 0 ns Row-address setup time tASR 0 0 ns Access time from CAS CAC 15 20 ns 9 Column-address hold time CAH 10 15 ns CAS pulse width CAS 15 10,000 20 10,000 ns CAS hold time (CBR REFRESH) CHR 10 10 ns 19 CAS to output in Low-Z 'CLZ 0 0 ns CAS precharge time tcp 10 10 : ns 18 Access time from CAS precharge 'CPA 35 40 ns CAS to RAS precharge time iCRP 10 10 ns CAS hold time 'CSH 60 70 ns CAS setup time (CBR REFRESH) 'CSR 10 10 ns 19 Write command to CAS lead time CWL 15 20 ns Data-in hold time 'DH 10 15 ns 15 Data-in hold time (referenced to RAS) 'DHR 45 55 ns Data-in setup time Ds _o 0 ns 15 Output buffer turn-off delay OFF 3 15 3 20 ns 12, 23, 26 FAST-PAGE-MODE READ or WRITE cycle time ipPC 35 40 ns Access time from RAS 'RAC 60 70 ns 8 RAS to column-address delay time 'RAD 15 30 15 35 ns 22 Row-address hold time ; 'RAH 10 10 ns Column-address to RAS lead time 'RAL 30 35 ns RAS pulse width tRAS 60 10,000 70 10,000 ns RAS pulse width (FAST PAGE MODE) tRASP 60 100,000 70 100,000 ns Random READ or WRITE cycle time 'RC 110 130 ns RAS to CAS delay time RCD 20 45 20 50 ns 13 Read command hold time (referenced to CAS) 'RCH 0 0 ns 14 Read command setup time RCS 0 0 ns Refresh period (1,024 cycles) 'REF 16 16 ms Oueonme ney epeset) . . 5-23 Micron Technology, Inc., reserves the right to change PEt ooo Maen Tostnelege ie M8 6311549 0013564 965 WINIS NV |WWIS NVHG MICRON MT8D132(X), MT16D232(X) 1 MEG, 2 MEG x 32 DRAM MODULES FAST PAGE MODE ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 3, 4, 5, 6, 7, 10,.11, 16) (Vcc = +5V +10%) AC CHARACTERISTICS - FAST PAGE MODE OPTION 6 7 : PARAMETER SYM ~ MIN MAX MIN MAX UNITS NOTES RAS precharge time 'RP 40 50 ns RAS to CAS precharge time tAPC 0 0 . ns Read command hold time 'RRH 0 0 ns 14 RAS hold time 'RSH 15 20 ns Write command to RAS lead time ~ TRWL 15 20 ns Transition time (rise or fall) tT 3 50 3 50 ns Write command hold time tWCH 10 15 . ns Write command hald time (referenced to RAS) WCR 45 55 ns WE command setup time twcs 0 0 ns Write command pulse width twPp 10 15 ns WE hold time (CBR REFRESH) 'WRH 10 10 ns WE setup time (CBR REFRESH) WRP 10 . 10. ns Dussemo Rev. 128 5-24 _ Moron Tedhaciog In reser he igh i Shane Ee eee MM 6411549 OO1L3565 87)Mtl Tes] Riser Ne Relea MT8D132(X), MT16D232(X) 1 MEG, 2 MEG x 32 DRAM MODULES EDO PAGE MODE ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 3, 4, 5, 6, 7, 10, 11, 16) (Voc = +5V +10%) AC CHARACTERISTICS - EDO PAGE MODE OPTION 6 : PARAMETER SYM MIN MAX UNITS NOTES Access time from column-address TAA 30 ns Column-address setup to CAS precharge during WRITE tACH 16 ns Column-address hold time (referenced to RAS) AR 45 ns Column-address setup time tasc 0 ns Row-address setup time 'aSR 0 ns Access time from CAS 'CAC 17 ns 9 Column-address hold time CAH 10 ns CAS pulse width CAS 13 10,000 ns CAS hold time (CBR REFRESH) CHR 10 ns 19 CAS to output in Low-Z 'CLZ 3 ns 23 Data output hold after CAS LOW 'COH 5 ns CAS precharge time tcp 10 . ns 18 Access time from CAS precharge tCPA 35 ns .. CAS to RAS precharge time 'CRP 10 ns CAS hold time 'CSH 50 ns CAS setup time (CBR REFRESH) icSR 10 ns 19 Write command to CAS lead time tCWL 15 ns Data-in hold time 'DH 9 ns 15 Data-in hold time (referenced to RAS) 'DHR 45 ns Data-in setup time tps 0 ns 15 Output buffer turn-off delay OFF 3 15 ns 12, 23, 26 FAST-PAGE-MODE READ or WRITE cycle time PC 26 ns Access time from RAS RAC 60 ns 8 RAS to column-address delay time 'RAD 15 30 ns 22 Row-address hold time 'RAH 10 ns Column-address to RAS lead time RAL 30 ns RAS pulse width 'RAS 60 10,000 ns RAS pulse width (FAST PAGE MODE) TRASP 60 100,000 ns Random READ or WRITE cycle time tRC 110 ns RAS to CAS delay time 'RCD 20 45 ns 13 Read command hold time (referenced to CAS) RCH 0 ns 14 Read command setup time 'RCS 0 ns Refresh period (1,024 cycles) 'REF 16 ms MT8D132(X), MT16D232(x) DMS53.pm65 Rev. 12/85 MM 6111549 5-25 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1995, Micron Technology, Inc. 00135bb 738 mm INWIS NV iWIS a MICRON MT8D132(X), MT16D232(X) 1 MEG, 2 MEG x 32 DRAM MODULES EDO PAGE MODE ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 3, 4, 5, 6, 7, 10, 11, 16) (Vcc = +5V +10%) AC CHARACTERISTICS - EDO PAGE MODE OPTION : 6 PARAMETER SYM MIN MAX UNITS NOTES RAS precharge time . tAP 40 ns RAS to CAS precharge time RPC 5 ns Read command hoid time : 'RRH 0 ns 14 RAS hold time 'RSH 15 ns Write command to RAS lead time 'RWL 15 ns Transition time (rise or fall) i 1.5 50 ns 4,5 Write command hold time 'WCH 10 ns Write command hold time (referenced to RAS) 'WCR 45 ns WE command setup time twos 0 ns | Output disable delay from WE (CAS HIGH) tWHZ 3 15 ns Write command pulse width twP 10 ns WE pulse width for output disable when CAS HIGH 'WPZ 10 ns WE hold time (CBR REFRESH) 'WRH 10 ns WE setup time (CBR REFRESH) : twWRP 10 ns MT8D132(X), MT16D232(x) 5 26 Micron Technology, Inc., reserves the right te change products or specifications without notice. DMS&3.pm5 = Rev. 12/95 = 1995, Micron Technology, inc. Me 6212549 0013567 b74MICRON MT8D132(X), MT16D232(X) 1 MEG, 2 MEG x 32 DRAM MODULES NOTES 1. All voltages referenced to Vss. 14. Either RCH or RRH must be satisfied for a READ 2. Icc is dependent on output loading and cycle rates. cycle. Specified values are obtained with minimum cycle 15. These parameters are referenced to CAS leading edge time and the output open. in EARLY WRITE cycles. 3. An initial pause of 100s is required after power-up 16. In addition to meeting the transition rate specifica- followed by eight RAS refresh cycles (RAS ONLY or tion, all input signals must transit between Vii and CBR with WE HIGH) before proper device operation Vit (or between Vit and Vin) in a monotonic manner. is assured. The eight RAS cycle wake-ups should be 17. This parameter is sampled. Capacitance is measured - repeated any time the 'REF refresh requirement is using MIL-STD-883C, Method 3012.1 (1 MHz AC, exceeded. Vee = 4.5V, DC bias = 2.4V at 15mV RMS). 4, AC characteristics assume 'T = 5ns for FAST PAGE 18. If CAS is LOW at the falling edge of RAS, data-out MODE and 'T = 1.5ns for EDO PAGE MODE. (Q) will be maintained from the previous cycle. To 5. Vin (MIN) and Vi (MAX) are reference levels for initiate a new cycle and clear the data-out buffer, CAS: po measuring timing of input signals. Transition times must be pulsed HIGH for 'CP. are measured between Vin and VIL. . 19. On-chip refresh and address counters are enabled. 6. The minimum specifications are used only to indicate 20. A HIDDEN REFRESH may also be performed after a 0 cycle time at which proper operation over the full . WRITE cycle. In this case, WE = LOW. temperature range (0C < T, < 70C) is assured. 21. LATE WRITE, READ WRITE or READ-MODIFY- > 7. Measured with a load equivalent to two TTL gates WRITE cycles are not available due to OE being and 100pP. grounded on U1-U8/U16. 8. Assumes that RCD < RCD (MAX). If RCD is greater 22. Operation within the RAD (MAX) limit ensures that ~ than the maximum recommended value shown in this 'RCD (MAX) can be met. RAD (MAX) is specifiedas = table, RAC will increase by the amount that RCD a reference point only; if RAD is greater than the exceeds the value shown. specified RAD (MAX) limit, then access time is = 9. Assumes that RCD 2 *RCD (MAX). controlled exclusively by tAA. 10. If CAS and RAS = Vin, data output is High-Z. 23. The 3ns minimum is a parameter guaranteed by 11. If CAS = Viz, data output may contain data from the design. last valid READ cycle. 24. Column-address changed once each cycle. 12. OFF (MAX) defines the time at which the output 25. 4MB module values will be half of those shown. achieves the open circuit condition and is not 26. For FAST PAGE MODE option, OFF is determined referenced to Vou or VoL. by the first RAS or CAS signal to transition HIGH. In 13. Operation within the RCD (MAX) limit ensures that comparison, OFF on an EDO option is determined by *RAC (MAX) can be met. RCD (MAX) is specified as the latter of the RAS and CAS signal to transition a reference point only; if RCD is greater than the HIGH. specified *RCD (MAX) limit, then access time is 27. Applies to both EDO and FAST PAGE MODEs. controlled exclusively by *CAC. MTaD132(X), MT16D232(X) 5 27 Micron Technology, Inc., reserves the right to change products ar spacifications without notice. DM53.pm5 Rev. 12/95 * 1995, Micron Technotogy, inc. MH 6111549 00135b8 SOO @WIS WWHG MT8D132(X), MT16D232(x) 1 MEG, 2 MEG x 32 DRAM MODULES _ Vy Ras Vin - cas vi T v ADDR Vit" = Vv WE vil DQ VIOH READ CYCLE (FAST PAGE MODE Module) tras COLUMN VALID DATA VioL DON'T CARE R&8) UNDEFINED FAST PAGE MODE TIMING PARAMETERS 6 7 6 7 SYM MIN MAX MIN MAX | UNITS SYM MIN MAX MIN MAX | UNITS 'AA 30 35 ns 'RAD 15 30 15 35 ns AR 45 50 ns RAH 10 10 ns taSC 6 0 ns 'RAL 30 35 ns ASR 0 0 ns RAS 60- | 10,000] 70 | 10,000] ns CAC 15 20 ns 'RC 110 J 130 ns 'CAH 10 15 ns RCD 20 45 20 50 ns icaS 15 10,000 | 20 10,000 ns 'RCH 0 0 ns 1CLZ 0 0 ns RCS 0 0 ns {CRP 10 10 ns iRP 40 50 ns. 'CSH 60 70 ns 'RRH 0 0 ns OFF 3 15. 3 20 ns 'RSH 15 20 ns 'RAC 60 70 ns MTED132(X), MT16D232(X) DMS53.pmS ~ Rev, 12/95 5-28 Micron Technology, Inc., reserves the right to change products or specifications without notice, 1995, Micron Technology, inc. MH 6131545 0013569 447Wala [a] Petree MT8D132(X), MT16D232(x) 1 MEG, 2 MEG x 32 DRAM MODULES READ CYCLE (EDO PAGE MODE Module) tras - Vy RAS VL CAS) VIH ~ Vit - Vv ADDR vii ROW twaP || WRH WE Vin Vit You pa yeh COLUMN VALID DATA OPEN DON'T CARE $88] UNDEFINED NOTE: 1. Although WE is a dont care at RAS time during an access cycle (READ or WRITE), the system designer should implement WE HIGH for WRP and WRH. This design implementation will facilitate compatibility with future EDO DRAMs. 2. OFF is referenced from rising edge of RAS or CAS, whichever occurs last. EDO PAGE MODE TIMING PARAMETERS SYM 17 10,000 6 MAX | UNITS ns ns ns ns ns ns ns ns ns ns ns ns MT8D132(X), MT16D23200 DM53.pm5 Rev. 12/95. ME 6121549 5-29 Micron Technology, Inc., reserves the right to change products or specilications without notice. 0013570 465 my 1995, Micron Technology, Inc. WIWIS NV |MT8D132(X), MT16D232(x) 1 MEG, 2 MEG x 32 DRAM MODULES EARLY WRITE CYCLE 2 Vv Ras vit CAS Vi Vit Vv v appr yi / COLUMN WE Vis Vit Viou 08 VioL VALID DATA DON'T CARE EX3) UNDEFINED WINIS WVHa | NOTE: 1. Although WE is a dont care at RAS time during an access cycle (READ or WRITE), the system designer should implement WE HIGH for 'WRP and WRH. This design implementation will facilitate compatibility with future EDO DRAMs. FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS 6 7 . 6 , 7 : SYM MIN MAX MIN MAX UNITS SYM MIN MAX MIN MAX UNITS 15 _ ns 'RAD 15 30 15 35 ns 45 ns RAH 10 10 ns 0 ns 'RAL 30 35 ns QO ns 'RAS 60 10,000 70 10,000 ns 10 ns iRC 110 130 ns 10,000 ns 'RCD 20 45 20 50 ns 10,000 ns 'RP 40 50 ns ns 'RSH 15 20 ns ns 'AWL : 15 20 ns ns 'WCH 10 15 ns ns 'WCR 45 55 ns. ns twcs 0 : 0 ns ns twe 10 15 ns ns tWRH 10 10 ns ns tWRP 10 10 ns MTSD132(X), MT16D232(x) 5 3 9) Micron Technology, Inc., reserves the right to change products or specilications without notice, DMS53.pm5 Rav. 12/95 = 1995, Micron Technology, Inc. MM 6123549 0013571 OTSMICRON MT8D132(X), MT16D232(X) 1 MEG, 2 MEG x 32 DRAM MODULES RAS CAS ADDR Wwe XH FAST-PAGE-MODE READ CYCLE Vin = Vit Vin Vit Vv viE COLUMN Vit DQ vigh OPEN DONT CARE RQ unperined FAST PAGE MODE TIMING PARAMETERS -6 7 6 7 SYM MIN MAX MIN MAX UNITS SYM MIN MAX MIN MAX UNITS TAA 30 35 ns Pc 35 40 ns 'aR 45 50 ns RAC 60 70 ns taSC 0 0 ns - 'RAD 15 30 15 35 ns ASR 0) 0 ns RAH 10 10 ns CAC 15 20 ns 'RAL 30 : 35 ns CAH 10 15 ns 'RASP 60 100,000 70 100,000 ns CAS 15 10,000 20 10,000 ns RCD 20 45 20 50 ns cLz 0 0 ns RCH 0 0 ns tcp 10 10 ns rcs 0 0 ns CPA 35 40 ns iRP 40 50 ns CRP 10 10 ns 'RRH 0 0 ns 'CSH 60 70 ns 'RSH 15 20 ns OFF 3 15 3 20 ns MT6D132(x), MT16D232(X) 5 3 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. OM53.pm Rev. 12/95 = 1995, Micron Technology, Inc. MM 6222549 0013572 T3L WINIS NV ileet To MT8D132(X), MT16D232(X) 1 MEG, 2 MEG x 32 DRAM MODULES EDO-PAGE-MODE READ CYCLE Vin CAS Vin Vit CAH appa yi COLUMN COLUMN ViL Vv be vet DON'T CARE RY] UNDEFINED WINIS WvHC i NOTE: 1. Although WE is a don't care at RAS time during an access cycle (READ or WRITE), the system designer should implement WE HIGH for WRP and 'WRH. This design implementation will facilitate compatibility with future EDO DRAMs, EDO PAGE MODE TIMING PARAMETERS 6 MAX UNITS ns 60 ns 30 ns ns . ns 100,000 ns 45 ns ns ns . ns ns ns ns ns SYM MT8D132(X}, MT18D232(X)} 5 32 Micron Technology, Inc., reserves the right to change products or specifications wilhaut notice. DM53.pm6 Rv. 12/95 = 1995, Micron Technology, Inc. MB 6131545 0013573 175MICRON MT8D132(X), MT16D232(X) 1 MEG, 2 MEG x 32 DRAM MODULES FAST-PAGE-MODE EARLY-WRITE CYCLE mas Ul oS it ADDR te COLUMN COLUMN COLUMN we uf BQ you VALID DATA VALID DATA VALID DATA DON'T CARE UNDEFINED FAST PAGE MODE TIMING PARAMETERS 6 7 . ; 6 7 SYM MIN MAX MAX UNITS SYM MIN MAX MIN MAX UNITS 45 ns 'RAD 15 30 15 35 ns 0 ns 'RAH 10 10 ns 0 , ns "RAL 30 35 ns 10 ns 'AASP 60 100,000| 70 100,000 ns 10,000 ns RCD 20 45 20 50 ns 10 ns tRP 40 50 ns 10 ns RSH 15 20 ns 60 : ns tRWL 15 20 ns 15 ns 'WCH 10 15 ns 10 ns 'WCR 45 55 ns 45 ns twWCS 0 0 ns 0 ns twp 10 15 ns 35 ns MT6D132(X), MT16D232(X} : 5- 3 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. DMS3.pm5 Rev. 12/95 @1995, Micron Fechnology, Inc. WH 6312549 0013574 304 me WIWIS NVdUG iWINIS NVHG i Nita a MT8D132(X), MT16D232(X) reomeei 1 MEG, 2 MEG x 32 DRAM MODULES Ras CAS ADDR EDO-PAGE-MODE EARLY-WRITE CYCLE Vin Vin Mn VIL Vin Vit COLUMN COLUMN we Ye pa yioH VALID DATA VALID DATA VALID DATA DON'T CARE Re UNDEFINED NOTE: 1. Although WE is a dont care at RAS time during an access cycle (READ or WRITE), the system designer should implement WE HIGH for 'WRP and 'WRH. This design implementation will facilitate compatibility with future EDO DRAMs. EDO PAGE MODE TIMING PARAMETERS SYM 6 . MAX | UNITS ns ns 100,000 | ns _ 45 10,000 MTED132(X), MT16D232(X) 5-34. Micron Technology, Inc., reserves the right to change products or specifications without notica. DM53.pm5 Rev. 12/95 61995, Micron Technology, Inc. MM 6111549 00133575 740ON MT8D132(X), MT16D232(X) Secon ha 1 MEG, y MEG X vd ae Wife} a] eT tS Nala EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE) tRASP trp mag VIH- , RAS vy L aa 'csH tec tee 'RSH tcrP treo tcas cp cas , top cas CP | r |__| as yf \ rN i ia tar TRAL 'RaD tack | fasr || tRAH tasc 'oaH ) tase || tCAH tasc_||_'GAH a rr s appr ya -ov VD COLUMN (A) Wh [ COLUMN (N) 4 ROW 0 t iwar || wR tacs oH] twes twou I y , -| t 7 We Vin- WEF val | tha K | > jl TAA _ t trac | CPA = * 'cac tps || to [cae ee 28 || 08 tcou tWHZ| a ~ v - + yo pa YIOH | VALID VALID DATA VioL OPEN 4 VALID DATA (A) DATA (B iN = V//\ DON'T CARE = RX} UNDEFINED NOTE: 1. Although WE is a dont care at RAS time during an access cycle (READ or WRITE), the system designer should implement WE HIGH for WRP and 'WRH. This design implementation will facilitate compatibility with future EDO DRAMs. EDO PAGE MODE TIMING PARAMETERS SYM MAX UNITS 60 ns 30 ns ns ns 100,000 ns 45 ns ns ns ns ns ns ns ns ns ns 17 10,000 MT8D132(X), MT16D232(X) 5 3 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DM53.pm5 Rav. 12/95 = 1995, Micron Technology, Inc. MB 6111549 0013576 47NEE RRP OM RL eerie 1 MEG, 2 MEG x 32 DRAM MODULES FAST-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE) Vv Ras vit eas IH CAS vit! tan RAL tase |. tasc toan Vv ADDR vit COLUMN COLUMN WINIS WWHa i We YS DQ vou > VALID DATA DON'T CARE NOTE: 1. Do not drive data prior to tristate. RY UNDEFINED FAST PAGE MODE TIMING PARAMETERS 6 7 , 6 7 SYM MAX MIN MAX UNITS SYM MIN MAX MIN MAX UNITS 30 35 ns IPC 35 40 ns ns TRAC 60 70 ns ns 'RAD 15 30 15 35 ns ns 'RAH 10 10 ns ns 'RAL 30 35 ns ns 'RASP 60 |100,000] 70 {100,000} ns ns RCD 20 45 20 50 ns ns 'RCS 0 0 ns ns tRP 40 50 ns ns 'RSH 15 20 , ns ns 'RWL 15 20 ns ns WCH 10 150 ns ns twcs 0 0 ns ns twp 10 15 ns ns MT8D132(X), MT16D232(xX} . 5 36 Micron Technology, Inc., reserves the right to change products or specifications withoul nolics. DMS53.pm5 Rev. 12/95. i @1995, Micron Technology, Inc. WM 6121549 0013577 513Ne tl MT8D132(X), MT16D232(X) costs 1 MEG, 2 MEG x 32 DRAM MODULES EDO READ CYCLE (with WE-controlled disable) VW ras vi > CAS) ViIH ~ VIL Vind ADDR Vit COLUMN COLUMN incs WE Vin Vit twuz toLz Vou De VoL = VALID DATA OPEN / : (//] DONT CARE R88 UNDEFINED NOTE: 1. Although WE is a dont care at RAS time during an access cycle (READ or WRITE), the system designer should implement WE HIGH for WRP and WRH. This design implementation will facilitate compatibility with future EDO DRAMs. EDO PAGE MODE TIMING PARAMETERS MT6D132(X}, MT16D232(X) Micron Technology, Inc., reserves the right to change products or specifications without notice. -37 MM 6121549 0013578 4ST WINIS NVHd iMT8D132(X), MT16D232(x) ad 1 MEG, 2 MEG x 32 DRAM MODULES RAS-ONLY REFRESH CYCLE 2 aoe (VIN - V, = cas yi > Oo 2 CBR REFRESH CYCLE 22 (Addresses = DONT CARE) = trp tras tre tras mas iH YL y N = t, 4 RPC, tg t mW I TTT % DP we UM ~~ DON'T CARE 8) UNDEFINED NOTE: 1. Although WE is a don't care at RAS time during an access cycle (READ or WRITE), the system designer should implement WE HIGH for 'WRP and WRH. This design implementation will facilitate compatibility with future EDO DRAMs. FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS 6 7 6 7 SYM : MIN MAX MIN MAX | UNITS SYM MIN MAX MIN MAX | UNITS 'ASR 0 0 ns RC 110 130 ns CHR - 10 10 ns 'RP 40 50 ns tcp 10 10 ns RPC (FPM) 0 0 ns CRP 10 10 ns 'RPC (EDO) 5 : = ns CSR 10 10 ns IWRH 10 10 ns tRAH 10 10 ns tWRP 10 10 ns RAS 60 | 10,000] 70 | 10,000] ns MT8D132(x), MT16D232(x) 5 3 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. DMS53,pms - Rav. 12/95 = 1995, Micron Technology, inc. MH 6111549 0013579 396MICRON MT8D132(X), MT16D232(X) 1 MEG, 2 MEG x 32 DRAM MODULES HIDDEN REFRESH CYCLE 27 (WE = HIGH) tras tap tras RAS Vi CAS Oy IH Vit taR tRap RAL tasc icaH ADDR vin, COLUMN TAA trac Da vou = VALID DATA OPEN DON'T CARE PRY) UNDEFINED FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS 6 7 6 1 SYM MAX MAX UNITS SYM MIN MAX MIN MAX UNITS 30 35 ns OFF 3 15 3 20 ns ns RAC . 60 70 ns ns TRAD 15 30 15 35 ns ns 'RAH 10 10 ns ns 'RAL 30 35 ns ns RAS 60 | 10,000} 70 | 10,000] ns ns ROD 20 45 20 50 ns ns 'RP 40 50 ns ns 'RSH 15 20 ns ns wrap T3208) , aT seD 28208) 5- 39 Micron Technology, Inc., reserves the right to change products os speciation thou noice, MB 6111549 0013580 008 WINIS NVC i