SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
1
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DRail-to-Rail Output Swing
DGain Bandwidth Product . . . 6.4 MHz
D±80 mA Output Drive Capability
DSupply Current . . . 500 µA/channel
DInput Offset Voltage . . . 100 µV
DInput Noise Voltage ...11 nV/√Hz
DSlew Rate . . . 1.6 V/µs
DMicropower Shutdown Mode
(TLV2460/3/5) . . . 0.3 µA/Channel
DUniversal Operational Amplifier EVM
DAvailable in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control/Print Support
Qualification to Automotive Standards
description
The TLV246x is a family of low-power rail-to-rail input/output operational amplifiers specifically designed for
portable applications. The input common-mode voltage range extends beyond the supply rails for maximum
dynamic range in low-voltage systems. The amplifier output has rail-to-rail performance with high-output-drive
capability, solving one of the limitations of older rail-to-rail input/output operational amplifiers. This rail-to-rail
dynamic range and high output drive make the TLV246x ideal for buffering analog-to-digital converters.
The operational amplifier has 6.4 MHz of bandwidth and 1.6 V/µs of slew rate with only 500 µA of supply current,
providing good ac performance with low power consumption. Three members of the family offer a shutdown
terminal, which places the amplifier in an ultralow supply current mode (IDD = 0.3 µA/ch). While in shutdown,
the operational-amplifier output is placed in a high-impedance state. DC applications are also well served with
an input noise voltage of 11 nV/√Hz and input offset voltage of 100 µV.
This family is available in the low-profile SOT23, MSOP, and TSSOP packages. The TLV2460 is the first
rail-to-rail input/output operational amplifier with shutdown available in the 6-pin SOT23, making it perfect for
high-density circuits. The family is specified over an expanded temperature range (TA = −40°C to 125°C) for
use in industrial control and automotive systems, and over the military temperature range
(TA = −55°C to 125°C) for use in military systems.
SELECTION GUIDE
DEVICE VDD
[V] VIO
[µV] IDD/ch
[µA] IIB
[pA] GBW
[MHz] SLEW RATE
[V/µs] Vn, 1 kHz
[nV/√Hz]IO
[mA] SHUTDOWN RAIL-RAIL
TLV246x(A) 2.7−6 150 550 1300 6.4 1.6 11 25 Y I/O
TLV277x(A) 2.5−5.5 360 1000 2 5.1 10.5 17 6 Y O
TLV247x(A) 2.7−6 250 600 2.5 2.8 1.5 15 20 Y I/O
TLV245x(A) 2.7−6 20 23 500 0.22 0.11 52 10 Y I/O
TLV225x(A) 2.7−8 200 35 1 0.2 0.12 19 3 — —
TLV226x(A) 2.7−8 300 200 1 0.71 0.55 12 3 — —
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0
$#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '1+ '+$%( #" +&( !('$*%+!'(
('&!/&$/ 2&$$&!'30 $#/*)'#! ,$#)+((!4 /#+( !#' !+)+((&$.3 !).*/+
'+('!4 #" &.. ,&$&%+'+$(0
Copyright 1998−2004, Texas Instruments Incorporated
3
2
4
6
(TOP VIEW)
1
OUT
GND
IN+
VDD+
IN−
TLV2460
DBV PACKAGE
5SHDN
! ,$#/*)'( )#%,.&!' '# 5 &.. ,&$&%+'+$( &$+ '+('+/
*!.+(( #'1+$2(+ !#'+/0 ! &.. #'1+$ ,$#/*)'( ,$#/*)'#!
,$#)+((!4 /#+( !#' !+)+((&$.3 !).*/+ '+('!4 #" &.. ,&$&%+'+$(0
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
2WWW.TI.COM
TLV2460C/I/AI and TLV2461C/I/AI AVAILABLE OPTIONS
VIOmax
PACKAGED DEVICES
TAVIOmax
AT 25°CSMALL OUTLINE
(D) SOT-23†
(DBV) SYMBOL PLASTIC DIP
(P)
0°C to 70°C2000 µVTLV2460CD
TLV2461CD TLV2460CDBV
TLV2461CDBV VAOC
VAPC TLV2460CP
TLV2461CP
−40°C to 125°C
2000 µVTLV2460ID
TLV2461ID TLV2460IDBV
TLV2461IDBV VAOI
VAPI TLV2460IP
TLV2461IP
−40
°
C to 125
°
C
1500 µVTLV2460AID
TLV2461AID —
——
—TLV2460AIP
TLV2461AIP
†This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2460CDR).
‡Chip forms are tested at TA = 25°C only.
TLV2460M/AM/Q/AQ and TLV2461M/AM/Q/AQ AVAILABLE OPTIONS
PACKAGED DEVICES
TAVIOmax
AT 25°CSMALL
OUTLINE†
(D)
SMALL
OUTLINE†
(PW)
CERAMIC DIP
(JG)
CERAMIC
FLATPACK
(U)
CHIP CARRIER
(FK)
−40°C to 125°C
2000 µVTLV2460QD
TLV2461QD TLV2460QPW
TLV2461QPW —
——
——
—
−40
°
C to 125
°
C
1500 µVTLV2460AQD
TLV2461AQD TLV2460AQPW
TLV2461AQPW —
——
——
—
−55°C to 125°C
2000 µV—
——
—TLV2460MJG
TLV2461MJG TLV2460MU
TLV2461MU TLV2460MFK
TLV2461MFK
−55°C to 125°C1500 µV—
——
—TLV2460AMJG
TLV2461AMJG TLV2460AMU
TLV2461AMU TLV2460AMFK
TLV2461AMFK
†This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2460QDR).
TLV2462C/I/AI and TLV2463C/I/AI AVAILABLE OPTIONS
PACKAGED DEVICES
TAVIOmax
AT 25°CSMALL
OUTLINE†
(D)
MSOP
(DGK) SYMBOL MSOP†
(DGS) SYMBOL PLASTIC DIP
(N) PLASTIC DIP
(P)
0°C to 70°C2000 µVTLV2462CD
TLV2463CD TLV2462CDGK
—xxTIAAI —
TLV2463CDGS —
xxTIAAK —
TLV2463CN TLV2462CP
—
−40°C to 2000 µVTLV2462ID
TLV2463ID TLV2462IDGK
—xxTIAAJ —
TLV2463IDGS —
xxTIAAL —
TLV2463IN TLV2462IP
—
−40 C to
125°C1500 µVTLV2462AID
TLV2463AID —
——
——
——
——
TLV2463AIN TLV2462AIP
—
†This package is available taped and reeled. To order this packaging option, add an R suf fix to the part number (e.g., TLV2462CDR).
‡Chip forms are tested at TA = 25°C only.
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
3
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TLV2462M/AM/Q/AQ and TLV2463M/AM/Q/AQ AVAILABLE OPTIONS
PACKAGED DEVICES
TAVIOmax
AT 25°CSMALL
OUTLINE†
(D)
SMALL
OUTLINE†
(PW)
CERAMIC DIP
(JG)
CERAMIC
DIP
(J)
CERAMIC
FLATPACK
(U)
CHIP CAR-
RIER
(FK)
−40°C to 125°C
2000 µVTLV2462QD
TLV2463QD TLV2462QPW
TLV2463QPW —
——
——
——
—
−40
°
C to 125
°
C
1500 µVTLV2462AQD
TLV2463AQD TLV2462AQPW
TLV2463AQPW —
——
——
——
—
−55°C to 125°C
2000 µV—
——
—TLV2462MJG
——
TLV2463MJ TLV2462MU TLV2462MFK
TLV2463MFK
−55°C to 125°C1500 µV—
——
—TLV2462AMJG
——
TLV2463AMJ TLV2462AMU TLV2462AMFK
TLV2463AMFK
†This package is available taped and reeled. To order this packaging option, add an R suf fix to the part number (e.g., TLV2462QDR).
TLV2464C/I/AI and TLV2465C/I/AI AVAILABLE OPTIONS
VIOmax
PACKAGED DEVICES
TAVIOmax
AT 25°CSMALL OUTLINE
(D) PLASTIC DIP
(N) TSSOP
(PW)
0°C to 70°C2000 µVTLV2464CD
TLV2465CD TLV2464CN
TLV2465CN TLV2464CPW
TLV2465CPW
−40°C to 125°C
2000 µVTLV2464ID
TLV2465ID TLV2464IN
TLV2465IN TLV2464IPW
TLV2465IPW
−40
°
C to 125
°
C
1500 µVTLV2464AID
TLV2465AID TLV2464AIN
TLV2465AIN TLV2464AIPW
TLV2465AIPW
†This package is available taped and reeled. To order this packaging option, add an R suffix to the part
number(e.g., TLV2464CDR).
‡Chip forms are tested at TA = 25°C only.
TLV2464M/AM/Q/AQ and TLV2465M/AM/Q/AQ AVAILABLE OPTIONS
PACKAGED DEVICES
TAVIOmax
AT 25°CSMALL
OUTLINE†
(D)
SMALL
OUTLINE†
(PW)
CERAMIC DIP
(J) CHIP CARRIER
(FK)
-40°C to 125°C
2000 µVTLV2464QD
TLV2465QD TLV2464QPW
TLV2465QPW —
——
—
-40
°
C to 125
°
C
1500 µVTLV2464AQD
TLV2465AQD TLV2464AQPW
TLV2465AQPW —
——
—
−55°C to 125°C
2000 µV—
——
—TLV2464MJ
TLV2465MJ TLV2464MFK
TLV2465MFK
−55°C to 125°C1500 µV—
——
—TLV2464AMJ
TLV2465AMJ TLV2464AMFK
TLV2465AMFK
†This package is available taped and reeled. To order this packaging option, add an R suffix to the part number
(e.g., TLV2464QDR).
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
4WWW.TI.COM
TLV246x PACKAGE PINOUTS(1)
1
2
3
4
5
10
9
8
7
6
1OUT
1IN−
1IN+
GND
1SHDN
VDD+
2OUT
2IN−
2IN+
2SHDN
3
2
4
5
(TOP VIEW)
1
OUT
GND
IN+
VDD+
IN−
TLV2461
DBV PACKAGE
3
2
4
6
(TOP VIEW)
1
OUT
GND
IN+
VDD+
IN−
TLV2460
DBV PACKAGE
5SHDN
TLV2463
DGS PACKAGE
(TOP VIEW)
NC − No internal connection
(1) SOT−23 may or may not be indicated
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
GND
NC
1SHDN
NC
VDD+
2OUT
2IN−
2IN+
NC
2SHDN
NC
(TOP VIEW)
TLV2463
D, N, J, OR PW PACKAGE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VDD+
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
(TOP VIEW)
TLV2464
D, N, PWP, J, OR PW PACKAGE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1OUT
1IN−
1IN+
VDD+
2IN+
2IN−
2OUT
1/2SHDN
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
3/4SHDN
(TOP VIEW)
TLV2465
D, N, PWP, J, OR PW PACKAGE
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
VDD+
2OUT
2IN−
2IN+
TLV2462
D, DGK, P, JG, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
SHDN
VDD+
OUT
NC
TLV2460
D, P, JG, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
NC
VDD+
OUT
NC
TLV2461
D, P, JG, OR PW PACKAGE
(TOP VIEW)
TYPICAL PIN 1 INDICATORS
Printed or
Molded Dot Bevel Edges
Pin 1
Molded ”U” Shape
Pin 1
Stripe Pin 1 Pin 1
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
5
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TLV246x PACKAGE PINOUTS (continued)(1)
1
2
3
4
5
10
9
8
7
6
NC
NC
IN−
IN+
GND
NC
SHDN
VDD
OUTPUT
NC
TLV2460
U PACKAGE
(TOP VIEW)
1
2
3
4
5
10
9
8
7
6
NC
1OUT
1IN−
1IN+
GND
NC
VDD+
2OUT
2IN−
2IN+
TLV2462
U PACKAGE
(TOP VIEW)
1
2
3
4
5
10
9
8
7
6
NC
NC
IN−
IN+
GND
NC
NC
VDD
OUTPUT
NC
TLV2461
U PACKAGE
(TOP VIEW)
1920132
17
18
16
15
14
1312119 10
5
4
6
7
8
NC
VDD
NC
OUT
NC
NC
IN−
NC
IN+
NC
NC
NC
NC
SHDN
NC
GND
NC
NC
NC
NC
TLV2460
FK PACKAGE
(TOP VIEW)
1920132
17
18
16
15
14
1312119 10
5
4
6
7
8
NC
VDD
NC
OUT
NC
NC
IN−
NC
IN+
NC
NC
NC
NC
NC
NC
GND
NC
NC
NC
NC
TLV2461
FK PACKAGE
(TOP VIEW)
1920132
17
18
16
15
14
1312119 10
5
4
6
7
8
2IN
−
NC
2IN
+
NC
NC
1IN+
NC
GND
NC
NC
1IN−
1OUT
NC
V
2OUT
NC
NC
NC
NC
NC
TLV2462
FK PACKAGE
(TOP VIEW)
DD
1920132
17
18
16
15
14
1312119 10
5
4
6
7
8
2IN−
NC
2IN+
NC
NC
1IN+
NC
GND
NC
NC
1IN−
1OUT
NC
V
2OUT
NC
NC
NC
2SHDN
1SHDN
TLV2463
FK PACKAGE
(TOP VIEW)
DD
TLV2464
FK PACKAGE
(TOP VIEW)
1920132
17
18
16
15
14
1312119 10
5
4
6
7
8
4IN+
NC
GND
NC
3IN+
1IN+
NC
VDD+
NC
2IN+
1IN−
1OUT
NC
4OUT
4IN−
2OUT
NC
3OUT
3IN−
2IN−
1920132
17
18
16
15
14
1312119 10
5
4
6
7
8
4IN+
GND
NC
3IN+
3IN−
1IN+
VDD+
NC
2IN+
2IN−
1IN−
1OUT
NC
4OUT
4IN−
1/2SHDN
NC
3/4SHDN
3OUT
2OUT
TLV2465
FK PACKAGE
(TOP VIEW)
NC − No internal connection
(1) SOT−23 may or may not be indicated
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
6WWW.TI.COM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID − 0.2 V to VDD + 0.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II (any input) ± 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO ± 175 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total input current, II (into VDD+) 175 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total output current, IO (out of GND) 175 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I and Q suffix −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M suffix −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE FOR C and I SUFFIX
PACKAGE
θ
JC
θ
JA
TA
≤
25
°
C
TA < 125
°
C
PACKAGE
θJC
(°C/W)
θJA
(°C/W)
TA ≤ 25 C
POWER RATING
TA < 125 C
POWER RATING
D (8) 38.3 176 710 mW 142 mW
D (14) 26.9 122.6 1022 mW 204.4 mW
D (16) 25.7 114.7 1090 mW 218 mW
DBV (5) 55 324.1 385 mW 77.1 mW
DBV (6) 55 294.3 425 mW 84.9 mW
DGK 54.2 259.9 481 mW 96.2 mW
DGS 54.1 257.7 485 mW 97 mW
N (14, 16) 32 78 1600 mW 320.5 mW
P (8) 41 104 1200 mW 240.4 mW
PW (14) 29.3 173.6 720 mW 144 mW
PW (16) 28.7 161.4 774 mW 154.9 mW
NOTE: Thermal resistances are not production tested and are for informational
purposes only.
DISSIPATION RATING TABLE FOR Q and M SUFFIX
PACKAGE
TA
≤
25
°
C
DERATING FACTOR
‡
TA = 70
°
C
TA = 85
°
C
TA = 125
°
C
PACKAGE
TA ≤ 25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C‡
TA = 70 C
POWER RATING
TA = 85 C
POWER RATING
TA = 125 C
POWER RATING
FK 1375 mW 11.0 mW/°C880 mW 715 mW 275 mW
JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW
U675 mW 5.4 mW/°C432 mW 350 mW 135 mW
‡This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA). Thermal resistances are not production tested and are for
informational purposes only.
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
7
WWW.TI.COM
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD
Single supply 2.7 6
V
Supply voltage, VDD Split supply ±1.35 ±3V
Common-mode input voltage range, VICR 0 VDD V
C-suffix 0 70
Operating free-air temperature, T
A
I-suffix and Q-suffix −40 125 °C
Operating free-air temperature, TA
M-suffix −55 125
C
Shutdown on/off voltage level‡
VIH 2
V
Shutdown on/off voltage level‡
VIL 0.7
V
‡Relative to voltage on the GND terminal of the device.
electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
V = 3 V,
25°C 500 2000
VIO
Input offset voltage
VDD = 3 V,
VIC = 1.5 V,
Full range 2200
V
VIO Input offset voltage
DD
VIC = 1.5 V,
VO = 1.5 V,
TLV246xA
25°C 500 1500 µV
VO = 1.5 V,
RS = 50
ΩTLV246xA Full range 1700
αVIO Temperature coef ficient of input offset voltage
RS = 50 Ω
2µV/°C
25°C 2.8 7
I
IO
Input offset current
VDD = 3 V,
TLV246xC Full range 20 nA
IIO
Input offset current
VDD = 3 V,
V
IC
= 1.5 V, TLV246xI/Q/M Full range 75
nA
VIC = 1.5 V,
VO = 1.5 V,
R = 50
25°C 4.4 14
I
IB
Input bias current
VO = 1.5 V,
RS = 50 ΩTLV246xC Full range 25 nA
IIB
Input bias current
TLV246xI/Q/M Full range 75
nA
IOH = −2.5 mA
25°C 2.9
VOH
High-level output voltage
IOH = −2.5 mA Full range 2.8
V
VOH High-level output voltage
IOH = −10 mA
25°C 2.7 V
IOH = −10 mA Full range 2.5
VIC = 1.5 V,
IOL = 2.5 mA
25°C 0.1
VOL
Low-level output voltage
VIC = 1.5 V, IOL = 2.5 mA Full range 0.2
V
VOL Low-level output voltage
VIC = 1.5 V,
IOL = 10 mA
25°C 0.3 V
VIC = 1.5 V, IOL = 10 mA Full range 0.5
Sourcing
25°C 50
IOS
Short-circuit output current
Sourcing Full range 20
mA
IOS Short-circuit output current
Sinking
25°C 40 mA
Sinking Full range 20
IOOutput current Measured 1 V from rail 25°C±40 mA
AVD
Large-signal differential voltage
RL = 10 kΩ
VO(PP) = 1 V
25°C 90 105
dB
AVD
Large-signal differential voltage
amplification RL = 10 kΩ, VO(PP) = 1 V Full range 89 dB
ri(d) Differential input resistance 25°C 109Ω
†Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
8WWW.TI.COM
electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
(continued)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
ci(c) Common-mode input
capacitance f = 10 kHz 25°C 7 pF
zoClosed-loop output impedance f = 100 kHz, AV = 10 25°C 33 Ω
VICR = 0 to 3 V,
25°C 66 80
CMRR Common-mode rejection ratio VICR = 0 to 3 V,
RS = 50 Ω
TLV246xC Full range 64 dB
CMRR
Common-mode rejection ratio
RS = 50 Ω
TLV246xI/Q/M Full range 60
dB
VDD = 2.7 V to 6 V,
VIC = VDD/2,
25°C 80 85
kSVR
Supply voltage rejection ratio
VDD = 2.7 V to 6 V,
No load
VIC = VDD/2,
Full range 75
dB
kSVR
Supply voltage rejection ratio
(∆VDD /∆VIO)
VDD = 3 V to 5 V,
VIC = VDD/2,
25°C 85 95 dB
( VDD / VIO)
VDD = 3 V to 5 V,
No load
VIC = VDD/2,
Full range 80
IDD
Supply current (per channels)
VO = 1.5 V,
No load
25°C 0.5 0.575
mA
IDD Supply current (per channels) VO = 1.5 V, No load Full range 0.9 mA
IDD(SHDN)
Supply current in shutdown
SHDN < 0.7 V,
25°C 0.3
A
IDD(SHDN
)
Supply current in shutdown
(TLV2460, TLV2463, TLV2465)
SHDN < 0.7 V,
Per channel in shutdown Full range 2.5 µA
†Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
operating characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VO(PP) = 0.8 V,
CL = 160 pF,
25°C0.9 1.6
SR Slew rate at unity gain VO(PP) = 0.8 V,
RL = 10 kΩCL = 160 pF, Full
range 0.8 V/µs
Vn
Equivalent input noise voltage
f = 100 Hz 25°C 16
nV/√Hz
VnEquivalent input noise voltage f = 1 kHz 25°C11
nV/√Hz
InEquivalent input noise current f = 1 kHz 25°C 0.13 pA/√Hz
Total harmonic distortion plus
VO(PP) = 2 V,
AV = 1 0.006%
THD + N Total harmonic distortion plus
noise
VO(PP) = 2 V,
RL = 10 kΩ, f = 1 kHz
AV = 10 25°C0.02%
THD + N
noise
RL = 10 kΩ, f = 1 kHz
AV = 100
25 C
0.08%
Both channels 7.6
t(on) Amplifier turnon time AV = 1, RL = 10 kΩChannel 1 only,
Channel 2 on 25°C7.65 µs
Both channels 333
t
(off)
Amplifier turnoff time A
V
= 1, R
L
= 10 kΩ
Channel 1 only,
Channel 2 on 25°C328 ns
t(off)
Amplifier turnoff time
AV = 1, RL = 10 kΩ
Channel 2 only,
Channel 1 on
25 C
329
ns
Gain-bandwidth product f = 10 kHz, CL = 160 pF RL = 10 kΩ,25°C 5.2 MHz
V(STEP)PP = 2 V,
AV = −1, CL = 10 pF,
0.1% 1.47
ts
Settling time
(STEP)PP
A
V
= −1, C
L
= 10 pF,
RL = 10 kΩ0.01%
25°C
1.78
s
tsSettling time V(STEP)PP = 2 V,
AV = −1, CL = 56 pF,
0.1% 25°C1.77 µs
(STEP)PP
A
V
= −1, C
L
= 56 pF,
RL = 10 kΩ0.01% 1.98
φmPhase margin at unity gain
RL = 10 kΩ,
CL = 160 pF
25°C 44°
Gain margin
R
L
= 10 k
Ω
,
C
L
= 160 pF
25°C 7 dB
†Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
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electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
25°C 500 2000
VIO
Input offset voltage
VDD = 5 V,
Full range 2200
V
VIO Input offset voltage
VDD = 5 V,
V
IC
= 2.5,
TLV246xA
25°C 500 1500 µV
VIC = 2.5,
VO = 2.5 V,
RS = 50 Ω
TLV246xA Full range 1700
VIO
Temperature coef ficient of input off-
O
RS = 50 Ω
25°C
2
V/°C
αVIO
Temperature coef ficient of input off-
set voltage 25°C 2 µV/°C
25°C 0.3 7
I
IO
Input offset current
VDD = 5 V,
TLV246xC Full range 15 nA
IIO
Input offset current
VDD = 5 V,
V
IC
= 2.5 V, TLV246xI/Q/M Full range 60
nA
VIC = 2.5 V,
VO = 2.5 V,
R = 50
25°C 1.3 14
I
IB
Input bias current
VO = 2.5 V,
RS = 50 ΩTLV246xC Full range 30 nA
IIB
Input bias current
TLV246xI/Q/M Full range 60
nA
IOH = −2.5 mA
25°C 4.9
VOH
High-level output voltage
IOH = −2.5 mA Full range 4.8
V
VOH High-level output voltage
IOH = −10 mA
25°C 4.8 V
IOH = −10 mA Full range 4.7
VIC = 2.5 V,
IOL = 2.5 mA
25°C 0.1
VOL
Low-level output voltage
VIC = 2.5 V, IOL = 2.5 mA Full range 0.2
V
VOL Low-level output voltage
VIC = 2.5 V,
IOL = 10 mA
25°C 0.2 V
VIC = 2.5 V, IOL = 10 mA Full range 0.3
Sourcing
25°C 145
IOS
Short-circuit output current
Sourcing Full range 60
mA
IOS Short-circuit output current
Sinking
25°C 100 mA
Sinking Full range 60
IOOutput current Measured at 1 V from rail 25°C±80 mA
AVD
Large-signal differential voltage
VIC = 2.5 V,
RL = 10 k
Ω
,
25°C 92 109
dB
AVD
Large-signal differential voltage
amplification
VIC = 2.5 V,
VO = 1 V to 4 V
RL = 10 kΩ,
Full range 90 dB
ri(d) Differential input resistance 25°C 109Ω
ci(c) Common-mode input capacitance f = 10 kHz 25°C 7 pF
zoClosed-loop output impedance f = 100 kHz, AV = 10 25°C 29 Ω
VICR = 0 V to 5 V,
25°C 71 85
CMRR Common-mode rejection ratio VICR = 0 V to 5 V,
RS = 50 Ω
TLV246xC Full range 69 dB
CMRR
Common-mode rejection ratio
RS = 50 Ω
TLV246xI/Q/M Full range 60
dB
VDD = 2.7 V to 6 V,
VIC = VDD/2,
25°C 80 85
dB
kSVR
Supply voltage rejection ratio
VDD = 2.7 V to 6 V,
No load
VIC = VDD/2,
Full range 75 dB
kSVR
Supply voltage rejection ratio
(∆VDD /∆VIO)
VDD = 3 V to 5 V,
VIC = VDD/2,
25°C 85 95
dB
( VDD / VIO)
VDD = 3 V to 5 V,
No load
VIC = VDD/2,
Full range 80 dB
IDD
Supply current (per channel)
VO = 2.5 V,
No load,
25°C 0.55 0.65
mA
IDD Supply current (per channel) VO = 2.5 V, No load, Full range 1mA
IDD(SHDN)
Supply current in shutdown
SHDN < 0.7 V, Per channels in
25°C 1
A
IDD(SHDN
)
Supply current in shutdown
(TLV2460, TLV2463, TLV2465)
SHDN < 0.7 V, Per channels in
shutdown Full range 3µA
†Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
10 WWW.TI.COM
operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VO(PP) = 2 V,
CL = 160 pF,
25°C0.9 1.6
SR Slew rate at unity gain VO(PP) = 2 V,
RL = 10 kΩCL = 160 pF, Full
range 0.8 V/µs
Vn
Equivalent input noise voltage
f = 100 Hz 25°C 14
nV/√Hz
VnEquivalent input noise voltage f = 1 kHz 25°C11
nV/√Hz
InEquivalent input noise current f = 100 Hz 25°C 0.13 pA/√Hz
VO(PP) = 4 V,
AV = 1 0.004%
THD + N Total harmonic distortion plus noise
VO(PP) = 4 V,
R
L
= 10 kΩ,
f = 10 kHz
AV = 10 25°C0.01%
THD + N
Total harmonic distortion plus noise
RL = 10 kΩ,
f = 10 kHz AV = 100
25 C
0.04%
Both channels 7.6
t
(on)
Amplifier turnon time A
V
= 1, R
L
= 10 kΩ
Channel 1 only,
Channel 2 on 25°C7.65 µs
t(on)
Amplifier turnon time
AV = 1, RL = 10 kΩ
Channel 2 only,
Channel 1 on
25 C
7.25
µs
Both channels 333
t
(off)
Amplifier turnoff time A
V
= 1, R
L
= 10 kΩ
Channel 1 only,
Channel 2 on 25°C328 ns
t(off)
Amplifier turnoff time
AV = 1, RL = 10 kΩ
Channel 2 only,
Channel 1 on
25 C
329
ns
Gain-bandwidth product f = 10 kHz,
CL = 160 pF RL = 10 kΩ,25°C 6.4 MHz
V(STEP)PP = 2 V,
AV = −1,
0.1% 1.53
ts
Settling time
AV = −1,
CL = 10 pF,
R
L
= 10 kΩ0.01%
25°C
1.83
s
tsSettling time V(STEP)PP = 2 V,
AV = −1,
0.1% 25°C3.13 µs
AV = −1,
CL = 56 pF,
R
L
= 10 kΩ0.01% 3.33
φmPhase margin at unity gain
RL = 10 kΩ,
CL = 160 pF
25°C 45°
Gain margin
R
L
= 10 k
Ω
,
C
L
= 160 pF
25°C 7 dB
†Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
11
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage vs Common-mode input voltage 1, 2
IIB Input bias current vs Free-air temperature 3, 4
IIO Input offset current vs Free-air temperature 3, 4
VOH High-level output voltage vs High-level output current 5, 6
VOL Low-level output voltage vs Low-level output current 7, 8
VO(PP) Peak-to-peak output voltage vs Frequency 9, 10
Open-loop gain vs Frequency 11, 12
Phase vs Frequency 11, 12
AVD Differential voltage amplification vs Load resistance 13
Capacitive load vs Load resistance 14
ZoOutput impedance vs Frequency 15, 16
CMRR Common-mode rejection ratio vs Frequency 17
kSVR Supply-voltage rejection ratio vs Frequency 18, 19
IDD
Supply current
vs Supply voltage 20
IDD Supply current vs Free-air temperature 21
Amplifier turnon characteristics 22
Amplifier turnoff characteristics 23
Supply current turnon 24
Supply current turnoff 25
Shutdown supply current vs Free-air temperature 26
SR Slew rate vs Supply voltage 27
Vn
Equivalent input noise voltage
vs Frequency 28, 29
V
n
Equivalent input noise voltage
vs Common-mode input voltage 30, 31
THD Total harmonic distortion vs Frequency 32, 33
THD+N Total harmonic distortion plus noise vs Peak-to-peak signal amplitude 34, 35
vs Frequency 11, 12
φ
m
Phase margin vs Load capacitance 36
φm
Phase margin
vs Free-air temperature 37
Gain bandwidth product
vs Supply voltage 38
Gain bandwidth product vs Free-air temperature 39
Large signal follower 40, 41
Small signal follower 42, 43
Inverting large signal 44, 45
Inverting small signal 46, 47
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
12 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 1
−0.2
−0.6
−1
0
−0.4
−0.8
1
VICR − Common-Mode Input Voltage − V
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
10.5 1.5 30 2 2.5
VDD = 3 V
TA = 25°C
− Input Offset Voltage − mV
VIO
0.8
0.4
0.6
0.2
Figure 2
−0.2
−0.6
−1
0
−0.4
−0.8
1
VICR − Common-Mode Input Voltage − V
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
213504
VDD = 5 V
TA = 25°C
− Input Offset Voltage − mV
VIO
0.8
0.4
0.6
0.2
Figure 3
TA − Free-Air Temperature − °C
INPUT BIAS AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
2.5
1.5
0.5
−0.5 −35 5
3
2
1
0
−15 25 125
4.5
−55 45 65
3.5
4
85 105
VDD = 3 V
VI = 1.5 V
IIB and I IO − Input Bias and Input Offset Current − nA
5
IIB
IIO
Figure 4
TA − Free-Air Temperature − °C
INPUT BIAS AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
−1 −35 5
3
2
1
0
−15 25 125−55 45 65
4
85 105
IIB and I IO − Input Bias and Input Offset Current − nA
5
IIB
IIO
VDD = 5 V
VI = 2.5 V
6
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
13
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TYPICAL CHARACTERISTICS
Figure 5
TA = 125°C
TA = 85°C
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0102030 60
IOH − High-Level Output Current − mA
5040 70 80
2.5
1
0
2
1.5
0.5
3
VOH− High-Level Output Voltage − V
VDD = 3 VDC
TA = −55°C
TA = 25°C
TA = −40°C
Figure 6
TA = 125°C
TA = 85°C
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0 20 40 60 120
IOH − High-Level Output Current − mA
10080 140 200
2.5
1
0
2
1.5
0.5
3
VOH− High-Level Output Voltage − V
VDD = 5 VDC
TA = −55°C
4
5
4.5
3.5
160 180
TA = 25°C
TA = −40°C
Figure 7
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0102030 60
IOL − Low-Level Output Current − mA
5040 70
2.5
1
0
2
1.5
0.5
3VDD = 3 VDC
TA = −55°C
OL
V − Low-Level Output Voltage − V
TA = 85°C
TA = 125°C
TA = 25°C
TA = −40°C
Figure 8
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0 204060 120
IOL − Low-Level Output Current − mA
10080 140
2.5
1
0
2
1.5
0.5
3
VDD = 5 VDC
4.5
4
3.5
160
OL
V − Low-Level Output Voltage − V
TA = −55°C
TA = 85°C
TA = 125°C
TA = 25°C
TA = −40°C
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
14 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 9
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
10k 100k 10M
f − Frequency − Hz
1M
3
2
1
0
2.5
1.5
0.5
VO(PP) − Peak-to-Peak Output Voltage − V
VDD = 3 V
AV = −10
THD = 1%
RL = 10 kΩ
Figure 10
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
10k 100k 10M
f − Frequency − Hz
1M
3
2
1
0
2.5
1.5
0.5
VO(PP) − Peak-to-Peak Output Voltage − V
VDD = 5 V
AV = −10
THD = 1%
RL = 10 kΩ
3.5
5
4
5.5
4.5
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
40
20
0
−20 100 10k
f − Frequency − Hz
50
30
10
−10
1k 100k 1M
60
80
10
70
90
−140°
−200°
−120°
−100°
−80°
100
−60°
−40°
−20°
0°
20°
40°
−180°
−160°
Open-Loop Gain − dB
Phase
10M
AVD
Phase
VDD = ±1.5 V
RL = 10 kΩ
CL = 0
TA = 25°C
Figure 11
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
15
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TYPICAL CHARACTERISTICS
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
40
20
0
−20 100 10k
f − Frequency − Hz
50
30
10
−10
1k 100k 1M
60
80
10
70
90
−140°
−200°
−120°
−100°
−80°
100
−60°
−40°
−20°
0°
20°
40°
−180°
−160°
Open-Loop Gain − dB
Phase
10M
AVD
Phase
VDD = ±2.5 V
RL = 10 kΩ
CL = 0
TA = 25°C
Figure 12
Figure 13
RL − Load Resistance − Ω
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
LOAD RESISTANCE
120
80
40
0
140
100
60
20
1k 10k 1M
180
100 100k
160 TA = 25°C
− Differential Voltage Amplification − V/mVAVD
VDD = ±2.5 V
VDD = ±1.5 V
Figure 14
CL− Capacitive Load − pF
CAPACITIVE LOAD
vs
LOAD RESISTANCE
10 100 10k
RL − Load Resistance − Ω
1k
10000
100
1000
Phase Margin > 30°
VDD = 5 V
Phase Margin = 30°
TA = 25°C
Phase Margin < 30°
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
16 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 15
OUTPUT IMPEDANCE
vs
FREQUENCY
f − Frequency − Hz
1
0.1
0.01
10
1000
AV = 100
100 1k 10k 10M1M100k
− Output Impedance −ZoΩ
100
VDD = ±1.5 V
TA = 25°C
AV = 10
AV = 1
Figure 16
OUTPUT IMPEDANCE
vs
FREQUENCY
f − Frequency − Hz
1
0.1
0.01
10
1000
AV = 100
100 1k 10k 10M1M100k
− Output Impedance −ZoΩ
100
VDD = ±2.5 V
TA = 25°C
AV = 10
AV = 1
CMRR − Common-Mode Rejection Ratio − dB
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
10 1k 10k 10M1M100k
90
80
70
60
85
75
65
VDD = 5 V
VIC = 2.5 V
100
VDD = 3 V
VIC = 1.5 V
Figure 17
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
17
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TYPICAL CHARACTERISTICS
Figure 18
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
10 1k 10k 10M1M100k
110
80
60
40
90
70
50
100
100 VDD = ±1.5 V
TA = 25°C
kSVR − Supply Voltage Rejection Ratio − dB
−kSVR
+kSVR
+kSVR
−kSVR
Figure 19
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
10 1k 10k 10M1M100k
80
60
40
90
70
50
100
VDD = ±2.5 V
TA = 25°C
kSVR − Supply Voltage Rejection Ratio − dB
−kSVR
+kSVR
+kSVR
−kSVR
Figure 20
VDD − Supply Voltage − V
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
0.7
0.5
0.30
0.10 34
0.8
0.6
0.40
0.20
3.5 4.5 62.5 5 5.5
IDD = 25°C
IDD − Supply Current − mA
IDD = 85°C
IDD = −55°C
IDD = 125°C
IDD = −40°C
Figure 21
TA − Free-Air Temperature − °C
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.60
0.50
0.40
0.30 −35 5
0.65
0.55
0.45
0.35
−15 25 125
0.80
−55 45 65
0.70
0.75
VDD = 5 V
VI = 2.5 V
85 105
IDD − Supply Current − mA
VDD = 3 V
VI = 1.5 V
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
18 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 22
t − Time − µs
AMPLIFIER WITH A SHUTDOWN PULSE
TURNON CHARACTERISTICS
2
0
2
0−3 1
1
3
1
−1 3 9
5
−5
V
57
SD − Shutdown Voltage − V
3
11
4
VDD = 5 V
RL = 10 kΩ
AV = 1
TA = 25°C
Shutdown Pin
Amplifier Output
Figure 23
t − Time − µs
AMPLIFIER WITH A SHUTDOWN PULSE
TURNOFF CHARACTERISTICS
2
0
2
0−3 1
1
3
1
−1 3
5
−5
V
57
SD − Shutdown Voltage − V
3
4VDD = 5 V
RL = 10 kΩ
AV = 1
TA = 25°C
Shutdown Pin
Amplifier Output
VDD = 5 V
VI = 2.5 V
AV = 1
TA = 25°C
0.4
−0.2
0.2
0
−0.4 −0.2 0 0.6
t − Time − µs0.40.2
SUPPLY CURRENT WITH A SHUTDOWN PULSE
TURNON CHARACTERISTICS
0.8
1
0.6
Supply Current
Shutdown Pin
IDD − Supply Current − mA
4.5
5.5
2.5
3.5
0.5
1.5
−0.5
VSD − Shutdown Voltage − V
Figure 24
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
19
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TYPICAL CHARACTERISTICS
VDD = 5 V
VI = 2.5 V
AV = 1
TA = 25°C
0.4
−0.2
0.2
0
−0.4 −0.2 0 0.6
t − Time − µs0.40.2
TURNOFF SUPPLY CURRENT
WITH A SHUTDOWN PULSE
0.8
1
0.6
Supply Current
Shutdown Pin
IDD − Supply Current − mA
4.5
5.5
2.5
3.5
0.5
1.5
−0.5
VSD − Shutdown Voltage − V
Figure 25
Figure 26
TA − Free-Air Temperature − °C
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
2.5
1.5
0.5
−0.5
−35 5
3
2
1
0
−15 25 125−55 45 65 85 105
VDD = 5 V
VI = 2.5 V
−1
DD
I Shutdown Supply Current − −Aµ
VDD = 3 V
VI = 1.5 V
Figure 27
VDD − Supply Voltage − V
SLEW RATE
vs
SUPPLY VOLTAGE
2.5 3 3.5 4 5.5 654.5
1.6
1.5
1.4
1.3
1.55
1.45
1.35
1.8
1.7
1.75
1.65
SR − Slew Rate − V/µs
VO(PP) = 2 V
CL = 160 pF
AV = 1
RL = 10 kΩ
TA = 25°C
SR+
SR−
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
20 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 28
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
100 1k 100k
f − Frequency − Hz
10k
10
14
12
15
13
11
17
18
16
nV/ Hz− Equivalent Input Noise Voltage −Vn
VDD = 3 V
AV = 10
VI = 1.5 V
TA = 25°C
Figure 29
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
100 1k 100k
f − Frequency − Hz
10k
10
14
12
15
13
11
17
18
16
nV/ Hz− Equivalent Input Noise Voltage −Vn
VDD = 5 V
AV = 10
VI = 2.5 V
TA = 25°C
Figure 30
VICR − Common-Mode Input Voltage − V
EQUIVALENT INPUT NOISE VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
12
10 1
14
13
11
0.5 1.5 3
20
02 2.5
15
VDD = 3 V
AV = 10
f = 1 kHz
TA = 25°C
nV/ Hz− Equivalent Input Noise Voltage −Vn
Figure 31
VICR − Common-Mode Input Voltage − V
EQUIVALENT INPUT NOISE VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
12
10 2
14
13
11
13
20
045
15
VDD = 5 V
AV = 10
f = 1 kHz
TA = 25°C
nV/ Hz− Equivalent Input Noise Voltage −Vn
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
21
WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 32
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0.010
0.001 100 10k
f − Frequency − Hz
1k 100
k
10
0.1
THD − Total Harmonic Distortion − %
VDD = ±1.5 V
VO(PP) = 2 V
RL = 10 kΩ
AV = 1
AV = 10
AV = 100
0.5
Figure 33
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0.010
0.001 100 10k
f − Frequency − Hz
1k 100k10
0.1
THD − Total Harmonic Distortion − %
VDD = ±2.5 V
VO(PP) = 4 V
RL = 10 kΩ
AV = 1
AV = 10
AV = 100
1
Figure 34
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
PEAK-TO-PEAK SIGNAL AMPLITUDE
0.010
0.001
0.1
THD+N − Total Harmonic Distortion + Noise − %
VDD = 3 V
AV = 1
TA = 25°C
1
RL = 10 kΩ
RL = 2 kΩ
RL = 250 Ω
RL = 100 kΩ
Peak-to-Peak Signal Amplitude − V
1 1.2 1.4 1.6 2.2 2.421.8 2.6 2.8 3 3.2
Figure 35
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
PEAK-TO-PEAK SIGNAL AMPLITUDE
0.010
0.001
0.1
THD+N − Total Harmonic Distortion + Noise − %
VDD = 5 V
AV = 1
TA = 25°C
1
RL = 10 kΩ
RL = 250 Ω
RL = 100 kΩ
Peak-to-Peak Signal Amplitude − V
4 4.1 4.2 4.3 4.6 4.74.54.4 4.8 4.9 5
RL = 2 kΩ
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
22 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 36
CL − Load Capacitance − pF
PHASE MARGIN
vs
LOAD CAPACITANCE
60
40
20
0
70
50
30
10
100 1k 100
k
90
10 10k
80
m
φ− Phase Margin − degrees
VDD = ±2.5 V
TA = 25°C
RL = 10 kΩ
Rnull = 50 Ω
Rnull = 20 Ω
Rnull = 0 Ω
Figure 37
TA − Free-Air Temperature − °C
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
60
50
40
30 −35 5
55
45
35
−15 25 125−55 45 65
RL = 10 kΩ
CL = 160 pF
85 105
VDD = ±2.5 V
VDD = ±1.5 V
m
φ− Phase Margin − degrees
Figure 38
VDD − Supply Voltage − V
GAIN BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
2.5 3 3.5 4 5.5 654.5
5
4.5
4
3.5
4.75
4.25
3.75
Gain Bandwidth Product − MHz
CL = 160 pF
RL = 10 kΩ
f = 10 kHz
TA = 25°C
Figure 39
TA − Free-Air Temperature − °C
GAIN BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
4.5
4
3.5
3−35 5
4.25
3.75
3.25
−15 25 125−55 45 65
RL = 10 kΩ
CL = 160 pF
85 105
VDD = ±2.5 V
VDD = ±1.5 V
5
4.75
Gain Bandwidth Product − MHz
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
23
WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 40
VO− Voltage − V
1.4
0.8
1.2
1
−2 0 2 4 10
t − Time − µs
861214
LARGE SIGNAL FOLLOWER
2.2
1.8
2
1.6
Input
Output
16 18
Output
Input
VDD = 3 V
VI(PP) = 1 V
VI = 1.5 V
RL = 10 kΩ
CL = 160 pF
AV = 1
TA = 25°C
Figure 41
VO− Voltage − V
2.1
1.7
1.3
−2 0 2 4 10
t − Time − µs
861214
LARGE SIGNAL FOLLOWER
3.7
2.9
3.3
2.5
Input
Output
16 18
Output
Input
VDD = 5 V
VI(PP) = 2 V
VI = 2.5 V
RL = 10 kΩ
CL = 160 pF
AV = 1
TA = 25°C
Figure 42
VO− Voltage − V
1.5
1.4
1.45
−0.2 0 0.2 0.4 1
t − Time − µs
0.80.6 1.2 1.4
SMALL SIGNAL FOLLOWER
1.6
1.55
Input
Output
1.6 1.8
VDD = 3 V
VI(PP) = 100 mV
VI = 1.5 V
RL = 10 kΩ
CL = 160 pF
AV = 1
TA = 25°C
Figure 43
VO− Voltage − V
2.5
2.4
2.45
−0.2 0 0.2 0.4 1
t − Time − µs
0.80.6 1.2 1.4
SMALL SIGNAL FOLLOWER
2.6
2.55
Input
Output
1.6 1.8
VDD = 5 V
VI(PP) = 100 mV
VI = 2.5 V
RL = 10 kΩ
CL = 160 pF
AV = 1
TA = 25°C
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
24 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 44
VO− Voltage − V
VDD = 3 V
VI(PP) = 1 V
VI = 1.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
1.1
0.5
0.9
0.7
−0.2 0 0.2 0.4 1
t − Time − µs
0.80.6 1.2 1.4
INVERTING LARGE SIGNAL
1.9
1.5
1.7
1.3
1.6 1.8
2.3
2.1 Input
Output
Figure 45
VDD = 5 V
VI(PP) = 2 V
VI = 2.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
2.5
1
2
1.5
−0.2 0 0.2 0.4 1
t − Time − µs
0.80.6 1.2 1.4
INVERTING LARGE SIGNAL
3.5
4
3
1.6 1.8
Input
Output
VO− Voltage − V
Figure 46
VO− Voltage − V
1.5
1.4
1.45
−0.2 0 0.2 0.4 1
t − Time − µs
0.80.6 1.2 1.4
INVERTING SMALL SIGNAL
1.6
1.55 Input
Output
1.6 1.8
VDD = 3 V
VI(PP) = 100 mV
VI = 1.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
Figure 47
VO− Voltage − V
2.5
2.4
2.45
−0.2 0 0.2 0.4 1
t − Time − µs
0.80.6 1.2 1.4
INVERTING SMALL SIGNAL
2.6
2.55 Input
Output
1.6 1.8
VDD = 5 V
VI(PP) = 100 mV
VI = 2.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
25
WWW.TI.COM
PARAMETER MEASUREMENT INFORMATION
_
+
Rnull
RLCL
Figure 48
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as
shown in Figure 49. A minimum value of 20 Ω should work well for most applications.
CLOAD
RF
Input Output
RGRNULL
_
+
Figure 49. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
VOO +VIOǒ1)ǒRF
RGǓǓ"IIB)RSǒ1)ǒRF
RGǓǓ"IIB– RF
+
−
VI+
RG
RS
RF
IIB−
VO
IIB+
Figure 50. Output Offset Voltage Model
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
26 WWW.TI.COM
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 51).
VIVO
C1
+
−
RGRF
R1
f–3dB +1
2pR1C1
VO
VI+ǒ1)RF
RGǓǒ1
1)sR1C1Ǔ
Figure 51. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
VI
C2
R2R1
C1
RF
RG
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
(
=1
Q
2 − )
RGRF
_
+f–3dB +1
2pRC
Figure 52. 2-Pole Low-Pass Sallen-Key Filter
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
27
WWW.TI.COM
APPLICATION INFORMATION
shutdown function
Three members of the TLV246x family (TLV2460/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.3 µA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to VDD/2.
Therefore, when operating the device with split supply voltages (e.g. ±2.5 V), the shutdown terminal needs to
be pulled to VDD− (not GND) to disable the operational amplifier.
The amplifier’s output with a shutdown pulse is shown in Figures 22, 23, 24, and 25. The amplifier is powered
with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon
and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output
waveform. The times for the single, dual, and quad are listed in the data tables.
circuit layout considerations
To achieve the levels of high performance o f the TLV246x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
DGround planes − It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
DProper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
DSockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
DShort trace runs/compact part placements − Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
DSurface-mount passive components − Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
28 WWW.TI.COM
APPLICATION INFORMATION
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 53 and is calculated by the following formula:
PD+ǒTMAX–TA
qJA Ǔ
Where: PD= Maximum power dissipation of THS246x IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
1
0.75
0.5
0
−55−40 −25 −10 5
Maximum Power Dissipation − W
1.25
1.5
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
1.75
20 35 50
0.25
TA − Free-Air Temperature − °C
2
65 80 95 110 125
MSOP Package
Low-K Test PCB
θJA = 260°C/W
TJ = 150°C
PDIP Package
Low-K Test PCB
θJA = 104°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
29
WWW.TI.COM
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 8, the model generation
software used with Microsim PSpice. The Boyle macromodel (see Note 2) and subcircuit in Figure 54 are
generated using the TLV246x typical electrical and operating characteristics at TA = 25°C. Using this
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
DMaximum positive output voltage swing
DMaximum negative output voltage swing
DSlew rate
DQuiescent power dissipation
DInput bias current
DOpen-loop voltage amplification
DUnity-gain frequency
DCommon-mode rejection ratio
DPhase margin
DDC output resistance
DAC output resistance
DShort-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers”, IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
+
−
+
−
+
−
+
−+
−
.SUBCKT TLV246X 1 2 3 4 5
C1 11 12 2.46034E−12
C2 6 7 10.0000E−12
CSS 10 99 443.21E−15
DC 5 53 DY
DE 54 5 DY
DLP 90 91 DX
DLN 92 90 DX
DP 43DX
EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5
FB 7 99 POLY (5) VB VC VE VLP
+ VLN 0 21.600E6 −1E3 1E3 22E6 −22E6
GA 6 0 11 12 345.26E−6
GCM 0 6 10 99 15.4226E−9
ISS 10 4 DC 18.850E−6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX1
J2 12 1 10 JX2
R2 6 9 100.00E3
RD1 3 11 2.8964E3
RD2 3 12 2.8964E3
R01 8 5 5.6000
R02 7 99 6.2000
RP 3 4 8.9127
RSS 10 99 10.610E6
VB 9 0 DC 0
VC 3 53 DC .7836
VE 54 4 DC .7436
VLIM 7 8 DC 0
VLP 91 0 DC 117
VLN 0 92 DC 117
.MODEL DX D (IS=800.00E−18)
.MODEL DY D (IS=800.00E−18 Rs = 1m Cjo=10p)
.MODEL JX1 NJF (IS=1.0000E−12 BETA=6.3239E−3
+ VTO=−1)
.MODEL JX2 NJF (IS=1.0000E−12 BETA=6.3239E−3
+ VTO=−1)
.ENDS
VDD+
RP
IN − 2
IN+ 1
GND
RD1
11
J1 J2
10
RSS
ISS
3
12
RD2
DP
VD
DC
4
C1
53
EGND FB
HLIM
90 DLP
91
DLN 92
VLNVLP
99
CSS
+
−
VE
DE
54
OUT
+
−
+
−
R2 6
9
VB
C2
GA
VLIM
8
5
RO1
RO2
7
GCM
Figure 54. Boyle Macromodels and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
30 WWW.TI.COM
macromodel information (continued)
.subckt TLV_246Y 1 2 3 4 5 6
c1 11 12 2.4603E−12
c2 72 7 10.000E−12
css 10 99 443.21E−15
dc 70 53 dy
de 54 70 dy
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0
21.600E6 −1E3 1E3 22E6 −22E6
ga 72 0 11 12 345.26E−6
gcm 0 72 10 99 15.422E−9
iss 74 4 dc 18.850E−6
hlim 90 0 vlim 1K
j1 11 2 10 jx1
j2 12 1 10 jx2
r2 72 9 100.00E3
rd1 3 11 2.8964E3
rd2 3 12 2.8964E3
ro1 8 70 5.6000
ro2 7 99 6.2000
rp 3 71 8.9127
rss 10 99 10.610E6
rs1 6 4 1G
rs2 6 4 1G
rs3 6 4 1G
rs4 6 4 1G
s1 71 4 6 4 s1x
s2 70 5 6 4 s1x
s3 10 74 6 4 s1x
s4 74 4 6 4 s2x
vb 9 0 dc 0
vc 3 53 dc .7836
ve 54 4 dc .7436
vlim 7 8 dc 0
vlp 91 0 dc 117
vln 0 92 dc 117
.model dx D(Is=800.00E−18)
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 NJF(Is=1.0000E−12 Beta=6.3239E−3 Vto=−1)
.model jx2 NJF(Is=1.0000E−12 Beta=6.3239E−3 Vto=−1)
.model s1x VSWITCH(Roff=1E8 Ron=1.0 Voff=2.5 Von=0.0)
.model s2x VSWITCH(Roff=1E8 Ron=1.0 Voff=0 Von=2.5)
.ends
Figure 54. Boyle Macromodels and Subcircuit (Continued)
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-0051201Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-0051201QHA ACTIVE CFP U 10 1 TBD A42 SNPB N / A for Pkg Type
5962-0051201QPA ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
5962-0051202Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-0051202QHA ACTIVE CFP U 10 1 TBD A42 SNPB N / A for Pkg Type
5962-0051202QPA ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
5962-0051203Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-0051203QHA ACTIVE CFP U 10 1 TBD A42 SNPB N / A for Pkg Type
5962-0051203QPA ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
5962-0051204Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-0051204QHA ACTIVE CFP U 10 1 TBD A42 SNPB N / A for Pkg Type
5962-0051204QPA ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
5962-0051205Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-0051205QHA ACTIVE CFP U 10 1 TBD A42 SNPB N / A for Pkg Type
5962-0051205QPA ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
5962-0051206Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-0051206QHA ACTIVE CFP U 10 1 TBD A42 SNPB N / A for Pkg Type
5962-0051206QPA ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
5962-0051207Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-0051207QCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
5962-0051208Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-0051208QCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
TLV2460AIDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460AIP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2460AIPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2460AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLV2460AMJG ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
TLV2460AMJGB ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
TLV2460AMUB ACTIVE CFP U 10 1 TBD A42 SNPB N / A for Pkg Type
TLV2460AQDR ACTIVE SOIC D 8 2500 TBD Call TI Call TI
TLV2460AQPW ACTIVE TSSOP PW 8 150 TBD Call TI Call TI
TLV2460AQPWR ACTIVE TSSOP PW 8 2000 TBD Call TI Call TI
TLV2460CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460CDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460CDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460CDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 7-May-2007
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
no Sb/Br)
TLV2460CDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460CDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460CDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460CP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2460CPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2460ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460IDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2460IPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2460MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLV2460MJG ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
TLV2460MJGB ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
TLV2460MUB ACTIVE CFP U 10 1 TBD A42 SNPB N / A for Pkg Type
TLV2460QD ACTIVE SOIC D 8 75 TBD Call TI Call TI
TLV2460QDR ACTIVE SOIC D 8 2500 TBD Call TI Call TI
TLV2460QPW ACTIVE TSSOP PW 8 150 TBD Call TI Call TI
TLV2460QPWR ACTIVE TSSOP PW 8 2000 TBD Call TI Call TI
TLV2461AID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461AIDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461AIDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461AIP ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 7-May-2007
Addendum-Page 2
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
(RoHS)
TLV2461AIPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2461AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLV2461AMJGB ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
TLV2461AMUB ACTIVE CFP U 10 1 TBD A42 SNPB N / A for Pkg Type
TLV2461AQD ACTIVE SOIC D 8 75 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2461AQDR ACTIVE SOIC D 8 2500 TBD Call TI Call TI
TLV2461AQPW ACTIVE TSSOP PW 8 TBD Call TI Call TI
TLV2461AQPWR ACTIVE TSSOP PW 8 2000 TBD Call TI Call TI
TLV2461CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461CDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461CDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461CDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461CDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461CDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461CP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2461CPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2461ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2461IPE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 7-May-2007
Addendum-Page 3
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
(RoHS)
TLV2461MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLV2461MJGB ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
TLV2461MUB ACTIVE CFP U 10 1 TBD A42 SNPB N / A for Pkg Type
TLV2461QD ACTIVE SOIC D 8 75 TBD Call TI Call TI
TLV2461QDR ACTIVE SOIC D 8 2500 TBD Call TI Call TI
TLV2461QPW ACTIVE TSSOP PW 8 TBD Call TI Call TI
TLV2461QPWR ACTIVE TSSOP PW 8 2000 TBD Call TI Call TI
TLV2462AID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462AIDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462AIDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462AIP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2462AIPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2462AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLV2462AMJG ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
TLV2462AMJGB ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
TLV2462AMUB ACTIVE CFP U 10 1 TBD A42 SNPB N / A for Pkg Type
TLV2462AQD ACTIVE SOIC D 8 75 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2462AQDR ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2462AQPWR ACTIVE TSSOP PW 8 2000 TBD CU NIPDAU Level-1-220C-UNLIM
TLV2462CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462CDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462CDGK ACTIVE MSOP DGK 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462CDGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462CDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462CDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462CDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462CP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2462CPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 7-May-2007
Addendum-Page 4
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV2462ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462IDGK ACTIVE MSOP DGK 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462IDGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462IDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462IDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2462IPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2462MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLV2462MJG ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
TLV2462MJGB ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
TLV2462MUB ACTIVE CFP U 10 1 TBD A42 SNPB N / A for Pkg Type
TLV2462QD ACTIVE SOIC D 8 75 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2462QDR ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2462QPW ACTIVE TSSOP PW 8 150 TBD CU NIPDAU Level-1-220C-UNLIM
TLV2462QPWR ACTIVE TSSOP PW 8 2000 TBD CU NIPDAU Level-1-220C-UNLIM
TLV2463AID ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463AIDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463AIDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463AIN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2463AINE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2463AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLV2463AMJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
TLV2463AMJB ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
TLV2463AQD ACTIVE SOIC D 14 50 TBD CU NIPDAU Level-1-220C-UNLIM
TLV2463AQDR ACTIVE SOIC D 14 75 TBD Call TI Call TI
TLV2463AQPWR ACTIVE TSSOP PW 14 2000 TBD CU NIPDAU Level-1-250C-UNLIM
TLV2463CD ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 7-May-2007
Addendum-Page 5
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
no Sb/Br)
TLV2463CDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463CDGS ACTIVE MSOP DGS 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463CDGSG4 ACTIVE MSOP DGS 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463CDGSR ACTIVE MSOP DGS 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463CDGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463CDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463CN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2463CNE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2463ID ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463IDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463IDGS ACTIVE MSOP DGS 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463IDGSG4 ACTIVE MSOP DGS 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463IDGSR ACTIVE MSOP DGS 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463IDGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463IN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2463INE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2463MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLV2463MJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
TLV2463MJB ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
TLV2463QD ACTIVE SOIC D 14 75 TBD CU NIPDAU Level-1-220C-UNLIM
TLV2463QDR ACTIVE SOIC D 14 2500 TBD Call TI Call TI
TLV2463QPWR ACTIVE TSSOP PW 14 2000 TBD CU NIPDAU Level-1-250C-UNLIM
TLV2464AID ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464AIDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464AIDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464AIN ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 7-May-2007
Addendum-Page 6
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
(RoHS)
TLV2464AINE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2464AIPW ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464AIPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464AIPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464CD ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464CDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464CDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464CN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2464CNE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2464CPW ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464CPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464CPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464ID ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464IDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464IDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464IN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2464INE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2464IPW ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 7-May-2007
Addendum-Page 7
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV2465AID ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465AIDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465AIPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465AIPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465CD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465CDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465CDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465CN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2465CNE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2465CPW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465CPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465CPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465ID ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465IDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465IDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465IN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2465INE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2465IPW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2465IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
PACKAGE OPTION ADDENDUM
www.ti.com 7-May-2007
Addendum-Page 8
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 7-May-2007
Addendum-Page 9
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
www.ti.com 7-May-2007
Pack Materials-Page 1
Device Package Pins Site Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2460AIDR D 8 TAI 330 12 6.4 5.2 2.1 8 12 Q1
TLV2460CDBVR DBV 6 LEN 180 9 3.15 3.2 1.4 4 8 NONE
TLV2460CDBVT DBV 6 LEN 180 9 3.15 3.2 1.4 4 8 NONE
TLV2460CDR D 8 TAI 330 12 6.4 5.2 2.1 8 12 Q1
TLV2460IDBVR DBV 6 LEN 180 9 3.15 3.2 1.4 4 8 NONE
TLV2460IDBVT DBV 6 LEN 180 9 3.15 3.2 1.4 4 8 NONE
TLV2460IDR D 8 TAI 330 12 6.4 5.2 2.1 8 12 Q1
TLV2461AIDR D 8 TAI 330 12 6.4 5.2 2.1 8 12 Q1
TLV2461CDBVR DBV 5 LEN 180 9 3.15 3.2 1.4 4 8 NONE
TLV2461CDBVT DBV 5 LEN 180 9 3.15 3.2 1.4 4 8 NONE
TLV2461CDR D 8 TAI 330 12 6.4 5.2 2.1 8 12 Q1
TLV2461IDBVR DBV 5 LEN 180 9 3.15 3.2 1.4 4 8 NONE
TLV2461IDBVT DBV 5 LEN 180 9 3.15 3.2 1.4 4 8 NONE
TLV2461IDR D 8 TAI 330 12 6.4 5.2 2.1 8 12 Q1
TLV2462AIDR D 8 TAI 330 12 6.4 5.2 2.1 8 12 Q1
TLV2462CDGKR DGK 8 HNT 330 8 5.3 3.4 1.4 8 12 NONE
TLV2462CDR D 8 TAI 330 12 6.4 5.2 2.1 8 12 Q1
TLV2462CDR D 8 FMX 330 0 6.4 5.2 2.1 8 12 Q1
TLV2462IDGKR DGK 8 HNT 330 8 5.3 3.4 1.4 8 12 NONE
TLV2462IDR D 8 TAI 330 12 6.4 5.2 2.1 8 12 Q1
TLV2463CDGSR DGS 10 HNT 330 8 5.3 3.4 1.4 8 12 NONE
TLV2463IDGSR DGS 10 HNT 330 8 5.3 3.4 1.4 8 12 NONE
TLV2464AIPWR PW 14 MLA 330 12 7.0 5.6 1.6 8 12 Q1
TLV2464CPWR PW 14 MLA 330 12 7.0 5.6 1.6 8 12 Q1
TLV2464IPWR PW 14 MLA 330 12 7.0 5.6 1.6 8 12 Q1
TLV2465AIPWR PW 16 MLA 330 12 7.0 5.6 1.6 8 12 Q1
TLV2465CPWR PW 16 MLA 330 12 7.0 5.6 1.6 8 12 Q1
TLV2465IPWR PW 16 MLA 330 12 7.0 5.6 1.6 8 12 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 7-May-2007
Pack Materials-Page 2
TAPE AND REEL BOX INFORMATION
Device Package Pins Site Length (mm) Width (mm) Height (mm)
TLV2460AIDR D 8 TAI 346.0 346.0 61.0
TLV2460CDBVR DBV 6 LEN 182.4 182.4 17.3
TLV2460CDBVT DBV 6 LEN 182.4 182.4 17.3
TLV2460CDR D 8 TAI 346.0 346.0 61.0
TLV2460IDBVR DBV 6 LEN 182.4 182.4 17.3
TLV2460IDBVT DBV 6 LEN 182.4 182.4 17.3
TLV2460IDR D 8 TAI 346.0 346.0 61.0
TLV2461AIDR D 8 TAI 346.0 346.0 61.0
TLV2461CDBVR DBV 5 LEN 182.4 182.4 17.3
TLV2461CDBVT DBV 5 LEN 182.4 182.4 17.3
TLV2461CDR D 8 TAI 346.0 346.0 61.0
TLV2461IDBVR DBV 5 LEN 182.4 182.4 17.3
TLV2461IDBVT DBV 5 LEN 182.4 182.4 17.3
TLV2461IDR D 8 TAI 346.0 346.0 61.0
TLV2462AIDR D 8 TAI 346.0 346.0 61.0
TLV2462CDGKR DGK 8 HNT 358.0 335.0 35.0
TLV2462CDR D 8 TAI 346.0 346.0 61.0
TLV2462CDR D 8 FMX 342.9 336.6 20.6
TLV2462IDGKR DGK 8 HNT 358.0 335.0 35.0
TLV2462IDR D 8 TAI 346.0 346.0 61.0
TLV2463CDGSR DGS 10 HNT 358.0 335.0 35.0
TLV2463IDGSR DGS 10 HNT 358.0 335.0 35.0
TLV2464AIPWR PW 14 MLA 342.9 336.6 20.6
TLV2464CPWR PW 14 MLA 342.9 336.6 20.6
TLV2464IPWR PW 14 MLA 342.9 336.6 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 7-May-2007
Pack Materials-Page 3
Device Package Pins Site Length (mm) Width (mm) Height (mm)
TLV2465AIPWR PW 16 MLA 342.9 336.6 20.6
TLV2465CPWR PW 16 MLA 342.9 336.6 20.6
TLV2465IPWR PW 16 MLA 342.9 336.6 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 7-May-2007
Pack Materials-Page 4
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE
8
4
0.015 (0,38)
Gage Plane
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
MAX
0.430 (10,92)
4040082/D 05/98
0.200 (5,08) MAX
0.125 (3,18) MIN
5
0.355 (9,02)
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.400 (10,60)
1
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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