ISPLSI 2128VE-180LTN176 - LATTICE SEMICONDUCTOR

ispLSI® 2128VE

3.3V In-System Programmable

SuperFAST™ High Density PLD

2128ve_12 1

Features

•SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

—6000 PLD Gates

—128 and 64 I/O Pin Versions, Eight Dedicated Inputs

—128 Registers

—High Speed Global Interconnect

—Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

—Small Logic Block Size for Random Logic

—100% Functional, JEDEC and Pinout Compatible

with ispLSI 2128V Devices

•3.3V LOW VOLTAGE 2128 ARCHITECTURE

—Interfaces with Standard 5V TTL Devices

•HIGH PERFORMANCE E2CMOS® TECHNOLOGY

—fmax = 250MHz Maximum Operating Frequency

—tpd = 4.0ns Propagation Delay

—Electrically Erasable and Reprogrammable

— Non-Volatile

—100% Tested at Time of Manufacture

—Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

—Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-

OR Bus Arbitration Logic

—Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

—Reprogram Soldered Devices for Faster Prototyping

•100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

•THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

—Enhanced Pin Locking Capability

—Three Dedicated Clock Input Pins

—Synchronous and Asynchronous Clocks

—Programmable Output Slew Rate Control

—Flexible Pin Placement

—Optimized Global Routing Pool Provides Global

Interconnectivity

•LEAD-FREE PACKAGE OPTIONS

Functional Block Diagram*

Description

The ispLSI 2128VE is a High Density Programmable

Logic Device available in 128 and 64 I/O-pin versions.

The device contains 128 Registers, eight Dedicated

Input pins, three Dedicated Clock Input pins, two dedi-

cated Global OE input pins and a Global Routing Pool

(GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 2128VE

features in-system programmability through the Bound-

ary Scan Test Access Port (TAP) and is 100% IEEE

1149.1 Boundary Scan Testable. The ispLSI 2128VE

offers non-volatile reprogrammability of the logic, as well

as the interconnect to provide truly reconfigurable sys-

tems.

The basic unit of logic on the ispLSI 2128VE device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. D7 (see Figure 1). There are a total of 32 GLBs in the

ispLSI 2128VE device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

Global Routing Pool (GRP)

Output Routing Pool (ORP) Output Routing Pool (ORP)

CLK 0

Output Routing Pool (ORP) Output Routing Pool (ORP)

CLK 1

CLK 2

Logic

Array GLB

0139A/2128V

D3 D2 D1 D0

D7 D6 D5 D4

B4 B5 B6 B7

B0 B1 B2 B3

*128 I/O Version Shown

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2004

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Lead-

Free

Package

Options

Available!

Specifications ispLSI 2128VE

Functional Block Diagram

Figure 1. ispLSI 2128VE Functional Block Diagram (128-I/O and 64-I/O Versions)

The 128-I/O 2128VE contains 128 I/O cells, while the 64-

I/O version contains 64 I/O cells. Each I/O cell is directly

connected to an I/O pin and can be individually pro-

grammed to be a combinatorial input, output or

bi-directional I/O pin with 3-state control. The signal

levels are TTL compatible voltages and the output drivers

can source 4mA or sink 8mA. Each output can be

programmed independently for fast or slow output slew

rate to minimize overall output switching noise. Device

pins can be safely driven to 5V signal levels to support

mixed-voltage systems.

Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and

two or one ORPs are connected together to make a

Megablock (see Figure 1). The outputs of the eight GLBs

are connected to a set of 32 or 16 universal I/O cells by

the two or one ORPs. Each ispLSI 2128VE device

contains four Megablocks.

The GRP has as its inputs, the outputs from all of the

GLBs and all of the inputs from the bi-directional I/O cells.

All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 2128VE device are selected using

the dedicated clock pins. Three dedicated clock pins (Y0,

Y1, Y2) or an asynchronous clock can be selected on a

GLB basis. The asynchronous or Product Term clock

can be generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the

outputs of the ispLSI 2128VE are individually program-

mable, either as a standard totem-pole output or an

open-drain output. The totem-pole output drives the

specified Voh and Vol levels, whereas the open-drain

output drives only the specified Vol. The Voh level on the

open-drain output depends on the external loading and

pull-up. This output configuration is controlled by a pro-

grammable fuse. The default configuration when the

device is in bulk erased state is totem-pole configuration.

The open-drain/totem-pole option is selectable through

the Lattice software tools.

Global

Routing

Pool

(GRP)

0139B/2128VE

Megablock

RESET

Input Bus

D3 D2 D1 D0

D7 D6 D5 D4

Output Routing Pool (ORP) Output Routing Pool (ORP)

I/O 127

I/O 126

I/O 125

I/O 124

I/O 123

I/O 122

I/O 121

I/O 120

I/O 119

I/O 118

I/O 117

I/O 116

I/O 115

I/O 114

I/O 113

I/O 112

I/O 111

I/O 110

I/O 109

I/O 108

I/O 107

I/O 106

I/O 105

I/O 104

I/O 103

I/O 102

I/O 101

I/O 100

I/O 99

I/O 98

I/O 97

I/O 96

IN 7

Output Routing Pool (ORP) Output Routing Pool (ORP)

Input Bus

IN 5

IN 4

I/O 91

I/O 90

I/O 89

I/O 88

I/O 87

I/O 86

I/O 85

I/O 84

I/O 83

I/O 82

I/O 81

I/O 80

I/O 79

I/O 78

I/O 77

I/O 76

I/O 75

I/O 74

I/O 73

I/O 72

I/O 71

I/O 70

I/O 69

I/O 68

I/O 67

I/O 66

I/O 65

I/O 64

I/O 95

I/O 94

I/O 93

I/O 92

Output Routing Pool (ORP) Output Routing Pool (ORP)

Input Bus

CLK 0

I/O 32

I/O 33

I/O 34

I/O 35

I/O 36

I/O 37

I/O 38

I/O 39

I/O 40

I/O 41

I/O 42

I/O 43

I/O 44

I/O 45

I/O 46

I/O 47

I/O 48

I/O 49

I/O 50

I/O 51

I/O 52

I/O 53

I/O 54

I/O 55

I/O 56

I/O 57

I/O 58

I/O 59

I/O 60

I/O 61

I/O 62

I/O 63

TDO/IN 2

TCK/IN 3

B4 B5 B6 B7

B0 B1 B2 B3

Output Routing Pool (ORP) Output Routing Pool (ORP)

BSCAN

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

I/O 0

I/O 1

I/O 2

I/O 3

GOE 0

GOE 1

CLK 1

CLK 2

Input Bus

TDI/IN 0

TMS/IN 1

IN 6

Generic Logic

Blocks (GLBs)

Global

Routing

Pool

(GRP)

0139B/2128VE.64IO

Megablock

RESET

Input Bus

D3 D2 D1 D0

D7 D6 D5 D4

Output Routing Pool (ORP)

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

IN 7*

Output Routing Pool (ORP)

Input Bus

IN 5*

IN 4*

I/O 43

I/O 42

I/O 41

I/O 40

I/O 39

I/O 38

I/O 37

I/O 36

I/O 35

I/O 34

I/O 33

I/O 32

I/O 47

I/O 46

I/O 45

I/O 44

Output Routing Pool (ORP)

Input Bus

CLK 0

TDO/IN 2

TCK/IN 3

B4 B5 B6 B7

B0 B1 B2 B3

Output Routing Pool (ORP)

BSCAN

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

I/O 0

I/O 1

I/O 2

I/O 3

GOE 0

GOE 1

CLK 1

CLK 2

Input Bus

TDI/IN 0

TMS/IN 1

*Not available on 84-PLCC Device

IN 6*

Generic Logic

Blocks (GLBs)

Specifications ispLSI 2128VE

Absolute Maximum Ratings 1

Supply Voltage Vcc .................................. -0.5 to +5.4V

Input Voltage Applied............................... -0.5 to +5.6V

Off-State Output Voltage Applied ............ -0.5 to +5.6V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125 °C

Max. Junction Temp. (TJ) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification

is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

Erase Reprogram Specifications

Capacitance (TA=25°C, f=1.0 MHz)

CSYMBOL

Table 2-0006/2128VE

PARAMETER

I/O Capacitance 6

UNITSTYPICAL TEST CONDITIONS

8Dedicated Input Capacitance pf

pf V = 3.3V, V = 0.0V

V = 3.3V, V = 0.0V

CC I/O

CClock and Global Output Enable Capacitance 10

pf V = 3.3V, V = 0.0V

CC Y

Table 2-0008/2128VE

PARAMETER MINIMUM MAXIMUM UNITS

Erase/Reprogram Cycles 10,000 – Cycles

TA = 0°C to + 70°C

TA = -40°C to + 85°C

SYMBOL

Table 2-0005/2128VE

VCC

VIH

VIL

PARAMETER

Supply Voltage

Input High Voltage

Input Low Voltage

MIN. MAX. UNITS

3.0

2.0

V – 0.5

3.6

5.25

0.8

Commercial

Industrial

Specifications ispLSI 2128VE

Switching Test Conditions

Figure 2. Test Load

Input Pulse Levels

Table 2 - 0003/2128VE

Input Rise and Fall Time

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

GND to 3.0V

≤ 1.5ns 10% to 90%

1.5V

See Figure 2

3-state levels are measured 0.5V from steady-state active level.

DC Electrical Characteristics

Over Recommended Operating Conditions

Output Load Conditions (see Figure 2)

TEST CONDITION R1 R2 CL

A 316Ω348Ω35pF

∞

348Ω35pF

316Ω348Ω35pF

Active High

Active Low

C316Ω348Ω5pF

∞

348Ω5pF

Active Low to Z

at V +0.5V

Active High to Z

at V -0.5V

Table 2-0004/2128VE

VOL

SYMBOL

1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test

problems by tester ground degradation. Characterized but not 100% tested.

2. Measured using eight 16-bit counters.

3. Typical values are at V = 3.3V and T = 25°C.

4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption

section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to

estimate maximum I .

Table 2-0007/2128VE

VOH

IIH

IIL

IIL-isp

PARAMETER

IIL-PU

IOS

2, 4

ICC

Output Low Voltage

Output High Voltage

Input or I/O High Leakage Current

Input or I/O Low Leakage Current

BSCAN Input Low Leakage Current

I/O Active Pull-Up Current

Output Short Circuit Current

Operating Power Supply Current

I = 8 mA

I = -4 mA

0V ≤ V ≤ V (Max.)

0V ≤ V ≤ V

V = 3.3V, V = 0.5V

V = 0.0V, V = 3.0V

f = 1 MHz

IN IL

CC OUT

CLOCK

IL IH

CONDITION MIN. TYP. MAX. UNITS

–

2.4

–

195

0.4

–

-10

-150

-100

–

µA

CC A

OUT

(V - 0.2)V ≤ V ≤ V

V ≤ V ≤ 5.25V

CC CC IN

+ 3.3V

R2CL*

Device

Output Test

Point

*CL includes Test Fixture and Probe Capacitance.

0213A/2128VE

Specifications ispLSI 2128VE

USE 2128VE-250

FOR NEW DESIGNS

External Timing Parameters

Over Recommended Operating Conditions

tpd1

UNITS

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.

2. Standard 16-bit counter using GRP feedback.

3. Reference Switching Test Conditions section.

Table 2-0030A/2128VE

v.1.0

tsu2 + tco1

( )

DESCRIPTION#PARAMETER

A1Data Propagation Delay, 4PT Bypass, ORP Bypass ns

tpd2 A2Data Propagation Delay ns

fmax A3Clock Frequency with Internal Feedback MHz

fmax (Ext.) –4Clock Frequency with External Feedback MHz

fmax (Tog.) –5Clock Frequency, Max. Toggle MHz

tsu1 –6GLB Reg. Setup Time before Clock, 4 PT Bypass ns

tco1 A7GLB Reg. Clock to Output Delay, ORP Bypass ns

th1 –8GLB Reg. Hold Time after Clock, 4 PT Bypass ns

tsu2 –9GLB Reg. Setup Time before Clock ns

tco2 A10GLB Reg. Clock to Output Delay ns

th2 –11GLB Reg. Hold Time after Clock ns

tr1 A12Ext. Reset Pin to Output Delay, ORP Bypass ns

trw1 –13Ext. Reset Pulse Duration ns

tptoeen B14Input to Output Enable ns

tptoedis C15Input to Output Disable ns

tgoeen B16Global OE Output Enable ns

tgoedis C17Global OE Output Disable ns

twh –18External Synchronous Clock Pulse Duration, High ns

twl –19External Synchronous Clock Pulse Duration, Low ns

-180

MIN. MAX.

– 5.0

–

180 –

–

0.0

4.5

–

0.0

–

4.0

–

2.5 –

125

200

3.5 3.5

–

4.5

–

7.0

–

10.0

5.0

7.5

-250

MIN. MAX.

– 4.0

–

250 –

–

0.0

3.3

–

0.0

–

3.5

–

1.8 –

158

277

2.5 3.0

–

3.7

–

6.0

–

6.0

4.0

6.0

Specifications ispLSI 2128VE

External Timing Parameters

Over Recommended Operating Conditions

tpd1

UNITS

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.

2. Standard 16-bit counter using GRP feedback.

3. Reference Switching Test Conditions section.

Table 2-0030B/2128VE

v.1.0

tsu2 + tco1

( )

DESCRIPTION#PARAMETER

A1Data Propagation Delay, 4PT Bypass, ORP Bypass ns

tpd2 A2Data Propagation Delay ns

fmax A3Clock Frequency with Internal Feedback MHz

fmax (Ext.) —4Clock Frequency with External Feedback MHz

fmax (Tog.) —5Clock Frequency, Max. Toggle MHz

tsu1 —6GLB Reg. Setup Time before Clock, 4 PT Bypass ns

tco1 A7GLB Reg. Clock to Output Delay, ORP Bypass ns

th1 —8GLB Reg. Hold Time after Clock, 4 PT Bypass ns

tsu2 —9GLB Reg. Setup Time before Clock ns

tco2 A10GLB Reg. Clock to Output Delay ns

th2 —11GLB Reg. Hold Time after Clock ns

tr1 A12Ext. Reset Pin to Output Delay, ORP Bypass ns

trw1 —13Ext. Reset Pulse Duration ns

tptoeen B14Input to Output Enable ns

tptoedis C15Input to Output Disable ns

tgoeen B16Global OE Output Enable ns

tgoedis C17Global OE Output Disable ns

twh —18External Synchronous Clock Pulse Duration, High ns

twl —19External Synchronous Clock Pulse Duration, Low ns

-135

MIN.

-100

MIN.MAX. MAX.

— 7.5 — 10.0

——

135 — 100 —

——

0.0 —

6.0 —

——

0.0 —

——

5.0 —

——

3.5 — —

100

143

5.0 4.0

—

5.0

—

9.0

—

12.0

7.0

10.0

100

6.5

0.0

8.0

0.0

6.5

5.0

13.0

5.0

6.0

12.5

15.0

9.0

Specifications ispLSI 2128VE

USE 2128VE-250 FOR NEW DESIGNS

Internal Timing Parameters1

Over Recommended Operating Conditions

tio

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

Table 2-0036A/2128VE

v.1.0

Inputs

UNITS

DESCRIPTION#2

PARAMETER

20 Input Buffer Delay ns

tdin 21 Dedicated Input Delay ns

tgrp 22 GRP Delay ns

GLB

t1ptxor 25 1 Product Term/XOR Path Delay ns

t20ptxor 26 20 Product Term/XOR Path Delay ns

txoradj 27 XOR Adjacent Path Delay ns

tgbp 28 GLB Register Bypass Delay ns

tgsu 29 GLB Register Setup Time before Clock ns

tgh 30 GLB Register Hold Time after Clock ns

tgco 31 GLB Register Clock to Output Delay ns

tgro 32 GLB Register Reset to Output Delay ns

tptre 33 GLB Product Term Reset to Register Delay ns

tptoe 34 GLB Product Term Output Enable to I/O Cell Delay ns

tptck 35 GLB Product Term Clock Delay ns

ORP

tob 38 Output Buffer Delay ns

tsl 39 Output Slew Limited Delay Adder ns

GRP

t4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) ns

t4ptbpr 24 4 Product Term Bypass Path Delay (Registered) ns

torp 36 ORP Delay ns

torpbp 37 ORP Bypass Delay ns

Outputs

toen 40 I/O Cell OE to Output Enabled ns

todis 41 I/O Cell OE to Output Disabled ns

tgoe 42 Global Output Enable ns

tgy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns

tgy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns

Clocks

tgr 45 Global Reset to GLB

-180

MIN. MAX.

0.5

1.1

0.6

3.4

0.0

—

0.3

0.6

4.3

5.9

4.0

1.6

2.0

1.9

2.4

1.4

0.4

3.0

2.0

1.2

1.4

4.4

—

1.2

2.3

—

1.0

—

1.2

1.4

—

-250

MIN. MAX.

0.5

0.7

0.2

2.8

0.0

—

0.2

0.3

3.7

2.9

3.6

1.4

2.0

1.5

2.0

1.1

0.4

2.4

1.6

1.0

1.2

3.9

—

0.8

1.7

—

0.8

—

1.0

1.2

—ns

Global Reset

Specifications ispLSI 2128VE

Internal Timing Parameters1

Over Recommended Operating Conditions

tio

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

Table 2-0036B/2128VE

v.1.0

Inputs

UNITS

DESCRIPTION#2

PARAMETER

20 Input Buffer Delay ns

tdin 21 Dedicated Input Delay ns

tgrp 22 GRP Delay ns

GLB

t1ptxor 25 1 Product Term/XOR Path Delay ns

t20ptxor 26 20 Product Term/XOR Path Delay ns

txoradj 27 XOR Adjacent Path Delay ns

tgbp 28 GLB Register Bypass Delay ns

tgsu 29 GLB Register Setup Time before Clock ns

tgh 30 GLB Register Hold Time after Clock ns

tgco 31 GLB Register Clock to Output Delay ns

tgro 32 GLB Register Reset to Output Delay ns

tptre 33 GLB Product Term Reset to Register Delay ns

tptoe 34 GLB Product Term Output Enable to I/O Cell Delay ns

tptck 35 GLB Product Term Clock Delay ns

ORP

tob 38 Output Buffer Delay ns

tsl 39 Output Slew Limited Delay Adder ns

GRP

t4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) ns

t4ptbpr 24 4 Product Term Bypass Path Delay (Registered) ns

torp 36 ORP Delay ns

torpbp 37 ORP Bypass Delay ns

Outputs

toen 40 I/O Cell OE to Output Enabled ns

todis 41 I/O Cell OE to Output Disabled ns

tgoe 42 Global Output Enable ns

tgy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns

tgy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns

Clocks

tgr 45 Global Reset to GLB ns

Global Reset

-135

MIN.

-100

MIN.MAX. MAX.

—

1.7

4.8

—

2.6

—

2.4

2.6

—

0.7

2.5

1.8

6.2

1.0

—

0.3

3.1

7.1

9.1

5.6

1.6

2.0

5.2

4.7

1.7

0.7

3.4

5.6

2.4

2.6

7.1

0.5

1.7

1.2

4.7

0.5

—

0.3

1.1

6.1

6.9

4.6

1.6

2.0

3.7

1.5

0.5

3.4

3.6

1.6

1.8

5.8

—

1.2

3.8

—

1.6

—

1.6

1.8

—

Specifications ispLSI 2128VE

ispLSI 2128VE Timing Model

GLB Reg

Delay

I/O Pin

(Output)

ORP

Delay

Feedback

Reg 4 PT Bypass

20 PT

XOR Delays

Control

PTs

I/O Pin

(Input)

Y0,1,2

GRP GLB Reg Bypass ORP Bypass

RST

I/O Delay

I/O CellORPGLBGRPI/O Cell

#24

#25, 26, 27

#33, 34,

#43, 44

#36

Reset

Ded. In #21

#20 #28

#29, 30,

31, 32

#38,

GOE 0 #42

#40, 41

0491/2032

#22

Comb 4 PT Bypass #23

#37

#45

Derivations of

su,

h and

co from the Product Term Clock

2.8ns

Logic + Reg su - Clock (min)

(

io +

grp +

20ptxor) + (

gsu) - (

io +

grp +

ptck(min))

(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)

(0.5 + 0.2 + 2.8) + (0.8) - (0.5 + 0.2 + 0.8)

hClock (max) + Reg h - Logic

(

io +

grp +

ptck(max)) + (

gh) - (

io +

grp +

20ptxor)

(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)

(0.5 + 0.2 + 3.6) + (1.7) - (0.5 + 0.2 + 2.8)

Note: Calculations are based upon timing specifications for the ispLSI 2128VE-250L.

Clock (max) + Reg co + Output

(

io +

grp +

ptck(max)) + (

gco) + (

orp +

ob)

(#20 + #22 + #35) + (#31) + (#36 + #38)

(0.5 + 0.2 + 3.6) + (0.2) + (1.1 + 1.4)

Table 2-0042/2128VE

v.1.0

2.5ns

7.0ns

Specifications ispLSI 2128VE

Power Consumption

Power consumption in the ispLSI 2128VE device de-

pends on two primary factors: the speed at which the

device is operating and the number of Product Terms

used. Figure 3 shows the relationship between power

and operating speed.

Figure 3. Typical Device Power Consumption vs fmax

0127/2128VE

ICC can be estimated for the ispLSI 2128VE using the following equation:

ICC = 8 + (# of PTs * 0.669) + (# of nets * max freq * 0.0026)

Where:

# of PTs = Number of Product Terms used in design

# of nets = Number of Signals used in device

Max freq = Highest Clock Frequency to the device (in MHz)

The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption

of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is

sensitive to operating conditions and the program in the device, the actual ICC should be verified.

150

100

250

050100 150 200 250

fmax (MHz)

ICC (mA)

Notes: Configuration of eight 16-bit counters

Typical current at 3.3V, 25¡ C

300

350

200

ispLSI 2128VE

Specifications ispLSI 2128VE

Signal Descriptions

RESET Active Low (0) Reset pin resets all the registers in the device.

GOE 0, GOE1 Global Output Enable input pins.

Y0, Y1, Y2 Dedicated Clock Input – These clock inputs are connected to one of the clock inputs of all the GLBs in

the device.

BSCAN Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to

enable the programming mode. The TMS, TDI, TDO and TCK controls become active.

TDI/IN 0 Input – This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin

to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin.

TCK/IN 3 Input – This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the

Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin.

TMS/IN 1 Input – This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for

the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin.

TDO/IN 2 Output/Input – This pin performs two functions. When BSCAN is logic low, it functions as an output pin

to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin.

IN 4 - IN 7 Dedicated Input Pins to the device.

GND Ground (GND)

VCC Vcc

NC1No Connect

I/O Input/Output Pins – These are the general purpose I/O pins used by the logic array.

Signal Name Description

1. NC pins are not to be connected to any active signals, VCC or GND.

Specifications ispLSI 2128VE

Signal Locations

langiS llaB-802 AGBpfAGBpf AGBpf AGBpfAGBpf niP-671 PFQTPFQT PFQT PFQTPFQT niP-061 PFQPPFQP PFQP PFQPPFQP llaB-001 AGBacAGBac AGBac AGBacAGBac niP-001 PFQTPFQT PFQT PFQTPFQT

TESER 3H12912D11

1EOG,0EOG1H,61J32,01112,0011E,9F31,26

2Y,1Y,0Y41J,41H,2H801,311,0289,301,818F,6F,3E06,56,01

NACSB 1J52325E51

0NI/IDT3J62422F61

3NI/KCT51J7017901G95

1NI/SMT8P66065J73

2NI/ODT9C4510416B78

7NI-4NI,8T,9A,61H4H ,76,551,41191 ,16,141,40171 1D,5K,6A,9E9,83,88,66

DNG,7G,31D,4D ,01G,9G,8G ,9H,8H,7H ,8J,7J,01H ,7K,01J,9J ,01K,9K,8K 31N,4N

,78,86,64,42 ,351,431,901 571

,97,26,24,22 ,931,221,99 951

6K,9G,1F,7B68,16,93,41

CCV,21D,6D,5D ,4F,31E,4E ,31L,4L,31F ,5N,31M,4M 21N,11N

,56,34,22,2 ,131,111,09 651

,95,93,02,2 ,911,101,28 241

4J,01F,2E,5A98,36,63,21

,51A,3A,2A ,2B,1B,61A ,51B,41B,3B ,3C,2C,61B ,41D,51C,41C ,3P,2P,1P ,51P,41P,31P ,3R,2R,1R ,61R,51R,41R ,51T,2T,1T 61T

,63,72,81,9 ,87,96,46,55 ,211,601,79 ,341,421,511 661,751,251

201,4C,3C,8A ,7E,8D,6D ,3G,4F,01E 3K,8H,7H,5G

,13,52,12,4 ,46,45,05,44 ,49,18,57,17 001

.DNGroCCV,slangisevitcaynaotdetcennocebottonerasnipCN.1

Specifications ispLSI 2128VE

I/O Locations

I/O 0 J2 28 25 G1 17

I/O 1 J4 29 26 F3 18

I/O 2 K1 30 27 E4 19

I/O 3 K3 31 28 H1 20

I/O 4 K2 32 29 G2 22

I/O 5 K4 33 30 J1 23

I/O 6 L1 34 31 H 2 24

I/O 7 L2 35 32 K1 26

I/O 8 L3 37 33 J2 27

I/O 9 M1 38 34 K2 28

I/O 10 M2 39 35 H3 29

I/O 11 M3 40 36 J3 30

I/O 12 N1 41 37 G4 32

I/O 13 N2 42 38 H4 33

I/O 14 N3 44 40 K4 34

I/O 15 P4 45 41 H5 35

I/O 16 T3 47 43 F5 40

I/O 17 R4 48 44 J6 41

I/O 18 T4 49 45 K7 42

I/O 19 P5 50 46 H6 43

I/O 20 R5 51 47 K8 45

I/O 21 N6 52 48 G6 46

I/O 22 T5 53 49 J7 47

I/O 23 R6 54 50 K9 48

I/O 24 P6 56 51 J8 49

I/O 25 T6 57 52 K10 51

I/O 26 N7 58 53 J9 52

I/O 27 R7 59 54 J10 53

I/O 28 P7 60 55 H9 55

I/O 29 T7 61 56 H10 56

I/O 30 N8 62 57 G7 57

I/O 31 R8 63 58 G8 58

I/O 32 T9 70 63 D10 67

I/O 33 P9 71 64 E8 68

I/O 34 R9 72 65 F7 69

I/O 35 N9 73 66 C10 70

I/O 36 T10 74 67 D9 72

I/O 37 P10 75 68 B10 73

I/O 38 R10 76 69 C9 74

I/O 39 N10 77 70 A10 76

I/O 40 T11 79 71 B9 77

I/O 41 P11 80 72 A9 78

I/O 42 R11 81 73 C8 79

I/O 43 T12 82 74 B8 80

I/O 44 P12 83 75 D7 82

I/O 45 R12 84 76 C7 83

I/O 46 T13 85 77 A7 84

I/O 47 R13 86 78 C6 85

I/O 48 T14 88 80 E6 90

I/O 49 N14 89 81 B5 91

I/O 50 P16 91 83 A4 92

I/O 51 N15 92 84 C5 93

I/O 52 N16 93 85 A3 95

I/O 53 M14 94 86 D5 96

I/O 54 M15 95 87 B4 97

I/O 55 M16 96 88 A2 98

I/O 56 L15 98 89 B3 99

I/O 57 L14 99 90 A1 1

I/O 58 L16 100 91 B2 2

I/O 59 K13 101 92 B1 3

I/O 60 K15 102 93 C2 5

I/O 61 K14 103 94 C1 6

I/O 62 K16 104 95 D4 7

I/O 63 J13 105 96 D3 8

208 176 160 100 100

Signal fpBGA TQFP PQFP caBGA TQFP

I/O 64 H15 116 105 — —

I/O 65 H13 117 106 — —

I/O 66 G16 118 107 — —

I/O 67 G14 119 108 — —

I/O 68 G15 120 109 — —

I/O 69 G13 121 110 — —

I/O 70 F16 122 111 — —

I/O 71 F14 123 112 — —

I/O 72 F15 125 113 — —

I/O 73 E16 126 114 — —

I/O 74 E14 127 115 — —

I/O 75 E15 128 116 — —

I/O 76 D16 129 117 — —

I/O 77 C16 130 118 — —

I/O 78 D15 132 120 — —

I/O 79 A14 133 121 — —

I/O 80 C13 135 123 — —

I/O 81 B13 136 124 — —

I/O 82 A13 137 125 — —

I/O 83 C12 138 126 — —

I/O 84 B12 139 127 — —

I/O 85 D11 140 128 — —

I/O 86 A12 141 129 — —

I/O 87 C11 142 130 — —

I/O 88 B11 144 131 — —

I/O 89 D10 145 132 — —

I/O 90 A11 146 133 — —

I/O 91 B10 147 134 — —

I/O 92 C10 148 135 — —

I/O 93 D9 149 136 — —

I/O 94 A10 150 137 — —

I/O 95 B9 151 138 — —

I/O 96 A8 158 143 — —

I/O 97 C8 159 144 — —

I/O 98 B8 160 145 — —

I/O 99 D8 161 146 — —

I/O 100 A7 162 147 — —

I/O 101 C7 163 148 — —

I/O 102 B7 164 149 — —

I/O 103 D7 165 150 — —

I/O 104 A6 167 151 — —

I/O 105 C6 168 152 — —

I/O 106 B6 169 153 — —

I/O 107 A5 170 154 — —

I/O 108 C5 171 155 — —

I/O 109 B5 172 156 — —

I/O 110 A4 173 157 — —

I/O 111 B4 174 158 — —

I/O 112 C4 176 160 — —

I/O 113 A1 1 1 — —

I/O 114 C1 3 3 — —

I/O 115 D3 4 4 — —

I/O 116 D2 5 5 — —

I/O 117 D1 6 6 — —

I/O 118 E3 7 7 — —

I/O 119 E2 8 8 — —

I/O 120 E1 10 9 — —

I/O 121 F3 11 10 — —

I/O 122 F2 12 11 — —

I/O 123 F1 13 12 — —

I/O 124 G4 14 13 — —

I/O 125 G2 15 14 — —

I/O 126 G3 16 15 — —

I/O 127 G1 17 16 — —

208 176 160 100 100

Signal fpBGA TQFP PQFP caBGA TQFP

Specifications ispLSI 2128VE

Signal Configuration

ispLSI 2128VE 208-Ball fpBGA Signal Diagram

GNDVCC

VCC

GND

GND GND GND GND

VCC

GNDVCCVCCVCCGND

VCC

IN 5

IN 4

VCC

GOE

0TCK/

IN 3

I/O

79 I/O

82 I/O

86 I/O

90 I/O

94 I/O

96 I/O

100 I/O

104 I/O

107 I/O

110

I/O

111

I/O

109

I/O

106

I/O

102

I/O

73 I/O

75 I/O

VCC

I/O

70 I/O

72 I/O

I/O

66 I/O

I/O

64 I/O

I/O

58 I/O

56 I/O

VCC

I/O

55 I/O

54 I/O

I/O

52 I/O

51 I/O

I/O

48 I/O

46 I/O

43 I/O

40 I/O

36 I/O

32 I/O

29 I/O

25 I/O

22 I/O

I/O

47 I/O

45 I/O

42 I/O

38 I/O

34 I/O

31 I/O

27 I/O

23 I/O

20 I/O

I/O

60 I/O

61 I/O

I/O

67 I/O

I/O

80 I/O

83 I/O

87 I/O

TDO/

IN 2 I/O

101

I/O

103

I/O

105 I/O

108 I/O

112 I/O

114

I/O

117

I/O

116

I/O

115

I/O

120

I/O

119

I/O

118

VCC

IN 7 Y0

IN 6

I/O

50 I/O

41 I/O

37 I/O

33 TMS/

IN 1 I/O

28 I/O

I/O

39 I/O

35 I/O

30 I/O

26 I/O

I/O

19 I/O

BSCAN

RESET

I/O

123

I/O

122

I/O

121

I/O

127

GOE

I/O

125

I/O

126

I/O

124

I/O

1TDI/

IN 0 I/O

I/O

113

12345678910111213141516

1. NCs are not to be connected to any active signals, Vcc or GND.

Note: Ball A1 indicator dot on top side of package.

208 BGA/2128VE

ispLSI 2128VE

Bottom View

Specifications ispLSI 2128VE

Pin Configuration

ispLSI 2128VE 176-Pin TQFP Pinout Diagram

ispLSI 2128VE

Top View

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

I/O 113

VCC

I/O 114

I/O 115

I/O 116

I/O 117

I/O 118

I/O 119

I/O 120

I/O 121

I/O 122

I/O 123

I/O 124

I/O 125

I/O 126

I/O 127

IN 7

RESET

VCC

GOE 1

GND

BSCAN

TDI/IN 0

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

VCC

I/O 14

I/O 112

GND

I/O 111

I/O 110

I/O 109

I/O 108

I/O 107

I/O 106

I/O 105

I/O 104

I/O 103

I/O 102

I/O 101

I/O 100

I/O 99

I/O 98

I/O 97

I/O 96

VCC

IN 5

TDO/IN 2

GND

I/O 95

I/O 94

I/O 93

I/O 92

I/O 91

I/O 90

I/O 89

I/O 88

I/O 87

I/O 86

I/O 85

I/O 84

I/O 83

I/O 82

I/O 81

I/O 80

GND

I/O 79

I/O 78

VCC

I/O 77

I/O 76

I/O 75

I/O 74

I/O 73

I/O 72

I/O 71

I/O 70

I/O 69

I/O 68

I/O 67

I/O 66

I/O 65

I/O 64

IN 4

VCC

GOE 0

GND

TCK/IN 3

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

VCC

I/O 49

I/O 15

GND

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

VCC

TMS/IN 1

IN 6

GND

I/O 32

I/O 33

I/O 34

I/O 35

I/O 36

I/O 37

I/O 38

I/O 39

I/O 40

I/O 41

I/O 42

I/O 43

I/O 44

I/O 45

I/O 46

I/O 47

GND

I/O 48

176-TQFP/2128VE

1. NC pins are not to be connected to any active signals, VCC or GND.

Specifications ispLSI 2128VE

Pin Configuration

ispLSI 2128VE 160-Pin PQFP Pinout Diagram

ispLSI 2128VE

Top View

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

I/O 113

VCC

I/O 114

I/O 115

I/O 116

I/O 117

I/O 118

I/O 119

I/O 120

I/O 121

I/O 122

I/O 123

I/O 124

I/O 125

I/O 126

I/O 127

IN 7

RESET

VCC

GOE 1

GND

BSCAN

TDI/IN 0

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

VCC

I/O 14

I/O 112

GND

I/O 111

I/O 110

I/O 109

I/O 108

I/O 107

I/O 106

I/O 105

I/O 104

I/O 103

I/O 102

I/O 101

I/O 100

I/O 99

I/O 98

I/O 97

I/O 96

VCC

IN 5

TDO/IN 2

GND

I/O 95

I/O 94

I/O 93

I/O 92

I/O 91

I/O 90

I/O 89

I/O 88

I/O 87

I/O 86

I/O 85

I/O 84

I/O 83

I/O 82

I/O 81

I/O 80

GND

I/O 79

I/O 78

VCC

I/O 77

I/O 76

I/O 75

I/O 74

I/O 73

I/O 72

I/O 71

I/O 70

I/O 69

I/O 68

I/O 67

I/O 66

I/O 65

I/O 64

IN 4

NC1

VCC

GOE 0

GND

TCK/IN 3

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

VCC

I/O 49

I/O 15

GND

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

VCC

TMS/IN 1

IN 6

GND

I/O 32

I/O 34

I/O 35

I/O 36

I/O 37

I/O 38

I/O 39

I/O 40

I/O 41

I/O 42

I/O 43

I/O 44

I/O 45

I/O 46

I/O 47

GND

I/O 48

1. NC pins are not to be connected to any active signal, VCC or GND.

160-PQFP/2128VE

Specifications ispLSI 2128VE

Signal Configuration

ispLSI 2128VE 100-Ball caBGA Signal Diagram

10 987654321

I/O

39 I/O

41 I/O

46 I/O

50 I/O

52 I/O

55 I/O

IN 5 VCC

I/O

35 I/O

38 I/O

42 I/O

45 I/O

47 I/O

51 I/O

60 I/O

TCK/

IN 3 I/O

31 I/O

30 I/O

21 I/O

12 I/O

4I/O

GND NC

I/O

29 I/O

28 I/O

19 I/O

13 I/O

I/O

15 I/O

6I/O

I/O

27 I/O

26 I/O

24 I/O

22 I/O

17 I/O

TMS/

IN 1 I/O

8I/O

VCC

I/O

NCs are not to be connected to any active signals, VCC or GND.

Note: Ball A1 indicator dot on top side of package.

I/O

23 I/O

20 I/O

18 I/O

14 I/O

9I/O

GND NC

IN 6

GOE

0I/O

34 I/O

16 I/O

1TDI/

IN 0

GND

100-BGA/2128VE

VCC Y2 Y1

I/O

32 I/O

36 I/O

44 I/O

53 I/O

62 I/O

IN 7NC

RESET

I/O

33 I/O

48 I/O

2GOE

VCCY0IN 4 NC

1BSCAN

I/O

37 I/O

40 I/O

43 I/O

I/O

TDO/

IN 2 I/O

56 I/O

58 I/O

GND

ispLSI 2128VE

Bottom View

Specifications ispLSI 2128VE

Pin Configuration

ispLSI 2128VE 100-Pin TQFP Pinout Diagram

I/O 57

I/O 58

I/O 59

I/O 60

I/O 61

I/O 62

I/O 63

IN 7

RESET

VCC

GOE 1

GND

BSCAN

TDI/IN 0

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 38

I/O 37

I/O 36

I/O 35

I/O 34

I/O 33

I/O 32

IN 4

VCC

GOE 0

GND

TCK/IN 3

I/O 31

I/O 30

I/O 29

I/O 28

I/O 27

I/O 26

I/O 25

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

VCC

IN 5

TDO/IN 2

GND

I/O 47

I/O 46

I/O 45

I/O 44

I/O 43

I/O 42

I/O 41

I/O 40

I/O 39

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

VCC

TMS/IN 1

IN 6

GND

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

100

ispLSI 2128VE

Top View

1. NC pins are not to be connected to any active signals, VCC or GND.

100-TQFP/2128VE

Specifications ispLSI 2128VE

Part Number Description

ispLSI 2128VE Ordering Information

Conventional Packaging

COMMERCIAL

180

176-Pin TQFP5.0

5.0

ispLSI 2128VE-180LT176*

160-Pin PQFPispLSI 2128VE-180LQ160*

Table 2-0041A/2128VE

135 7.5 100-Pin TQFPispLSI 2128VE-135LT100

FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)

ispLSI

128

180 5.0 208-Ball fpBGAispLSI 2128VE-180LB208*128

250

250 176-Pin TQFP4.0

4.0 ispLSI 2128VE-250LT176 160-Pin PQFPispLSI 2128VE-250LQ160

128

250 4.0 208-Ball fpBGAispLSI 2128VE-250LB208128

180 100-Pin TQFP5.0 ispLSI 2128VE-180LT100*64

180 5.0 100-Ball caBGAispLSI 2128VE-180LB100*64

250 100-Pin TQFP4.0 ispLSI 2128VE-250LT10064

250 4.0 100-Ball caBGAispLSI 2128VE-250LB10064

I/Os

135 100-Ball caBGA7.5 ispLSI 2128VE-135LB10064

135 7.5 176-Pin TQFPispLSI 2128VE-135LT176128

135 160-Pin PQFP7.5 ispLSI 2128VE-135LQ160128

135 208-Ball fpBGA7.5 ispLSI 2128VE-135LB208128

100 100-Pin TQFP10 ispLSI 2128VE-100LT10064

100 10 100-Ball caBGAispLSI 2128VE-100LB10064

100

100 176-Pin TQFP10

10 ispLSI 2128VE-100LT176 160-Pin PQFPispLSI 2128VE-100LQ160

128

100 10 208-Ball fpBGAispLSI 2128VE-100LB208

128

*Use ispLSI 2128VE-250 for new designs

Device Number

ispLSI 2128VE XXX XXXXXX

Grade

Blank = Commercial

I = Industrial

Speed

250 = 250 MHz

max

180 = 180 MHz

max*

135 = 135 MHz

max

100 = 100 MHz

max

*Use ispLSI 2128VE-250 for new designs

Package

–

Device Family

0212/2128VE

Q160 = 160-Pin PQFP

T176 = 176-Pin TQFP

TN176 = Lead-Free 176-Pin TQFP

B208 = 208-Ball fpBGA

BN208 = Lead-Free 208-Ball fpBGA

T100 = 100-Pin TQFP

TN100 = Lead-Free 100-Pin TQFP

B100 = 100-Ball caBGA

Power

L = Low

Specifications ispLSI 2128VE

INDUSTRIAL

135 100-Pin TQFP7.5 ispLSI 2128VE-135LT100I

Table 2-0041B/2128VE

FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)

ispLSI 64

135 176-Pin TQFP7.5 ispLSI 2128VE-135LT176I128

I/Os

ispLSI 2128VE Ordering Information (Cont.)

Conventional Packaging (Cont.)

Lead-Free Packaging

COMMERCIAL

135

100

Lead-Free 100-Pin TQFP7.5

ispLSI 2128VE-135LTN100

Lead-Free 176-Pin TQFPispLSI 2128VE-100LTN176

FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)

ispLSI

128

100 10 Lead-Free 208-Ball fpBGAispLSI 2128VE-100LBN208128

250

250 Lead-Free 176-Pin TQFP4.0

4.0 ispLSI 2128VE-250LTN176 Lead-Free 208-Ball fpBGAispLSI 2128VE-250LBN208

128

250 4.0 Lead-Free 100-Pin TQFPispLSI 2128VE-250LTN10064

100 Lead-Free 100-Pin TQFP10 ispLSI 2128VE-100LTN10064

135 Lead-Free 176-Pin TQFP7.5 ispLSI 2128VE-135LTN176128

135 7.5 Lead-Free 208-Ball fpBGAispLSI 2128VE-135LBN208128

I/Os

INDUSTRIAL

135 Lead-Free 176-Pin TQFP7.5 ispLSI 2128VE-135LTN176I

FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)

ispLSI 128

135 Lead-Free 100-Pin TQFP7.5 ispLSI 2128VE-135LTN100I64

I/Os