SN54LVC138A, SN74LVC138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS291I – MARCH 1993 – REVISED OCT OBER 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
D
Inputs Accept Voltages to 5.5 V
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flat (W) Package, and DIPs (J)
description
The SN54LVC138A 3-line to 8-line decoder/
demultiplexer is designed for 2.7-V to 3.6-V VCC
operation and the SN74LVC138A 3-line to 8-line
decoder/demultiplexer is designed for 1.65-V to
3.6-V VCC operation.
The ’LVC138A devices are designed for high-
performance memory-decoding or data-routing
applications requiring very short propagation
delay times. In high-performance memory systems, these decoders minimize the effects of system decoding.
When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and
the enable time of the memory are usually less than the typical access time of the memory. This means that
the effective system delay introduced by the decoders is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires
only one inverter. An enable input can be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN54LVC138A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVC138A is characterized for operation from –40°C to 85°C.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
B
C
G2A
G2B
G1
Y7
GND
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
SN54LVC138A ...J OR W PACKAGE
SN74LVC138A . . . D, DB, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
Y1
Y2
NC
Y3
Y4
C
G2A
NC
G2B
G1
B
A
NC
Y6
Y5 V
Y0
Y7
GND
NC
SN54LVC138A . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LVC138A, SN74LVC138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS291I – MARCH 1993 – REVISED OCT OBER 1998
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
ENABLE INPUTS SELECT INPUTS OUTPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X X H H H H H H H H
XXHXXXHHHHHHHH
LXXXXXHHHHHHHH
HLLLLLLHHHHHHH
HLLLLHHLHHHHHH
HLLLHLHHLHHHHH
HLLLHHHHHLHHHH
HLLHLLHHHHLHHH
HLLHLHHHHHHLHH
HLLHHLHHHHHHLH
HLLHHHHHHHHHHL
logic symbols (alternatives)†
BIN/OCT
1
1
A
2
2
B
4
3
C
4
5
6
G1
Y0
15
0
&
EN
Y1
14
1
Y2
13
2
Y3
12
3
Y4
11
4
Y5
10
5
Y6
9
6
Y7
7
7
DMUX
0
1
A2
B
2
3
C
4
5
6
G1
Y0
15
0
&
Y1
14
1
Y2
13
2
Y3
12
3
Y4
11
4
Y5
10
5
Y6
9
6
Y7
7
7
G7
0
G2A
G2B
G2A
G2B
†These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, PW , and W packages.
SN54LVC138A, SN74LVC138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS291I – MARCH 1993 – REVISED OCT OBER 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
G2B
G2A
G1
C
B
A
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data
Outputs
Select
Inputs
Enable
Inputs
1
2
3
6
4
5
15
14
13
12
11
10
9
7
Pin numbers shown are for the D, DB, J, PW , and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
SN54LVC138A, SN74LVC138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS291I – MARCH 1993 – REVISED OCT OBER 1998
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54LVC138A SN74LVC138A
UNIT
MIN MAX MIN MAX
UNIT
VCC
Su
pp
ly voltage
Operating 2 3.6 1.65 3.6
V
V
CC
S
u
ppl
y v
oltage
Data retention only 1.5 1.5
V
VCC = 1.65 V to 1.95 V 0.65 ×VCC
VIH High-level input voltage VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 2 2
VCC = 1.65 V to 1.95 V 0.35 ×VCC
VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 V
VCC = 2.7 V to 3.6 V 0.8 0.8
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
VCC = 1.65 V –4
IOH
High level out
p
ut current
VCC = 2.3 V –8
mA
I
OH
High
-
le
v
el
o
u
tp
u
t
c
u
rrent
VCC = 2.7 V –12 –12
mA
VCC = 3 V –24 –24
VCC = 1.65 V 4
IOL
Low level out
p
ut current
VCC = 2.3 V 8
mA
I
OL
Lo
w-
le
v
el
o
u
tp
u
t
c
u
rrent
VCC = 2.7 V 12 12
mA
VCC = 3 V 24 24
∆t/∆vInput transition rise or fall rate 0 10 0 10 ns/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
SN54LVC138A, SN74LVC138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS291I – MARCH 1993 – REVISED OCT OBER 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
SN54LVC138A SN74LVC138A
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP†MAX MIN TYP†MAX
UNIT
IOH = 100 µA
1.65 V to 3.6 V VCC–0.2
I
OH = –
100
µ
A
2.7 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
VOH IOH = –8 mA 2.3 V 1.7 V
IOH =12mA
2.7 V 2.2 2.2
I
OH = –
12
mA
3 V 2.4 2.4
IOH = –24 mA 3 V 2.2 2.2
IOL = 100 µA
1.65 V to 3.6 V 0.2
I
OL =
100
µ
A
2.7 V to 3.6 V 0.2
VOL
IOL = 4 mA 1.65 V 0.45
V
V
OL IOL = 8 mA 2.3 V 0.7
V
IOL = 12 mA 2.7 V 0.4 0.4
IOL = 24 mA 3 V 0.55 0.55
IIVI = 5.5 V or GND 3.6 V ±5±5µA
ICC VI = VCC or GND, IO = 0 3.6 V 10 10 µA
∆ICC One input at VCC – 0.6 V,
Other inputs at VCC or GND 2.7 V to 3.6 V 500 500 µA
CiVI = VCC or GND 3.3 V 5 5 pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
SN54LVC138A
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 2.7 V VCC = 3.3 V
± 0.3 V UNIT
MIN MAX MIN MAX
A or B or C 7.9 1 6.7
tpd G2A or G2B Y7.4 1 6.5 ns
G1 6.4 1 5.8
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
SN74LVC138A
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 1.8 V VCC = 2.5 V
± 0.2 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V UNIT
TYP MIN MAX MIN MAX MIN MAX
A or B or C 15.9 1 9.9 7.9 1 6.7
tpd G2A or G2B Y15.4 1 9.4 7.4 1 6.5 ns
G1 14.4 1 8.4 6.4 1 5.8
tsk(o)‡1ns
‡Skew between any two outputs of the same package switching in the same direction
SN54LVC138A, SN74LVC138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS291I – MARCH 1993 – REVISED OCT OBER 1998
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, TA = 25°C
PARAMETER
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
UNIT
PARAMETER
CONDITIONS TYP TYP TYP
UNIT
Cpd Power dissipation capacitance f = 10 MHz 25 26 27 pF
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
1 kΩ
1 kΩ
Output
Control
(low-level
enabling)
Output
W aveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at Open
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 1. Load Circuit and Voltage Waveforms
SN54LVC138A, SN74LVC138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS291I – MARCH 1993 – REVISED OCT OBER 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
W aveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 2. Load Circuit and Voltage Waveforms
SN54LVC138A, SN74LVC138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS291I – MARCH 1993 – REVISED OCT OBER 1998
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
VOH
VOL
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 6 V
Open
GND
500 Ω
500 Ω
tPLH tPHL
Output
Control
(low-level
enabling)
Output
W aveform 1
S1 at 6 V
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
1.5 V 1.5 V 2.7 V
0 V
1.5 V 1.5 V VOH
VOL
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
0 V
1.5 V 2.7 V
0 V
1.5 V 1.5 V 0 V
2.7 V
0 V
1.5 V 1.5 V
tw
Input
2.7 V 2.7 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
