AM29SL160CB-120 - Advanced Micro Devices

Publication Number 21635 Revision CAmendment +3 Issue Date November 1, 2004

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-

inally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order

these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Am29SL160C

Data Sheet

2 Am29SL160C November 1, 2004

ADVANCE INFORMATION

THIS PAGE LEFT INTENTIONALLY BLANK.

This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may

be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 21635 Rev: CAmendment/+3

Issue Date: November 1, 2004

Refer to AMD’s Website (www.amd.com) for the latest information.

Am29SL160C

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)

CMOS 1.8 Volt-only Super Low Voltage Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■Secured Silicon (SecSi) Sector: 256-byte sector

—Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function. ExpressFlash option allows entire sector to

be available for factory-secured data

—Customer lockable: Customer may program own

custom data. Once locked, data cannot be changed

■Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero

■Package options

— 48-ball FBGA

— 48-pin TSOP

■Top or bottom boot block

■Manufactured on 0.32 µm process technology

■Compatible with JEDEC standards

— Pinout and software compatible with single-power-

supply flash standard

PERFORMANCE CHARACTERISTICS

■High performance

— Access time as fast 90 ns

— Program time: 8 µs/word typical using Accelerate

■Ultra low power consumption (typical values)

— 1 mA active read current at 1 MHz

— 5 mA active read current at 5 MHz

— 1 µA in standby or automatic sleep mode

■Minimum 1 million erase cycles guaranteed per

sector

■20 Year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

■Supports Common Flash Memory Interface (CFI)

■Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in

same bank

■Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

■Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

HARDWARE FEATURES

■Any combination of sectors can be erased

■Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

■Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to reading array data

■WP#/ACC input pin

— Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect status

— Acceleration (ACC) function accelerates program

timing

■Sector protection

— Hardware method of locking a sector, either in-

system or using programming equipment, to prevent

any program or erase operation within that sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

4 Am29SL160C November 1, 2004

GENERAL DESCRIPTION

The Am29SL160C is a 16 Mbit, 1.8 V volt-only Flash

memory organized as 2,097,152 bytes or 1,048,576

words. The data appears on DQ0–DQ15. The device is

offered in 48-pin TSOP and 48-ball FBGA packages.

The word-wide data (x16) appears on DQ15–DQ0; the

byte-wide (x8) data appears on DQ7–DQ0. This device is

designed to be programmed and erased in-system with a

single 1.8 volt VCC supply. No VPP is required for program

or erase operations. The device can also be programmed

in standard EPROM programmers.

The standard device offers access times of 90, 100,

120, or 150 ns, allowing microprocessors to operate

without wait states. To eliminate bus contention the

device has separate chip enable (CE#), write enable

(WE#) and output enable (OE#) controls.

The device requires only a single 1.8 volt power

supply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

Device erasure occurs by executing the erase

command sequence. This initiates the Embedded

Erase algorithm—an internal algorithm that automati-

cally preprograms the array (if it is not already

programmed) before executing the erase operation.

During erase, the device automatically times the erase

pulse widths and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle

completes, the device is ready to read array data or

accept another command.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write operations

during power transitions. The hardware sector pro-

tection feature disables both program and erase

operations in any combination of the sectors of

memory. This is achieved in-system or via program-

ming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor to

read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When

addresses are stable for a specified amount of time, the

device enters the automatic sleep mode. The system

can also place the device into the standby mode.

Power consumption is greatly reduced in both modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunneling.

The data is programmed using hot electron injection.

November 1, 2004 Am29SL160C 5
TABLE OF CONTENTS
Product Selector Guide   . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling I nstructions for FBGA Packages  ..................8
Pin Configuration   . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information   . . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29SL160C Device Bus Operations  .............................11
Word/Byte Configuration  ........................................................11
Requirements for Reading Array Data ...................... .. .. .........11
Writing Commands/Command Sequences ............ ................12
Acc e le ra t ed  Pr o g r a m O p era t io n  ........... ... .. .. ....... ... .. ....... ... .. ...12
Program and Erase Operation Status  ....................................12
Standby Mode ......... .................. ........ .......................... ......... ..12
Automatic Sleep Mode  ............................... ................... .........12
RESET#: Hardware Reset Pin  ...............................................12
Output Disable Mode ..............................................................13
Table 2. Am29SL160CT Top Boot Sector Architecture  ..................14
Table 3. Am29SL160CB Bottom Boot Sector Architecture .............15
Autoselect Mode ........................... ............................. .............16
Table 4. Am29SL160C Autoselect Codes (High Voltage Method) . .16
Sector/Sector Block Protection and Unprotection  ..................17
Table 5. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................17
Table 6. Bottom Boot Sector/Sector Block 
Addresses forProtection/Unprotection ...........................................17
Write Protect (WP#) ................................................................18
Temporary Sector Unprotect ..................................................18
Figur e 1. In -System Sector Protect/Unprotect Algori th ms.............. 19
Figure 2. Temporary Sector Unprotect Operation........................... 20
Secured Silicon (SecSi) Sector Flash Memory Region ..........20
Table 7. SecSi Sector Addresses ...................................................20
Hardware Data Protection ......................................................20
Low VCC Write Inhibit ..............................................................20
Write Pulse “Glitch” Protection  ...............................................20
Logical Inhibit ..........................................................................20
Power-Up Write Inhibit ............................................................20
Common Flash Memory Interface (CFI) . . . . . . .   21
Table 8. CFI Query Identification String ..........................................21
Table 9. System Interface  String .....................................................22
Table 10.  Device  Geome try Definition ............................................22
Table 11. Primary Vendor-Specific Extended Query ......................23
Command Definitions . . . . . . . . . . . . . . . . . . . . .   23
Reading Array Data ................................................................23
Reset Command ............. ......... ......... ............... ......... ..............23
Autoselect Command Sequence ...... ............... .......................24
Enter SecSi Sector/Exit SecSi Sector Command Sequence  ..24
Word/Byte Program Command Sequence .............................24
Unlock Bypass Command Sequence ........................ ........... ..24
Figur e 3. Pro g r a m Opera tion ...... ....................... ....... ....... ............... 25
Chip Erase Command Sequence ...........................................26
Sector Erase Command Sequence ........................................26
Erase Suspend/Erase Resume Commands ...........................26
Figur e 4. Era se  Ope ra tion......................... .................. ....... ............  27
Command De f in i ti o n s  . ........ .. .. ....... ... .. ....... ... .. .. ....... ... .. ....... ... 28
Table 12. Am29SL160C Command Definitions  .............................28
Write Operation Status   . . . . . . . . . . . . . . . . . . . .  29
DQ7: Da ta# Po l lin g  .... . ... .............. .. ... ....... .. ... ....... .. .. ........ .. .. ...2 9
Figur e 5. Dat a #  Poll in g  Al g orithm........................ ................... ....... 29
RY/BY#: Ready/Busy# ............................................................30
DQ6: Toggle Bit I ....................................................................30
DQ2: Toggle Bit II ...................................................................30
Reading Toggle Bits DQ6/DQ2 ...............................................30
DQ5: Exceeded Timing Limits ................................................31
DQ3: S e cto r  Er a s e  Time r ... .. .. ....... ... .. .. ........ .. .. ............... .. .. ...31
Figure 6. Toggle Bit Algorithm........................................................  31
Table 13.  Write Ope r a tion Stat us  ........................ ........................... 32
Absolute Maximum Ratings  . . . . . . . . . . . . . . . .  33
Figure 7. Maximum Negative Overshoot Waveform......................  33
Figure 8. Maximum Posi tive Oversh o otWavefo r m....... ............ .....  33
Operating Ranges   . . . . . . . . . . . . . . . . . . . . . . . .  33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .  34
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic 
SleepCurrents)............... ................... .................. ................... ....... 35
Figure 10. Typical ICC1 vs.  Fre q uen cy....................................... ..... 35
Test Conditions  . . . . . . . . . . . . . . . . . . . . . . . . . .  36
Figure 11. Test Setup ..................................................................... 36
Table 14.  Te st Sp e ci fication s  .............. ....... .................. ....... ....... ....36
Figure 12. Input Waveforms and Measurement Levels ................. 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .  37
Read Operations  ......... ........ ........... ................... ........ ........... ..37
Figure 13. Read Operations Timings.............................................  37
Hardware Reset (RESET#) ........ .. ........................ .. .. ..............38
Figure 14. RESET# Timings ..........................................................  38
Word/Byte Configuration (BYTE#)  ........................................39
Figure 15. BYTE# Ti mings for Read Operations...... .............. ........  39
Figure 16. BYTE# Timings for Write Operations............................  39
Erase/Program Operations .....................................................40
Figure 17. Program Operation Timings.......................................... 41
Figure 18. Chip/Sector Erase Operation Timings.......................... 42
Figure 19. Data# Polling Timings (During Embedded Algorithms).  43
Figure 20. Toggle Bit Timings (During Embedded Algorithms)......  43
Figur e 21 . DQ2 vs. DQ6................................................................. 44
Figure 22. Temporary Sector Unprotect Timing Diagram. .............  44
Figure 23. Accelerated Program Timing Diagram..........................  45
Figure 24. Sector Protect/Unprotect Timing Diagram.......... ....... ... 45
Figure 25. Alternate CE# Controlled Write Operation Tim ing s ......  47
Erase And Programming Performance  . . . . . . .  48
Latchup Characteristics. . . . . . . . . . . . . . . . . . . .  48
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . .  48
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . .  48
Physical Dimensions*  . . . . . . . . . . . . . . . . . . . . .  49
TS 048— 4 8 -P i n  Sta n da rd  TS OP . ....... .. ... .. ....... ... .. .. ........ .. .. ...49
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8 x 9 mm package  ..................................................................50
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . .  51

6 Am29SL160C November 1, 2004

PRODUCT SELECTOR GUIDE

Note:See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

Family Part Number Am29SL160C

Speed Options -90 -100 -120 -150

Max access time, ns (tACC) 90 100 120 150

Max CE# access time, ns (tCE) 90 100 120 150

Max OE# access time, ns (tOE)35355065

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

VCC

VSS

WE#

BYTE#

WP#/ACC

CE#

OE#

STB

DQ0–DQ15 (A-1)

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A19

November 1, 2004 Am29SL160C 7

CONNECTION DIAGRAMS

A15

A18

A14

A13

A12

A11

A10

A19

WE#

RESET#

WP#/ACC

RY/BY#

A17

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

Standard TSOP

8 Am29SL160C November 1, 2004

CONNECTION DIAGRAMS (Continued)

Special Handling Instructions for FBGA

Packages

Special handling is required for Flash Memory products

in FBGA packages.

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be compro-

mised if the package body is exposed to temperatures

above 150°C for prolonged periods of time.

A1 B1 C1 D1 E1 F1 G1 H1

A2 B2 C2 D2 E2 F2 G2 H2

A3 B3 C3 D3 E3 F3 G3 H3

A4 B4 C4 D4 E4 F4 G4 H4

A5 B5 C5 D5 E5 F5 G5 H5

A6 B6 C6 D6 E6 F6 G6 H6

DQ15/A-1 VSS

BYTE#A16A15A14A12A13

DQ13 DQ6DQ14DQ7A11A10A8A9

VCC DQ4DQ12DQ5A19NCRESET#WE#

DQ11 DQ3DQ10DQ2NCA18WP#/ACCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE# VSS

CE#A0A1A2A4A3

48-Ball FBGA

(Top View, Balls Facing Down)

November 1, 2004 Am29SL160C 9

PIN CONFIGURATION

A0–A19 = 20 addresses

DQ0–DQ14 = 15 data inputs/outputs

DQ15/A-1 = DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

CE# = Chip enable

OE# = Output enable

WE# = Write enable

WP#/ACC = Hardware write protect/acceleration

RESET# = Hardware reset pin, active low

BYTE# = Selects 8-bit or 16-bit mode

RY/BY# = Ready/Busy# output

VCC = 1.8–2.2 V single power supply

VSS = Device ground

NC = Pin not connected internally

LOGIC SYMBOL

16 or 8

DQ0–DQ15

(A-1)

A0–A19

CE#

OE#

WE#

RESET#

BYTE#

RY/BY#

WP#/ACC

10 Am29SL160C November 1, 2004

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

Am29SL160C T -90 E C N

STANDARD PROCESSING

N = SecSi Sector factory-locked with random ESN

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

D= Commercial (0

oC to +70oC) with PB-free Package

F = Industrial (-40oC to +85oC) with PB-free Package

F = Extended (-55oC to +125oC) with PB-free Package

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

WC=48-ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 8 x 9 mm package (FBC048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top sector

B = Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29SL160C

16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations for TSOP Packages

AM29SL160CT-90,

AM29SL160CB-90

EC, EI

ED, EF

AM29SL160CT-100,

AM29SL160CB-100

AM29SL160CT-120,

AM29SL160CB-120

AM29SL160CT-150,

AM29SL160CB-150

Valid Combinations for FBGA Packages

Order Number Package Marking

AM29SL160CT-90,

AM29SL160CB-90

WCC,

WCI

WCD,

WCF

A160CT90V,

A160CB90V

C, I,

D, F

AM29SL160CT-100,

AM29SL160CB-100

A160CT10V,

A160CB10V

AM29SL160CT-120,

AM29SL160CB-120

A160CT12V,

A160CB12V

AM29SL160CT-150,

AM29SL160CB-150

A160CT15V,

A160CB15V

November 1, 2004 Am29SL160C 11
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tabl e 1  lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29SL160C Device Bus Operations 
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 10 ± 1.0 V, VHH = 10 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In,
DOUT = Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector/Sector 
Block Protection and Unprotection” on page 17.
3. If WP#/ACC = VIL, the two outermost boot sectors are protected. If WP#/ACC = VIH, the two outermost boot sectors are 
protected or unprotected as previously set by the system. If WP#/ACC = VHH, all sectors, including the two outermost boot 
sectors, are unprotected. 
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function. 
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
Operation CE# OE# WE# RESET# WP#/ACC
Addresses
(Note 1)
DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE# 
= VIL
Read L L H H X AIN DOUT DOUT DQ8–DQ14 = High-Z, 
DQ15 = A-1
Write 
(Program/Erase) L H L H (Note 3) AIN DIN DIN
Standby VCC ± 
0.2 V XXVCC ± 
0.2 V X X High-Z High-Z High-Z
Output Disable L H H H X X High-Z High-Z High-Z
Reset X X X L X X High-Z High-Z High-Z
Sector Protect 
(Note 2) LHL V
ID X
Sector Address, 
A6 = L, A1 = H, 
A0 = L
DIN XX
Sector Unprotect 
(Note 2) LHL V
ID (Note 3)
Sector Address, 
A6 = H, A1 = H, 
A0 = L
DIN XX
Temporary Sector 
Unprotect XXX V
ID (Note 3) AIN DIN DIN High-Z

12 Am29SL160C November 1, 2004
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” on page 23 for more infor-
mation. Refer to the AC  table for timing specifications
and to Figure 13, on page 37 for the timing diagram.
ICC1 in the DC Characteristics table represents the
active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” on page 11
for more information. 
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” on
page 24 contains details on programming data to the
device using both standard and Unlock Bypass
command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2, on page 14 and
Table 3, on page 15 indicate the address space that
each sector occupies. A “sector address” consists of
the address bits required to uniquely select a sector.
The “Command Definitions” on page 23 contains
details on erasing a sector or the entire chip, or sus-
pending/resuming the erase operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to “Autoselect Mode” on page 16
and “Autoselect Command Sequence” on page 24 for
more information.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The “AC
Characteristics” on page 37 contains timing specifica-
tion tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operation
through the ACC function, which is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster in-system programming of
the device during the system production process.
If the system asserts VHH on the pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode and uses the higher voltage on the pin to reduce
the time required for program operations. The system
would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing VHH
from the WP#/ACC pin returns the device to normal
operation.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” on page 29 for more information, and to “AC
Characteristics” on page 37 for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input. 
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.2 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.2 V, the device is in the standby mode, but the
standby current is greater. The device requires stan-
dard access time (tCE) for read access when the device
is in either of these standby modes, before it is ready to
read data.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to “RESET#: Hard-
ware Reset Pin” on page 12.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification. 
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
tACC + 50 ns. The automatic sleep mode is independent
of the CE#, WE#, and OE# control signals. Standard
address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system. ICC4
in the DC Characteristics table represents the auto-
matic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the

November 1, 2004 Am29SL160C 13

RESET# pin is driven low for at least a period of tRP

, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all read/

write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to

reading array data. The operation that was interrupted

should be reinitiated once the device is ready to accept

another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS ± 0.2 V, the device

draws CMOS standby current (ICC4). If RESET# is held

at VIL but not within VSS ± 0.2 V, the standby current is

greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The

system can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of tREADY (not during Embedded Algo-

rithms). The system can read data tRH after the

RESET# pin returns to VIH.

Refer to “AC Characteristics” on page 37 for RESET#

parameters and to “RESET# Timings” on page 38 for

the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

14 Am29SL160C November 1, 2004

Table 2. Am29SL160CT Top Boot Sector Architecture

Note: Address range is A19:A-1 in byte mode and A19:A0 in

word mode. See “Word/Byte Configuration” section for more

information.

Sector

Sector Address Sector Size

(Kbytes/Kwords)

Address Range (in Hexadecimal

A19 A18 A17 A16 A15 A14 A13 A12 Byte Mode (x8) Word Mode (x16)

SA0 00000XXX 64/32 000000h–00FFFFh00000h–07FFFh

SA1 00001XXX 64/32 010000h–01FFFFh08000h–0FFFFh

SA2 00010XXX 64/32 020000h–02FFFFh10000h–17FFFh

SA3 00011XXX 64/32 030000h–03FFFFh18000h–1FFFFh

SA4 00100XXX 64/32 040000h–04FFFFh20000h–27FFFh

SA5 00101XXX 64/32 050000h–05FFFFh28000h–2FFFFh

SA6 00110XXX 64/32 060000h–06FFFFh30000h–37FFFh

SA7 00111XXX 64/32 070000h–07FFFFh38000h–3FFFFh

SA8 01000XXX 64/32 080000h–08FFFFh40000h–47FFFh

SA9 01001XXX 64/32 090000h–09FFFFh48000h–4FFFFh

SA1001010XXX 64/32 0A0000h–0AFFFFh50000h–57FFFh

SA1101011XXX 64/32 0B0000h–0BFFFFh58000h–5FFFFh

SA1201100XXX 64/32 0C0000h–0CFFFFh60000h–67FFFh

SA1301101XXX 64/32 0D0000h–0DFFFFh68000h–6FFFFh

SA1401110XXX 64/32 0E0000h–0EFFFFh70000h–77FFFh

SA1501111XXX 64/32 0F0000h–0FFFFFh78000h–7FFFFh

SA1610000XXX 64/32 100000h–10FFFFh80000h–87FFFh

SA1710001XXX 64/32 110000h–11FFFFh88000h–8FFFFh

SA1810010XXX 64/32 120000h–12FFFFh90000h–97FFFh

SA1910011XXX 64/32 130000h–13FFFFh98000h–9FFFFh

SA2010100XXX 64/32 140000h–14FFFFhA0000h–A7FFFh

SA2110101XXX 64/32 150000h–15FFFFhA8000h–AFFFFh

SA2210110XXX 64/32 160000h–16FFFFhB0000h–B7FFFh

SA2310111XXX 64/32 170000h–17FFFFhB8000h–BFFFFh

SA2411000XXX 64/32 180000h–18FFFFhC0000h–C7FFFh

SA2511001XXX 64/32 190000h–19FFFFhC8000h–CFFFFh

SA2611010XXX 64/32 1A0000h–1AFFFFhD0000h–D7FFFh

SA2711011XXX 64/32 1B0000h–1BFFFFhD8000h–DFFFFh

SA2811100XXX 64/32 1C0000h–1CFFFFhE0000h–E7FFFh

SA2911101XXX 64/32 1D0000h–1DFFFFhE8000h–EFFFFh

SA3011110XXX 64/32 1E0000h–1EFFFFhF0000h–F7FFFh

SA3111111000 8/4 1F0000h–1F1FFFhF8000h–F8FFFh

SA3211111001 8/4 1F2000h–1F3FFFhF9000h–F9FFFh

SA3311111010 8/4 1F4000h–1F5FFFhFA000h–FAFFFh

SA3411111011 8/4 1F6000h–1F7FFFhFB000h–FBFFFh

SA3511111100 8/4 1F8000h–1F9FFFhFC0004–FCFFFh

SA3611111101 8/4 1FA000h–1FBFFFhFD000h–FDFFFh

SA3711111110 8/4 1FC000h–1DFFFFhFE000h–FEFFFh

SA3811111111 8/4 1FE000h–1FFFFFhFF000h–FFFFFh

November 1, 2004 Am29SL160C 15

Table 3. Am29SL160CB Bottom Boot Sector Architecture

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section for more information.

Sector

Sector Address Sector Size

(Kbytes/Kwords)

Address Range (in hexadecimal)

A19 A18 A17 A16 A15 A14 A13 A12 Byte Mode (x8) Word Mode (x16)

SA0 00000000 8/4 000000h–001FFFh00000h–00FFFh

SA1 00000001 8/4 002000h–003FFFh01000h–01FFFh

SA2 00000010 8/4 004000h–005FFFh02000h–02FFFh

SA3 00000011 8/4 006000h–07FFFFh03000h–03FFFh

SA4 00000100 8/4 008000h–009FFFh04000h–04FFFh

SA5 00000101 8/4 00A000h–00BFFFh05000h–05FFFh

SA6 00000110 8/4 00C000h–00DFFFh06000h–06FFFh

SA7 00000111 8/4 00E000h–00FFFFh07000h–07FFFh

SA8 00001XXX 64/32 010000h–01FFFFh08000h–0FFFFh

SA9 00010XXX 64/32 020000h–02FFFFh10000h–17FFFh

SA1000011XXX 64/32 030000h–03FFFFh18000h–1FFFFh

SA1100100XXX 64/32 040000h–04FFFFh20000h–27FFFh

SA1200101XXX 64/32 050000h–05FFFFh28000h–2FFFFh

SA1300110XXX 64/32 060000h–06FFFFh30000h–37FFFh

SA1400111XXX 64/32 070000h–07FFFFh38000h–3FFFFh

SA1501000XXX 64/32 080000h–08FFFFh40000h–47FFFh

SA1601001XXX 64/32 090000h–09FFFFh48000h–4FFFFh

SA1701010XXX 64/32 0A0000h–0AFFFFh50000h–57FFFh

SA1801011XXX 64/32 0B0000h–0BFFFFh58000h–5FFFFh

SA1901100XXX 64/32 0C0000h–0CFFFFh60000h–67FFFh

SA2001101XXX 64/32 0D0000h–0DFFFFh68000h–6FFFFh

SA2101110XXX 64/32 0E0000h–0EFFFFh70000h–77FFFh

SA2201111XXX 64/32 0F0000h–0FFFFFh78000h–7FFFFh

SA2310000XXX 64/32 100000h–10FFFFh80000h–87FFFh

SA2410001XXX 64/32 110000h–11FFFFh88000h–8FFFFh

SA2510010XXX 64/32 120000h–12FFFFh90000h–97FFFh

SA2610011XXX 64/32 130000h–13FFFFh98000h–9FFFFh

SA2710100XXX 64/32 140000h–14FFFFhA0000h–A7FFFh

SA2810101XXX 64/32 150000h–15FFFFhA8000h–AFFFFh

SA2910110XXX 64/32 160000h–16FFFFhB0000h–B7FFFh

SA3010111XXX 64/32 170000h–17FFFFhB8000h–BFFFFh

SA3111000XXX 64/32 180000h–18FFFFhC0000h–C7FFFh

SA3211001XXX 64/32 190000h–19FFFFhC8000h–CFFFFh

SA3311010XXX 64/32 1A0000h–1AFFFFhD0000h–D7FFFh

SA3411011XXX 64/32 1B0000h–1BFFFFhD8000h–DFFFFh

SA3511100XXX 64/32 1C0000h–1CFFFFhE0000h–E7FFFh

SA3611101XXX 64/32 1D0000h–1DFFFFhE8000h–EFFFFh

SA3711110XXX 64/32 1E0000h–1EFFFFhF0000h–F7FFFh

SA3811111XXX 64/32 1F0000h–1FFFFFhF8000h–FFFFFh

16 Am29SL160C November 1, 2004

Autoselect Mode

The autoselect mode provides manufacturer and

device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

When using programming equipment, the autoselect

mode requires VID on address pin A9. Address pins A6,

A1, and A0 must be as shown in Table 4. In addition,

when verifying sector protection, the sector address

must appear on the appropriate highest order address

bits (see Tables 2 and 3). Table 4 shows the remaining

address bits that are don’t care. When all necessary

bits are set as required, the programming equipment

may then read the corresponding identifier code on

DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 12, on page 28.

This method does not require VID. See “Command Def-

initions” on page 23 for details on using the autoselect

mode.

Table 4. Am29SL160C Autoselect Codes (High Voltage Method)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Note: Outputs for data bits DQ8–DQ15 are for BYTE#=VIH. DQ8–DQ15 are don’t care when BYTE#=VIL.

Description Mode CE# OE# WE#

A19

A12

A11

A10 A9

A7 A6

A2 A1 A0

DQ8

DQ15

DQ7

DQ0

Manufacturer ID: AMD L L H X X VID XLXLL X 01h

Device ID:

Am29SL160CT

(Top Boot Block)

Word L L H

XXV

ID XLXLH

22h E4

Byte L L H X E4

Device ID:

Am29SL160CB

(Bottom Boot

Block)

Word L L H

XXV

ID XLXLH

22h E7

Byte L L H X E7

Sector Protection Verification L L H SA X VID XLXHL

X01h

(protected)

X00h

(unprotected)

SecSi Sector Indicator bit

(DQ7) LLHSAXV

ID XLXHH X

81h

(factory

locked)

November 1, 2004 Am29SL160C 17

Sector/Sector Block Protection and

Unprotection

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Tab l e 5

and Table 6).

Table 5. Top Boot Sector/Sector Block Addresses

for Protection/Unprotection

Table 6. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors. Sector protection/unprotection is implemented

via two methods.

Sector / Sector

Block A19–A12 Sector / Sector Block Size

SA0 00000XXX 64 Kbytes

SA1-SA3

00001XXX,

00010XXX,

00011XXX

192 (3x64) Kbytes

SA4-SA7 001XXXXX 256 (4x64) Kbytes

SA8-SA11 010XXXXX 256 (4x64) Kbytes

SA12-SA15 011XXXXX 256 (4x64) Kbytes

SA16-SA19 100XXXXX 256 (4x64) Kbytes

SA20-SA23 101XXXXX 256 (4x64) Kbytes

SA24-SA27 110XXXXX 256 (4x64) Kbytes

SA28-SA30

11100XXX,

11101XXX,

11110XXX

192 (3x64) Kbytes

SA31 11111000 8 Kbytes

SA32 11111001 8 Kbytes

SA33 11111010 8 Kbytes

SA34 11111011 8 Kbytes

SA35 11111100 8 Kbytes

SA36 11111101 8 Kbytes

SA37 11111110 8 Kbytes

SA38 11111111 8 Kbytes

Sector / Sector

Block A19–A12 Sector / Sector Block Size

SA38 11111XXX 64 Kbytes

SA37-SA35

11110XXX,

11101XXX,

11100XXX

192 (3x64) Kbytes

SA34-SA31 110XXXXX 256 (4x64) Kbytes

SA30-SA27 101XXXXX 256 (4x64) Kbytes

SA26-SA23 100XXXXX 256 (4x64) Kbytes

SA22-SA19 011XXXXX 256 (4x64) Kbytes

SA18-SA15 010XXXXX 256 (4x64) Kbytes

SA14-SA11 001XXXXX 256 (4x64) Kbytes

SA10-SA8

00001XXX,

00010XXX,

00011XXX

192 (3x64) Kbytes

SA7 00000111 8 Kbytes

SA6 00000110 8 Kbytes

SA5 00000101 8 Kbytes

SA4 00000100 8 Kbytes

SA3 00000011 8 Kbytes

SA2 00000010 8 Kbytes

SA1 00000001 8 Kbytes

SA0 00000000 8 Kbytes

18 Am29SL160C November 1, 2004
The primary method requires VID on the RESET# pin
only, and is implemented either in-system or via pro-
gramming equipment. Figure 1, on page 19 shows the
algorithms and Figure 24, on page 45 shows the timing
diagram. This method uses standard microprocessor
bus cycle timing. For sector unprotect, all unprotected
sectors must first be protected prior to the first sector
unprotect write cycle. 
The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD flash devices. Pub-
lication number 21622 contains further details. Contact
an AMD representative to request the document con-
taining further details.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” on page 16 for
details.
Write Protect (WP#)
The write protect function provides a hardware method
of protecting certain boot sectors without using VID.
This function is one of two provided by the WP#/ACC
pin.
If the system asserts VIL on the WP#/ACC pin, the
device disables program and erase functions in the two
“outermost” 8 Kbyte boot sectors independently of
whether those sectors were protected or unprotected
using the method described in “Sector/Sector Block
Protection and Unprotection” on page 17. The two out-
ermost 8 Kbyte boot sectors are the two sectors
containing the lowest addresses in a bottom-boot-con-
figured device, or the two sectors containing the
highest addresses in a top-boot-configured device.
If the system asserts VIH on the WP#/ACC pin, the
device reverts to whether the two outermost 8 Kbyte
boot sectors were last set to be protected or unpro-
tected. That is, sector protection or unprotection for
these two sectors depends on whether they were last
protected or unprotected using the method described
in “Sector/Sector Block Protection and Unprotection”
on page 17.
Note that if the system asserts VHH on the WP#/ACC
pin, all sectors, including the two outermost sectors,
are unprotected. VHH is intended for accelerated in-
system programming of the device during system pro-
duction. It is advisable, therefore, not to assert VHH on
this pin after the system has been placed in the field for
use. If faster programming is desired, the system may
use the unlock bypass program command sequence.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the
RESET# pin to VID. During this mode, formerly pro-
tected sectors can be programmed or erased by
selecting the sector addresses. Once VID is removed
from the RESET# pin, all the previously protected
sectors are protected again. Figure 2, on page 20
shows the algorithm, and Figure 22, on page 44 shows
the timing diagrams, for this feature.

November 1, 2004 Am29SL160C 19

Figure 1. In-System Sector Protect/Unprotect Algorithms

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode No

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

Data = 00h?

Last sector

verified?

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Secto

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

ector Protect

Algorithm Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

20 Am29SL160C November 1, 2004

Figure 2. Temporary Sector Unprotect Operation

Secured Silicon (SecSi) Sector Flash

Memory Region

The Secured Silicon (SecSi) Sector is a flash memory

region that enables permanent part identification

through an Electronic Serial Number (ESN). The SecSi

Sector in this device is 256 bytes in length. The device

contains a SecSi Sector indicator bit that allows the

system to determine whether or not the SecSi Sector

was factory locked. This indicator bit is permanently set

at the factory and cannot be changed, which prevents

a factory-locked part from being cloned.

AMD offers this device only with the SecSi Sector

factory serialized and locked. The first sixteen bytes of

the SecSi Sector contain a random ESN. To utilize the

remainder SecSi Sector space, customers must

provide their code to AMD through AMD’s Express

Flash service. The factory will program and perma-

nently protect the SecSi Sector (in addition to

programming and protecting the remainder of the

device as required).

The system can read the SecSi Sector by writing the

Enter SecSi Sector command sequence (see “Enter

SecSi Sector/Exit SecSi Sector Command Sequence”

on page 24). Table 7, on page 20 shows the layout for

the SecSi Sector.

Table 7. SecSi Sector Addresses

The device continues to read from the SecSi Sector

until the system issues the Exit SecSi Sector command

sequence, or until power is removed from the device.

On power-up, or following a hardware reset, the device

reverts to sending commands to the boot sectors.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 12, on

page 28 for command definitions). In addition, the fol-

lowing hardware data protection measures prevent

accidental erasure or programming, which might other-

wise be caused by spurious system level signals during

VCC power-up and power-down transitions, or from

system noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept

any write cycles. This protects data during VCC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until VCC

is greater than VLKO. The system must provide the

proper signals to the control pins to prevent uninten-

tional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sectors unprotected. (If WP#/ACC = VIL,

the outermost sectors remain protected)

2. All previously protected sectors are protected once

again.

Description

Address Range

Word Mode

(x16) Byte Mode (x8)

16-byte random ESN 00–07h 000–00Fh

User-defined code or

factory erased (all 1s) 08–7Fh 010–0FFh

November 1, 2004 Am29SL160C 21

COMMON FLASH MEMORY INTERFACE

(CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-indepen-

dent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

This device enters the CFI Query mode when the

system writes the CFI Query command, 98h, to

address 55h in word mode (or address AAh in byte

mode), any time the device is ready to read array data.

The system can read CFI information at the addresses

given in Table 8, on page 21 to Table 11, on page 23.

To terminate reading CFI data, the system must write

the reset command.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Table 8, on page 21

to Table 11, on page 23. The system must write the

reset command to return the device to the autoselect

mode.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/products/nvd/over-

view/cfi.html. Alternatively, contact an AMD

representative for copies of these documents.

Table 8. CFI Query Identification String

Addresses

(Word Mode)

Addresses

(Byte Mode) Data Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

0000h Alternate OEM Command Set (00h = none exists)

19h

1Ah

32h

34h

0000h

0000h Address for Alternate OEM Extended Table (00h = none exists)

22 Am29SL160C November 1, 2004

Table 9. System Interface String

Table 10. Device Geometry Definition

Addresses

(Word Mode)

Addresses

(Byte Mode) Data Description

1Bh 36h 0018h VCC Min. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch 38h 0022h VCC Max. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)

1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present)

1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs

20h 40h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported)

21h 42h 000Ah Typical timeout per individual block erase 2N ms

22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)

23h 46h 0005h Max. timeout for byte/word write 2N times typical

24h 48h 0000h Max. timeout for buffer write 2N times typical

25h 4Ah 0004h Max. timeout per individual block erase 2N times typical

26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

Addresses

(Word Mode)

Addresses

(Byte Mode) Data Description

27h 4Eh 0015h Device Size = 2N byte

28h

29h

50h

52h

0002h

0000h Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0000h

Max. number of bytes in multi-byte write = 2N

(00h = not supported)

2Ch 58h 0002h Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

001Eh

0000h

0001h

Erase Block Region 2 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

Erase Block Region 3 Information

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Erase Block Region 4 Information

November 1, 2004 Am29SL160C 23
Table 11. Primary Vendor-Specific Extended Query
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 12, on page 28 defines the valid reg-
ister command sequences. Writing incorrect address
and data values or writing them in the improper
sequence resets the device to reading array data. 
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in “AC
Characteristics” on page 37.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” on page 26 for
more information on this mode.
The system must issue the reset command to re-
enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See “Reset Com-
mand”, next.
See also “Requirements for Reading Array Data” on
page 11 for more information. The  table provides the
read parameters, and Figure 13, on page 37 shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command. 
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to
reading array data. Once erasure begins, however, the
device ignores reset commands until the operation is
complete.
The reset command may be written between the
sequence cycles in a program command sequence
Addresses
(Word Mode)
Addresses
(Byte Mode) Data Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h 86h 0031h Major version number, ASCII
44h 88h 0030h Minor version number, ASCII
45h 8Ah 0000h Address Sensitive Unlock
0 = Required, 1 = Not Required
46h 8Ch 0002h Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 8Eh 0001h Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 90h 0001h Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 92h 0004h
Sector Protect/Unprotect scheme 
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah 94h 0000h Simultaneous Operation
00 = Not Supported, 01 = Supported
4Bh 96h 0000h Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 98h 0000h Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

24 Am29SL160C November 1, 2004
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies during Erase
Suspend).
See “AC Characteristics” on page 37 for parameters, and
to Figure 14, on page 38 for the timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Table 12, on page 28 shows the address and data
requirements. This method is an alternative to that
shown in Table 4, on page 16, which is intended for
PROM programmers and requires VID on address bit
A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence. A read cycle at address XX00h retrieves the
manufacturer code. A read cycle at address 01h in
word mode (or 02h in byte mode) returns the device
code. A read cycle containing a sector address (SA)
and the address 02h in word mode (or 04h in byte
mode) returns 01h if that sector is protected, or 00h if it
is unprotected. Refer to Table 2, on page 14 and
Table 3, on page 15 for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Enter SecSi Sector/Exit SecSi Sector Com-
mand Sequence
The SecSi Sector region provides a secured data area
containing a random, sixteen-byte electronic serial
number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi
Sector command sequence. The device continues to
access the SecSi Sector region until the system issues
the four-cycle Exit SecSi command sequence. The Exit
SecSi command sequence returns the device to
normal operation. Table 12, on page 28 shows the
address and data requirements for both command
sequences. See also “Secured Silicon (SecSi) Sector
Flash Memory Region” on page 20 for further
information. 
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up command.
The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or tim-
ings. The device automatically generates the program
pulses and verifies the programmed cell margin.
Table 12, on page 28 shows the address and data
requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
on page 29 for information on these status bits. 
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command
sequence should be reinitiated once the device resets
to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read shows that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes or words to the device faster than using
the standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-
cycle unlock bypass program command sequence is all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two
unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 12, on page 28 shows the
requirements for the command sequence.

November 1, 2004 Am29SL160C 25

During the unlock bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset

command sequence. The first cycle must contain the

data 90h; the second cycle the data 00h. Addresses

are don’t cares. The device then returns to reading

array data.

The device offers accelerated program operations

through the WP#/ACC pin. This function is intended

only to speed in-system programming of the device

during system production. When the system asserts

VHH on the WP#/ACC pin, the device automatically

enters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at VHH for any operation

other than accelerated programming, or device

damage may result. In addition, the WP#/ACC pin must

not be left floating or unconnected; inconsistent

behavior of the device may result.

Figure 3 illustrates the algorithm for the program oper-

ation. See “Erase/Program Operations” on page 40 for

parameters, and Figure 17, on page 41 for timing

diagrams.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

Note: See Table 12, on page 28 for program command

sequence.

Figure 3. Program Operation

26 Am29SL160C November 1, 2004
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 12, on
page 28 shows the address and data requirements for
the chip erase command sequence.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation imme-
diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device returns to reading array data, to ensure data
integrity.
The system can determine the status of the erase oper-
ation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write
Operation Status” on page 29 for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data and
addresses are no longer latched. 
Figure 4, on page 27 illustrates the algorithm for the
erase operation. See “Erase/Program Operations” on
page 40 for parameters, and Figure 18, on page 42 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 12, on page 28 shows the
address and data requirements for the sector erase
command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations. 
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts are re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See “DQ3: Sector Erase
Timer” on page 31.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation begins, only the Erase
Suspend command is valid. All other commands are
ignored. Note that a hardware reset during the sector
erase operation immediately terminates the operation.
The Sector Erase command sequence should be rein-
itiated once the device returns to reading array data, to
ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. (Refer to “Write Operation Status” on
page 29 for information on these status bits.)
Figure 4, on page 27 illustrates the algorithm for the
erase operation. Refer to the “Erase/Program Opera-
tions” on page 40 for parameters, and to Figure 18, on
page 42 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation.
Addresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.

November 1, 2004 Am29SL160C 27

After the erase operation is suspended, the system can

read array data from or program data to any sector not

selected for erasure. (The device “erase suspends” all

sectors selected for erasure.) Normal read and write

timings and command definitions apply. Reading at any

address within erase-suspended sectors produces

status data on DQ7–DQ0. The system can use DQ7, or

DQ6 and DQ2 together, to determine if a sector is

actively erasing or is erase-suspended. See “Write

Operation Status” on page 29 for information on these

status bits.

After an erase-suspended program operation is com-

plete, the system can once again read array data within

non-suspended sectors. The system can determine the

status of the program operation using the DQ7 or DQ6

status bits, just as in the standard program operation.

See “Write Operation Status” on page 29 for more

information.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

on page 24 for more information.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the

device resumes erasing.

Notes:

1. See Table 12, on page 28 for erase command sequence.

2. See “DQ3: Sector Erase Timer” on page 31 for more in-

formation.

Figure 4. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFH?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

28 Am29SL160C November 1, 2004
Command Definitions
Table 12. Am29SL160C Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read. 
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses 
latch on the falling edge of the WE# or CE# pulse, whichever happens 
later.
PD = Data to be programmed at location PA. Data latches on the rising 
edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or 
erased. Address bits A19–A12 uniquely select any sector.
Notes:
1. See Table 1, on page 11 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect 
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t cares in byte mode.
5. Unless otherwise noted, address bits A19–A11 are don’t cares.
6. No unlock or command cycles required when in read mode.
7. The Reset command is required to return to the read mode (or to 
the erase-suspend-read mode if previously in Erase Suspend) 
when in the autoselect mode, or if DQ5 goes high (while providing 
status information).
8. The fourth cycle of the autoselect command sequence is a read 
cycle. 
9. The data is 00h for an unprotected sector and 01h for a protected 
sector. Data bits DQ15–DQ8 are don’t care. See the Autoselect 
Command Sequence section for more information.
10. The Unlock Bypass command is required prior to the Unlock 
Bypass Program command.
11. The Unlock Bypass Reset command is required to return to the 
read mode when in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or 
enter the autoselect mode, when in the Erase Suspend mode. 
The Erase Suspend command is valid only during a sector erase 
operation.
13. The Erase Resume command is valid only during the Erase 
Suspend mode.
14. Command is valid when device is ready to read array data or 
when device is in autoselect mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third  Fourth  Fifth Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Autoselect (Note 8)
Manufacturer ID Word 4555 AA 2AA 55 555 90 X00 01
Byte AAA 555 AAA
Device ID
(Top Boot/Bottom 
Boot)
Word 4555 AA 2AA 55 555 90 X01 22E4/
22E7
Byte AAA 555 AAA X02 E4/E7
SecSi Sector Factory 
Protect
Word 4555 AA 2AA 55 555 90 X03
Byte AAA 555 AAA X06
Sector Protect Verify 
(Note 9)
Word 4555 AA 2AA 55 555 90 (SA)X02
Byte AAA 555 AAA (SA)X04
Enter SecSi Sector Region Word 3555 AA 2AA 55 555 88
Byte AAA 555 AAA
Exit SecSi Sector Region Word 4555 AA 2AA 55 555 90 XXX 00
Byte AAA 555 AAA
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Unlock Bypass Word 3555 AA 2AA 55 555 20
Byte AAA 555 AAA
Unlock Bypass Program (Note 10) 2XXX A0 PA PD
Unlock Bypass Reset (Note 11) 2BA 90 XXX 00
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 12) 1 BA B0
Erase Resume (Note 13) 1 BA 30
CFI Query (Note 14) Word 155 98
Byte AA

November 1, 2004 Am29SL160C 29

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a program or erase operation: DQ2, DQ3,

DQ5, DQ6, DQ7, and RY/BY#. Table 13, on page 32

and the following subsections describe the functions of

these bits. DQ7 and DQ6 each offer a method for deter-

mining whether a program or erase operation is

complete or in progress. The device also provides a

hardware-based output signal, RY/BY#, to determine

whether an embedded program or erase operation is in

progress or is completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in progress

or completed, or whether the device is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the

final WE# pulse in the program or erase command

sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status

information on DQ7.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 100 µs, then

the device returns to reading array data. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores

the selected sectors that are protected.

When the system detects DQ7 changes from the com-

plement to true data, it can read valid data at DQ7–

DQ0 on the following read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. Figure 19, on

page 43, Data# Polling Timings (During Embedded

Algorithms), in the “AC Characteristics” section illus-

trates this.

Table 13, on page 32 shows the outputs for Data#

Polling on DQ7. Figure 5, on page 29 shows the Data#

Polling algorithm.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

30 Am29SL160C November 1, 2004
RY/BY#: Ready/Busy#
RY/BY# is a dedicated, open-drain output pin that indi-
cates whether an Embedded Algorithm is in progress
or complete. The RY/BY# status is valid after the rising
edge of the final WE# pulse in the command sequence.
Since RY/BY# is an open-drain output, several RY/BY#
pins can be tied together in parallel with a pull-up
resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 13, on page 32 shows the outputs for RY/BY#.
Figure 14, on page 38, Figure 17, on page 41 and
Figure 18, on page 42 shows RY/BY# for reset, pro-
gram, and erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle (The system may use either OE#
or CE# to control the read cycles). When the operation
is complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6
toggles for approximately 100 µs, then returns to
reading array data. If not all selected sectors are pro-
tected, the Embedded Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected. 
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling” on
page 29).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
Table 13, on page 32 shows the outputs for Toggle Bit
I on DQ6. Figure 6, on page 31 shows the toggle bit
algorithm. Figure 20, on page 43 shows the toggle bit
timing diagrams. Figure 21, on page 44 shows the dif-
ferences between DQ2 and DQ6 in graphical form. See
also the subsection on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence. The device toggles DQ2 with
each OE# or CE# read cycle. 
DQ2 toggles when the system reads at addresses
within those sectors that were selected for erasure. But
DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison,
indicates whether the device is actively erasing, or is in
Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are
required for sector and mode information. Refer to
Table 13, on page 32 to compare outputs for DQ2 and
DQ6. 
Figure 6, on page 31 shows the toggle bit algorithm in
flowchart form, and the section “DQ2: Toggle Bit II”
explains the algorithm. See also the “DQ6: Toggle Bit I”
subsection. Figure 20, on page 43 shows the toggle bit
timing diagram. Figure 21, on page 44 shows the differ-
ences between DQ2 and DQ6 in graphical form. 
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6, on page 31 for the following discus-
sion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice
in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of
the toggle bit after the first read. After the second read,
the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the
device completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device successfully completed the
program or erase operation. If it is still toggling, the

November 1, 2004 Am29SL160C 31

device did not completed the operation successfully,

and the system must write the reset command to return

to reading array data.

The remaining scenario is that the system initially

determines that the toggle bit is toggling and DQ5 is not

high. The system may continue to monitor the toggle bit

and DQ5 through successive read cycles, determining

the status as described in the previous paragraph.

Alternatively, it may choose to perform other system

tasks. In this case, the system must start at the begin-

ning of the algorithm when it returns to determine the

status of the operation (top of Figure 6).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the operation

exceeds the timing limits, DQ5 produces a “1.”

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation began. (The sector erase timer does

not apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out is complete, DQ3 switches

from “0” to “1.” If the time between additional sector

erase commands from the system are assumed to be

less than 50 µs, the system need not monitor DQ3. See

also the “Sector Erase Command Sequence” on

page 26.

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensure the device

accepted the command sequence, and then read DQ3.

If DQ3 is “1”, the internally controlled erase cycle

started; all further commands (other than Erase Sus-

pend) are ignored until the erase operation is complete.

If DQ3 is “0”, the device accepts additional sector erase

commands. To ensure the command is accepted, the

system software should check the status of DQ3 prior

to and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

Table 13, on page 32 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

Figure 6. Toggle Bit Algorithm

(Notes

1, 2)

(Note 1)

32 Am29SL160C November 1, 2004

Table 13. Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. See

“DQ5: Exceeded Timing Limits” on page 31 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

Operation

DQ7

(Note 2) DQ6

DQ5

(Note 1) DQ3

DQ2

(Note 2) RY/BY#

Standard

Mode

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Reading within Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Reading within Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

November 1, 2004 Am29SL160C 33

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1). . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

A9, OE#,

and RESET# (Note 2) . . . . . . . . –0.5 V to +11.0 V

All other pins (Note 1) . . . . . –0.5 V to VCC + 0.5 V

Output Short Circuit Current (Note 3) . . . . . . 100 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may overshoot VSS to

–2.0 V for periods of up to 20 ns. See Figure 7. Maximum

DC voltage on input or I/O pins is VCC +0.5 V. During

voltage transitions, input or I/O pins may overshoot to VCC

+2.0 V for periods up to 20 ns. See Figure 8.

2. Minimum DC input voltage on pins A9, OE#, RESET#,

and WP#/ACC is –0.5 V. During voltage transitions, A9,

OE#, WP#/ACC, and RESET# may overshoot VSS to –2.0

V for periods of up to 20 ns. See Figure 7. Maximum DC

input voltage on pin A9 is +11.0 V which may overshoot to

+12.5 V for periods up to 20 ns. Maximum DC input

voltage on pin WP#/ACC is +10.0 V which may overshoot

to +11.5 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C

VCC Supply Voltages

VCC, all speed options . . . . . . . . . . . .+1.8 V to +2.2 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

20 ns

0.0 V

–0.5 V

20 ns

–2.0 V

Figure 7. Maximum Negative

Overshoot Waveform

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

Figure 8. Maximum Positive

Overshoot Waveform

34 Am29SL160C November 1, 2004
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 1 mA/MHz, with OE# at VIL. Typical VCC is 2.0 V.
2. The maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 50 ns.
5. Not 100% tested.
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, 
VCC = VCC max
±1.0 µA
ILIT A9 Input Load Current VCC = VCC max; A9 = 11.0 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC, 
VCC = VCC max
±1.0 µA
ICC1
VCC Active Read Current 
(Notes 1, 2)
CE# = VIL, OE# = VIH,
Byte Mode
5 MHz 5 10
mA
1 MHz 1 3
CE# = VIL, OE# = VIH,
Word Mode
5 MHz 5 10
1 MHz 1 3
ICC2
VCC Active Write Current 
(Notes 2, 3, 5) CE# = VIL, OE# = VIH 20 30 mA
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC±0.2 V 1 5 µA
ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.2 V 1 5 µA
ICC5
Automatic Sleep Mode 
(Notes 2, 3)
VIH = VCC ± 0.2 V; 
VIL = VSS ± 0.2 V 15µA
VIL Input Low Voltage –0.5 0.2 x VCC V
VIH Input High Voltage 0.8 x VCC VCC + 0.3 V
VHH
Voltage for WP#/ACC Sector 
Protect/Unprotect and Program 
Acceleration
8.5 9.5 V
VID
Voltage for Autoselect and 
Temporary Sector Unprotect VCC = 2.0 V 9.0 11.0 V
VOL Output Low Voltage IOL = 100 µA, VCC = VCC min 0.1
VOH Output High Voltage IOH = –100 µA, VCC = VCC min V
CC–0.1
VLKO
Low VCC Lock-Out Voltage 
(Note 4) 1.2 1.5 V

November 1, 2004 Am29SL160C 35

DC CHARACTERISTICS (Continued)

Zero Power Flash

0 500 1000 1500 2000 2500 3000 3500 4000

Supply Current in mA

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

12345

Frequency in MHz

Supply Current in mA

Note: T = 25 °C

Figure 10. Typical ICC1 vs. Frequency

1.8 V

2.2 V

36 Am29SL160C November 1, 2004

TEST CONDITIONS

Table 14. Test Specifications

Key To Switching Waveforms

Device

Under

Te s t

Figure 11. Test Setup

Test Condition

-90,

-100

-120,

-150 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig capacitance) 30 100 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–2.0 V

Input timing measurement

reference levels 1.0 V

Output timing measurement

reference levels 1.0 V

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

2.0 V

0.0 V 1.0 V 1.0 V OutputMeasurement LevelInput

Figure 12. Input Waveforms and Measurement Levels

November 1, 2004 Am29SL160C 37

AC CHARACTERISTICS

Read Operations

Notes:

1. Not 100% tested.

2. See Figure 11, on page 36 and Table 14, on page 36 for

test specifications.

Parameter

Description

Speed Option

JEDEC Std Test Setup -90 -100 -120 -150 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 90 100 120 150 ns

tAVQV tACC Address to Output Delay CE# = VIL

OE# = VIL

Max 90 100 120 150 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 90 100 120 150 ns

tGLQV tOE Output Enable to Output Delay Max 35 35 50 65 ns

tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns

tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns

tOEH

Output Enable

Hold Time (Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 30 ns

tAXQX tOH

Output Hold Time From Addresses, CE#

or OE#, Whichever Occurs First (Note 1) Min 0 ns

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

0 V

RY/BY#

RESET#

tDF

tOH

Figure 13. Read Operations Timings

38 Am29SL160C November 1, 2004

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

tREADY

RESET# Pin Low (During Embedded

Algorithms) to Read or Write (see Note) Max 20 µs

tREADY

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (see Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH RESET# High Time Before Read (see Note) Min 200 ns

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

Figure 14. RESET# Timings

November 1, 2004 Am29SL160C 39

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Description

Speed Options

JEDEC Std -90 -100 -120 -150 Unit

tELFL/tELFH CE# to BYTE# Switching Low or High Max 10 ns

tFLQZ BYTE# Switching Low to Output HIGH Z Max 50 50 60 60 ns

tFHQV BYTE# Switching High to Output Active Min 90 100 120 150 ns

DQ15

Output

Data Output

(DQ0–DQ7)

CE#

OE#

BYTE#

tELFL

DQ0–DQ14 Data Output

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFLQZ

BYTE#

Switching

from word

to byte

mode

DQ15

Output

Data Output

(DQ0–DQ7)

BYTE#

tELFH

DQ0–DQ14 Data Output

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFHQV

BYTE#

Switching

from byte

to word

mode

Figure 15. BYTE# Timings for Read Operations

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.

Figure 16. BYTE# Timings for Write Operations

CE#

WE#

BYTE#

The falling edge of the last WE# signal

tHOLD (tAH)

tSET

(tAS)

40 Am29SL160C November 1, 2004

AC CHARACTERISTICS

Erase/Program Operations

Notes:

1. Not 100% tested.

2. See “Erase And Programming Performance” on page 48 for more information.

Parameter Speed Options

JEDEC Std Description -90 -100 -120 -150 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 150 ns

tAVWL tAS Address Setup Time Min 0 ns

tWLAX tAH Address Hold Time Min50506070ns

tDVWH tDS Data Setup Time Min50506070ns

tWHDX tDH Data Hold Time Min 0 ns

tGHWL tGHWL

Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 50 50 60 70 ns

tWHWL tWPH Write Pulse Width High Min 30 ns

tWHWH1 tWHWH1

Programming Operation (Notes 1, 2)

Byte Typ 10

µs

Word Typ 12

Accelerated Program Operation, Byte or Word

(Note 2) Typ 8 µs

tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 2 sec

tVCS VCC Setup Time Min 50 µs

tRB Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Min 200 ns

November 1, 2004 Am29SL160C 41

AC CHARACTERISTICS

OE#

WE#

CE#

VCC

Data

Addresses

tDS

WHWH1

WPH

VCS

555h PA PA

Read Status Data (last two cycles)

A0h

Status D

OUT

Program Command Sequence (last two cycles)

RY/BY#

tBUSY

Notes:

1. PA = program address, PD = program data, DOUT is the true data at the program address.

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

42 Am29SL160C November 1, 2004

AC CHARACTERISTICS

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

tRB

tBUSY

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

November 1, 2004 Am29SL160C 43

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

ddresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 19. Data# Polling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

DQ6/DQ2

RY/BY#

BUSY

Addresses VA

OEH

VA VA

ACC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle.

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

44 Am29SL160C November 1, 2004

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

All Speed OptionsJEDEC Std Description Unit

tVIDR VID Rise and Fall Time Min 500 ns

tVHH VHH Rise and Fall Time Min 500 ns

tRSP

RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Figure 21. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

ESET#

tVIDR

VID

0 or 1.8

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

0 or 1.8 V

Figure 22. Temporary Sector Unprotect Timing Diagram

November 1, 2004 Am29SL160C 45

AC CHARACTERISTICS

Figure 23. Accelerated Program Timing Diagram

P#/ACC

tVHH

VHH

VIL or VI

tVHH

VIL or VIH

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

ESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Protect/Unprotect Verify

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 24. Sector Protect/Unprotect Timing Diagram

46 Am29SL160C November 1, 2004

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Notes:

1. Not 100% tested.

2. See “Erase And Programming Performance” on page 48 for more information.

Parameter Speed Options

JEDEC Std Description -90 -100 -120 -150 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 150 ns

tAVEL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 50 50 60 70 ns

tDVEH tDS Data Setup Time Min 50 50 60 70 ns

tEHDX tDH Data Hold Time Min 0 ns

tGHEL tGHEL

Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 50 50 60 70 ns

tEHEL tCPH CE# Pulse Width High Min 30 ns

tWHWH1 tWHWH1

Programming Operation

(Notes 1, 2)

Byte Typ 10

µs

Word Typ 12

Accelerated Program Operation, Byte or Word

(Note 2) Typ 8 µs

tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 2 sec

November 1, 2004 Am29SL160C 47

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written, DOUT = data written

2. Figure indicates the last two bus cycles of command sequence.

3. Word mode address used as an example.

Figure 25. Alternate CE# Controlled Write Operation Timings

48 Am29SL160C November 1, 2004

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 2.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 1.8 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 12, on page 28 for further information on command definitions.

6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time.

TSOP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 2 15 s Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time 70 s

Byte Programming Time 10 300 µs

Excludes system level

overhead (Note 5)

Word Programming Time 12 360 µs

Accelerated Program Time, Word/Byte 8 240 µs

Chip Programming Time

(Note 3)

Byte Mode 20 160 s

Word Mode 14 120 s

Description Min Max

Input voltage with respect to VSS on all pins except I/O pins

(including A9, OE#, and RESET#) –1.0 V 11.0 V

Input voltage with respect to VSS on all I/O pins –0.5 V VCC + 0.5 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C10 Years

125°C20 Years

November 1, 2004 Am29SL160C 49

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP

* For reference only. BSC is an ANSI standard for Basic Space Centering.

Dwg rev AA; 10/99

50 Am29SL160C November 1, 2004

PHYSICAL DIMENSIONS

FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

8 x 9 mm package

Dwg rev AF; 10/99

November 1, 2004 Am29SL160C 51

REVISION SUMMARY

Revision A (December 1998)

Initial release.

Revision A+1 (January 1999)

Distinctive Characteristics

WP#/ACC pin: In the third subbullet, deleted reference

to increased erase performance.

Device Bus Operations

Accelerated Program and Erase Operations: Deleted

all references to accelerated erase.

Sector/Sector Block Protection and Unprotection:

Changed section name and text to include tables and

references to sector block protection and unprotection.

AC Characteristics

Accelerated Program Timing Diagram: Deleted refer-

ence in title to accelerated erase.

Revision A+2 (March 23, 1999)

Connection Diagrams

Corrected the TSOP pinout on pins 13 and 14.

Revision A+3 (April 12, 1999)

Global

Modified the description of accelerated programming to

emphasize that it is intended only to speed in-system

programming of the device during the system produc-

tion process.

Distinctive Characteristics

Secured Silicon (SecSi) Sector bullet: Added the 8-

byte unique serial number to description.

Device Bus Operations table

Modified Note 3 to indicate sector protection behavior

when VIH is asserted on WP#/ACC. Applied Note 3 to

the WP#/ACC column for write operations.

Ordering Information

Added the “N” designator to the optional processing

section.

Secured Silicon (SecSi) Sector Flash Memory

Region

Modified explanatory text to indicate that devices now

have an 8-byte unique ESN in addition to the 16-byte

random ESN. Added table for address range

clarification.

Revision A+4 (May 14, 1999)

Global

Deleted all references to the unique ESN.

Revision A+5 (July 23, 1999)

Global

Added 90 ns speed option.

Revision A+6 (September 1, 1999)

AC Characteristics

Hardware Reset (RESET#) table: Deleted tRPD specifi-

cation. Erase/Program Operations table: Deleted tOES

specification.

Revision A+7 (September 7, 1999)

Distinctive Characteristics

Ultra low power consumption bullet: Corrected values

to match those in the DC Characteristics table.

AC Characteristics

Alternate CE# Controlled Erase/Program Operations:

Deleted tOES specification.

Revision B (December 14, 1999)

AC Characteristics—Figure 17. Program

Operations Timing and Figure 18. Chip/Sector

Erase Operations

Deleted tGHWL and changed OE# waveform to start at

high.

Physical Dimensions

Replaced figures with more detailed illustrations.

Revision C (February 21, 2000)

Removed “Advance Information” designation from data

sheet. Data sheet parameters are now stable; only

speed, package, and temperature range combinations

are expected to change in future revisions.

Device Bus Operations table

Changed standby voltage specification to VCC ± 0.2 V.

Standby Mode

Changed standby voltage specification to VCC ± 0.2 V.

DC Characteristics table

Changed test conditions for ICC3, ICC4, ICC5 to VCC ± 0.2

Revision C+1 (November 14, 2000)

Global

Added dash to speed options and OPNs. Added table

of contents.

AC Characteristics—Read Operations

Changed tDF to 16 ns for all speeds.

52 Am29SL160C November 1, 2004

Revision C+2 (June 11, 2002)

Secured Silicon (SecSi) Sector Flash Memory

Region

Deleted reference to A-1 not being used in addressing,

and to address bits that are don’t cares. In Tab le 7 ,

changed lower address bit for user-defined code to 08h

(word mode) and 010h (byte mode).

Revision C+3 (November 1, 2004)

Global

Added Colophon.

Added reference links.

Ordering Information

Added temperature ranges for Pb-free Package

Valid Combinations for TSOP Packages

Added ED, and EF combinations.

Valid Combinations for FBGA Packages

Added WCD, and WCF to Order Number column, and

added D, and F to Package Marking column.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable

to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operat-

ing conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the

prior authorization by the respective government entity will be required for export of those products.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies