MEMSIC MMC246xMT Rev D Page 11 of 15 5/30/2013
measurement (collect x and y data). A STOP condition
indicates the end of the write operation.
Fourth cycle: The Master device sends a START
command followed by the MEMSIC device’s seven bit
address, and finally the eighth bit set low to indicate a
WRITE. An Acknowledge should be send by the
MEMSIC device in response.
Fifth cycle: The Master device sends the MEMSIC
device’s Status Register [00000110] as the address to
read.
Sixth cycle: The Master device sends a START
command followed by the MEMSIC device’s seven bit
address, and finally the eighth bit set high to indicate a
READ. An Acknowledge should be send by the
MEMSIC device in response.
Seventh cycle: The Master device cycles the SCL line.
This causes the Status Register data to appear on
SDA line. Continuously read the Status Register until
the Meas Done bit (bit 0) is set to ‘1’. This indicates
that data for the x and y sensors is available to be
read.
Eighth cycle: The Master device sends a START
command followed by the MEMSIC device’s seven bit
address, and finally the eighth bit set low to indicate a
WRITE. An Acknowledge should be send by the
MEMSIC device in response.
Ninth cycle: The Master device sends a [00000000]
(Xout LSB register address) as the register address to
read.
Tenth cycle: The Master device calls the MEMSIC
device’s address with a READ (8
th
SCL cycle SDA line
high). An Acknowledge should be send by the
MEMSIC device in response.
Eleventh cycle: Master device continues to cycle the
SCL line, and each consecutive byte of data from the
X and Y registers should appear on the SDA line. The
internal memory address pointer automatically moves
to the next byte. The Master device acknowledges
each. Thus:
Eleventh cycle: LSB of X channel.
Twelfth cycle: MSB of X channel.
Thirteenth cycle: LSB of Y channel.
Fourteenth cycle: MSB of Y channel.
Master ends communications by NOT sending an
‘Acknowledge’ and also follows with a ‘STOP’
command.
EXAMPLE OF SET
First cycle: A START condition is established by the
Master Device followed by a call to the slave address
[0110xxx] with the eighth bit held low to indicate a
WRITE request. Note: [xxx] is determined by factory
programming and a total of 8 different addresses are
available.
Second cycle: After an acknowledge signal is received
by the master device (The MEMSIC device pulls the
SDA line low during the 9
th
SCL pulse), the master
device sends [00000111] as the target address
(Internal Control Register 0). The MEMSIC device
should acknowledge receipt of the address (9
th
SCL
pulse).
Third cycle: The Master device writes to the MEMSIC
device’s Internal Control Register 0 the code
[10000000] (Refill Cap) to prepare for SET action.*
A minimum of 50ms wait should be provided to allow
the MEMSIC device to finish its preparation for the
SET action.
Fourth cycle: The Master device writes to the
MEMSIC device’s Internal Control 0 register the code
[00100000] (SET bit) to initiate a SET action. The
MEMSIC device should send an Acknowledge.
EXAMPLE OF RESET*
First cycle: A START condition is established by the
Master Device followed by a call to the slave address
[0110xxx] with the eighth bit held low to indicate a
WRITE request. Note: [xxx] is determined by factory
programming and a total of 8 different addresses are
available.
Second cycle: After an acknowledge signal is received
by the master device (The MEMSIC device pulls the
SDA line low during the 9
th
SCL pulse), the master
device sends [00000111] as the target address
(Internal Control Register 0). The MEMSIC device
should acknowledge receipt of the address (9
th
SCL
pulse).
Third cycle: The Master device writes to the MEMSIC
device’s Internal Control Register 0 the code
[10000000] (Refill Cap) to prepare for RESET action.
A minimum of 50ms wait should be provided to allow
the MEMSIC device to finish its preparation for the
RESET action.
Fourth cycle: The Master device writes to the
MEMSIC device’s Internal Control 0 register the code
[01000000] (RESET bit) to initiate a RESET action.
The MEMSIC device should send an Acknowledge.
At this point, the MEMSIC AMR sensors have been
conditioned for optimum performance and data
measurements can commence.
Note *: The RESET action can be skipped for most
applications