W957D6HB 128Mb Async./Burst/Sync./A/D MUX TABLE OF CONTENTS 1. GENERAL DESCRIPTION .......................................................................................................... 3 2. FEATURES.................................................................................................................................. 3 3. ORDERING INFORMATION ....................................................................................................... 3 4. PIN CONFIGURATION ................................................................................................................ 4 4.1 Ball Assignment ............................................................................................................................... 4 5. PIN DESCRIPTION ..................................................................................................................... 5 5.1 Signal Description ............................................................................................................................ 5 6. BLOCK DIAGRAM ...................................................................................................................... 6 7. INSTRUCTION SET .................................................................................................................... 7 7.1 Bus Operation .................................................................................................................................. 7 8. FUNCTIONAL DESCRIPTION .................................................................................................... 8 8.1 Power Up Initialization ..................................................................................................................... 8 8.1.1 Power-Up Initialization Timing ................................................................................................................... 8 8.2 Bus Operating Modes ...................................................................................................................... 8 8.2.1 Asynchronous Modes ................................................................................................................................ 8 8.2.1.1 READ Operation (ADV# LOW)......................................................................................................................... 9 8.2.1.2 WRITE Operation (ADV# LOW) ....................................................................................................................... 9 8.2.2 Burst Mode Operation.............................................................................................................................. 10 8.2.2.1 Burst Mode READ (4-word burst) ................................................................................................................... 10 8.2.2.2 Burst Mode WRITE (4-word burst) ................................................................................................................. 11 8.2.2.3 Refresh Collision During Variable-Latency READ Operation ......................................................................... 12 8.2.3 Mixed-Mode Operation ............................................................................................................................ 13 8.2.4 WAIT Operation ....................................................................................................................................... 13 8.2.4.1 Wired-OR WAIT Configuration ....................................................................................................................... 13 8.2.5 LB#/ UB# Operation................................................................................................................................. 14 8.3 Low Power Operation .................................................................................................................... 14 8.3.1 Standby Mode Operation ......................................................................................................................... 14 8.3.2 Temperature Compensated Refresh ....................................................................................................... 14 8.3.3 Partial-Array Refresh ............................................................................................................................... 14 8.3.4 Deep Power-Down Operation .................................................................................................................. 14 8.4 Registers ....................................................................................................................................... 15 8.4.1 Access Using CRE .................................................................................................................................. 15 8.4.1.1 Configuration Register WRITE Asynchronous Mode Followed by READ Operation ...................................... 15 8.4.1.2 Configuration Register WRITE Synchronous Mode Followed by READ Operation ........................................ 16 8.4.1.3 Configuration Register READ Asynchronous Mode Followed by READ ARRAY Operation ........................... 17 8.4.1.4 Configuration Register READ Synchronous Mode Followed by READ ARRAY Operation ............................ 18 8.4.2 Software Access ...................................................................................................................................... 19 8.4.2.1 Load Configuration Register ........................................................................................................................... 19 8.4.2.2 Read Configuration Register .......................................................................................................................... 20 8.4.3 Bus Configuration Register ...................................................................................................................... 20 8.4.3.1 Bus Configuration Register Definition ............................................................................................................ 21 8.4.3.2 Burst Length (BCR[2:0]) Default = Continuous Burst ..................................................................................... 22 8.4.3.3 Burst Wrap (BCR[3]) Default = No Wrap ........................................................................................................ 22 8.4.3.4 Sequence and Burst Length ........................................................................................................................... 23 8.4.3.5 Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength ........................................................... 24 8.4.3.6 Table of Drive Strength ................................................................................................................................... 24 8.4.3.7 WAIT Configuration. (BCR[8]) ........................................................................................................................ 24 8.4.3.8 WAIT Polarity (BCR[10])................................................................................................................................. 24 8.4.3.9 WAIT Configuration During Burst Operation ................................................................................................... 25 8.4.3.10 Latency Counter (BCR[13:11]) Default = Three Clock Latency .................................................................... 25 8.4.3.11 Initial Access Latency (BCR[14]) Default = Variable ..................................................................................... 25 8.4.3.12 Allowed Latency Counter Settings in Variable Latency Mode ....................................................................... 25 Publication Release Date: Aug. 17, 2016 Revision: A01-005 -1- W957D6HB 8.4.3.13 Latency Counter (Variable Initial Latency, No Refresh Collision) .................................................................. 26 8.4.3.14 Allowed Latency Counter Settings in Fixed Latency Mode ........................................................................... 26 8.4.3.15 Latency Counter (Fixed Latency) ................................................................................................................. 27 8.4.3.16 Operating Mode (BCR[15]) ........................................................................................................................... 27 8.4.4 Refresh Configuration Register ............................................................................................................... 28 8.4.4.1 Refresh Configuration Register Mapping ....................................................................................................... 28 8.4.4.2 Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh ....................................................................... 28 8.4.4.3 Address Patterns for PAR (RCR [4] = 1)......................................................................................................... 29 8.4.4.4 Deep Power-Down (RCR[4]) Default = DPD Disabled ................................................................................... 29 8.4.5 Device Identification Register .................................................................................................................. 29 8.4.5.1 Device Identification Register Mapping .......................................................................................................... 29 9. ELECTRICAL CHARACTERISTIC ........................................................................................... 30 9.1 Absolute Maximum DC, AC Ratings .............................................................................................. 30 9.2 Electrical Characteristics and Operating Conditions ....................................................................... 30 9.3 Deep Power-Down Specifications .................................................................................................. 31 9.4 Partial Array Self Refresh Standby Current .................................................................................... 31 9.5 Capacitance ................................................................................................................................... 31 9.6 AC Input-Output Reference Wave form.......................................................................................... 31 9.7 AC Output Load Circuit .................................................................................................................. 31 10. TIMING REQUIRMENTS ......................................................................................................... 32 10.1 Read, Write Timing Requirements ............................................................................................... 32 10.1.1 Asynchronous READ Cycle Timing Requirements ............................................................................... 32 10.1.2 Burst READ Cycle Timing Requirements .............................................................................................. 33 10.1.3 Asynchronous WRITE Cycle Timing Requirements .............................................................................. 34 10.1.4 Burst WRITE Cycle Timing Requirements ............................................................................................ 35 10.2 TIMING DIAGRAMS .................................................................................................................... 36 10.2.1 Initialization Period................................................................................................................................. 36 10.2.2 DPD Entry and Exit Timing Parameters ................................................................................................ 36 10.2.3 Initialization and DPD Timing Parameters ............................................................................................. 36 10.2.4 Asynchronous READ ............................................................................................................................. 37 10.2.5 Single Access Burst READ Operation - Variable Latency..................................................................... 38 10.2.6 Four Word Burst READ Operation-Variable Latency ............................................................................ 39 10.2.7 Single-Access Burst READ Operation-Fixed Latency ........................................................................... 40 10.2.8 Four Word Burst READ Operation-Fixed Latency ................................................................................. 41 10.2.9 Burst READ Terminate at End-of-Row (Wrap Off) ................................................................................ 42 10.2.10 Burst READ Row Boundary Crossing ................................................................................................. 43 10.2.11 Asynchronous WRITE ......................................................................................................................... 44 10.2.12 Burst WRITE Operation--Variable Latency Mode .............................................................................. 45 10.2.13 Burst WRITE Operation-Fixed Latency Mode ..................................................................................... 46 10.2.14 Burst WRITE Terminate at End of Row (Wrap Off) ............................................................................. 47 10.2.15 Burst WRITE Row Boundary Crossing ................................................................................................ 48 10.2.17 Asynchronous WRITE Followed by Burst READ ................................................................................ 50 10.2.18 Burst READ Followed by Asynchronous WRITE ................................................................................ 51 10.2.19 Asynchronous WRITE Followed by Asynchronous READ .................................................................. 52 11. PACKAGE DESCRIPTION ..................................................................................................... 53 11.1 Package Dimension ..................................................................................................................... 53 12. REVISION HISTORY ............................................................................................................... 54 Publication Release Date: Aug. 17, 2016 Revision: A01-005 -2- W957D6HB 1. GENERAL DESCRIPTION Winbond x16 ADMUX products are high-speed, CMOS pseudo-static random access memory developed for lowpower, portable applications. The device has a DRAM core organized. These devices are a variation of the industrystandard Flash control interface, with a multiplexed address/data bus. The multiplexed address and data functionality dramatically reduce the required signal count, and increase READ/WRITE bandwidth. For seamless operation on a burst Flash bus, Winbond x16 ADMUX products incorporate a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device READ/WRITE performance. Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the Winbond x16 ADMUX device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. Winbond x16 ADMUX products include two mechanisms to minimize standby current. Partial-array refresh (PAR) enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature-compensated refresh (TCR) uses an on-chip sensor to adjust the refresh rate to match the device temperature--the refresh rate decreases at lower temperatures to minimize current consumption during standby. The system-configurable refresh mechanisms are accessed through the RCR. Winbond x16 ADMUX device is compliant with the industry-standard CellularRAM 1.5 x16 A/D MUX. 2. FEATURES * Supports asynchronous, page, and burst operations * Low-power features * VCC, VCCQ Voltages: On-chip temperature compensated refresh (TCR) 1.7V-1.95V VCC Partial array refresh (PAR) 1.7V-1.95V VCCQ Deep power-down (DPD) mode * Random access time: 70ns * Package: 54 Ball VFBGA * Burst mode READ and WRITE access: *16-bit multiplexed address/data bus *Operating temperature range: 4, 8, 16, or 32 words, or continuous burst -40C TCASE 85C Burst wrap or sequential Max clock rate: 133 MHz (tCLK = 7.5ns) * Low power consumption: Asynchronous READ: <35 mA Continuous burst READ: <40 mA Standby current: 300 A 3. ORDERING INFORMATION Part Number VDD/VDDQ I/O Width Type W957D6HBCX7I 1.8/1.8 x16 54VFBGA Others CRAM A/D Mux,133MHz, -40C~85C Publication Release Date: Aug. 17, 2016 Revision: A01-005 -3- W957D6HB 4. PIN CONFIGURATION 4.1 Ball Assignment 1 2 3 4 5 6 A LB# OE# NC NC NC CRE B ADQ8 UB# NC NC CE# ADQ0 C ADQ9 ADQ10 NC NC ADQ1 ADQ2 D VSSQ ADQ11 A17 NC ADQ3 VCC E VCCQ ADQ12 A21 A16 ADQ4 VSS F ADQ14 ADQ13 NC NC ADQ5 ADQ6 G ADQ15 A19 NC NC WE# ADQ7 H A18 NC NC NC NC A20 J WAIT CLK ADV# A22 NC NC (Top View) Pin Configuration Publication Release Date: Aug. 17, 2016 Revision: A01-005 -4- W957D6HB 5. PIN DESCRIPTION 5.1 Signal Description Symbol Type Description Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are A[max:16] Input internally latched during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the BCR or the RCR. A[max:16]=A[22:16] (128Mb) Clock: Synchronizes the memory to the system operating frequency during synchronous CLK (Note 1) Input operations. When configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is active. CLK must be static (HIGH or LOW) during asynchronous access READ and WRITE operations when burst mode is enabled. ADV# (Note 1) Input Address valid: Indicates that a valid address is present on the address inputs. Addresses are latched on the rising edge of ADV# during asynchronous READ and WRITE operations. Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and CRE Input CE# Input OE# Input WE# Input LB# Input Lower byte enable: DQ[7:0] UB# Input Upper byte enable: DQ[15:8] READ operations access the RCR, BCR, or DIDR. Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby mode. Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or to the memory array. Address/data I/Os: These pins are a multiplexed address/data bus. As inputs for addresses, A/DQ[15:0] Input/Output these pins behave as A[15:0]. A[0] is the LSB of the 16-bit word address within the CellularRAM device. Address, RCR, and BCR values are loaded with ADV# LOW. Data is input or output when ADV# is HIGH. WAIT: Provides data-valid feedback during burst READ and WRITE operations. WAIT is WAIT (Note 1) Output used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is also asserted at the end of a row unless wrapping within the burst length. WAIT should be ignored during asynchronous operations. WAIT is High-Z when CE# is HIGH. NC -- Reserved for future use. VCC Supply Device power supply: (1.70V-1.95V) Power supply for device core operation. VCCQ Supply I/O power supply: (1.70V-1.95V) Power supply for input/output buffers. VSS Supply VSS must be connected to ground. VSSQ Supply VSSQ must be connected to ground. Note: 1. When using asynchronous mode exclusively, CLK can be tied to VSSQ or VCCQ. WAIT should be ignored during asynchronous mode operations. Publication Release Date: Aug. 17, 2016 Revision: A01-005 -5- W957D6HB 6. BLOCK DIAGRAM A[max:16] Address Decode Logic DRAM Memory Array Refresh Configuration Input / Output MUX and A/DQ [7:0] A/DQ [15:8] Buffers Register (RCR) Device ID Register (DIDR) Bus Configuration Register (BCR) CE# WE# OE# CLK ADV# CRE WAIT LB#/UB# Control Logic Internal External Publication Release Date: Aug. 17, 2016 Revision: A01-005 -6- W957D6HB 7. INSTRUCTION SET 7.1 Bus Operation Asynchronous Mode BCR[15] = 1 (default) CE# OE# WE# CRE LB#/ UB# WAIT*2 A/DQ[15:0]*3 Notes X L L H L L Low-Z Data out 4 Active X L X L L L High-Z Data in 4 Standby H or L X H X X L X High-Z High-Z 5, 6 Idle X X L X X L X Low-Z X 4, 6 Configuration register WRITE Active X L H L H X Low-Z High-Z Configuration register READ Active x L L H H L Low-Z Config. reg. out Deep powerdown X X H X X X X High-Z High-Z 10 Power CLK*1 ADV# CE# OE# WE# CRE LB#/ UB# WAIT*2 A/DQ[15:0]*3 Notes Power CLK Read Active Write Standby No operation DPD Burst Mode BCR[15] = 0 ADV# Read Active H or L L L H L L Low-Z Data out 4, 7 Write Active H or L L X L L L High-Z Data in 4 Standby H or L X H X X L X High-Z High-Z 5, 6 Idle H or L X L X X L X Low-Z X 4, 6 Standby No operation Initial burst READ Active L L X H L L Low-Z Address 4, 8 Initial burst WRITE Active L L H L L X Low-Z Address 4, 8 Burst continue Active H L X X X L Low-Z Data in or Data out 4, 8 Configuration register WRITE Active L L H L H X Low-Z High-Z 8, 9 Configuration register READ Active L L L H H L Low-Z Config. reg. out 8, 9 X H X X X X High-Z High-Z 10 DPD Deep powerdown L Notes: 1. With burst mode enabled, CLK must be static (HIGH or LOW) during asynchronous READs and asynchronous WRITEs and to achieve standby power during standby and DPD modes. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in select mode, DQ[7:0] are enabled. When only UB# is in the select mode, DQ[15:8] are enabled. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby current. 7. When the BCR is configured for synchronous mode, synchronous READ and WRITE and asynchronous WRITE and READ are supported. 8. Burst mode operation is initialized through the bus configuration register (BCR[15]) 9. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as indicated by WAIT). 10. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CE# transitions from HIGH to LOW. Publication Release Date: Aug. 17, 2016 Revision: A01-005 -7- W957D6HB 8. FUNCTIONAL DESCRIPTION In general, ADMUX PSRAM devices are high-density alternatives to SRAM and Pseudo SRAM products, popular in low-power, portable applications. Both devices implement a multiplexed address/data bus. This multiplexed configuration supports greater bandwidth through the x16 data bus, yet still reduces the required signal count. The ADMUX PSRAM bus interface supports both asynchronous and burst mode transfers. 8.1 Power Up Initialization ADMUX PRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will configure the BCR and the RCR with their default settings. VCC and VCCQ must be applied simultaneously. When they reach a stable level at or above 1.7V, the device will require 150s to complete its selfinitialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. 8.1.1 Power-Up Initialization Timing VCC=1.7V tPU VCC VCCQ Device ready for normal operation Device Initialization 8.2 Bus Operating Modes This asynchronous/burst ADMUX PSRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications. This bus interface supports asynchronous, and burst mode read and write transfers. The specific interface supported is defined by the value loaded into the BCR. 8.2.1 Asynchronous Modes Using industry-standard SRAM control signals (CE#, ADV#, OE#, WE#, and LB#/UB#). READ operations are initiated by bringing CE#, ADV#, and LB#/UB# LOW while keeping OE# and WE# HIGH, and driving the address onto the A/DQ bus. ADV# is taken HIGH to capture the address, and OE# is taken LOW. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations occur when CE#, ADV#, WE#, and LB#/UB# are driven LOW with the address on the A/DQ bus. ADV# is taken HIGH to capture the address, then the WRITE data is driven onto the bus. During asynchronous WRITE operations, the OE# level is a "Don't Care," and WE# will override OE#; however, OE# must be HIGH while the address is driven onto the A/DQ bus. The data to be written is latched on the rising edge of CE#, WE#, UB#, or LB# (whichever occurs first). During asynchronous operation with burst mode enabled, the CLK input must be held static (LOW). WAIT will be driven during asynchronous READs, and its state should be ignored. WE# LOW time must be limited to tCEM. Publication Release Date: Aug. 17, 2016 Revision: A01-005 -8- W957D6HB 8.2.1.1 READ Operation (ADV# LOW) A[max:16] Address CE# OE# WE# A/DQ[15:0] Address High - Z DATA ADV# LB#/UB# DON'T CARE 8.2.1.2 WRITE Operation (ADV# LOW) A[max:16] Address CE# OE# <tCEM WE# A/DQ[15:0] Address DATA ADV# LB#/UB# DON'T CARE Undefined Publication Release Date: Aug. 17, 2016 Revision: A01-005 -9- W957D6HB 8.2.2 Burst Mode Operation Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. .After CE# goes LOW; the address to access is latched on the first CLK edge after ADV# LOW. During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH) or WRITE (WE# =LOW). 8.2.2.1 Burst Mode READ (4-word burst) CLK A[max:16] Valid Address ADV# Latency Code 2(3 clocks) CE# OE# WE# LB#/UB# A/DQ[15:0] Valid Address D0 D1 D2 D3 WAIT READ burst identified (WE# = HIGH) Invalid Don't Care Undefined Note: Non-default BCR settings for burst mode READ (4-word burst): fixed or variable latency, Latency code 2 (3 clocks), WAIT active Low, WAIT asserted during delay. Diagram is representative of variable latency with no refresh collision or fixed-latency access. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 10 - W957D6HB 8.2.2.2 Burst Mode WRITE (4-word burst) CLK A[max:16] Valid Address ADV# Latency Code 2(3 clocks) CE# OE# WE# LB#/UB# A/DQ[15:0] Valid Address D0 D1 D2 D3 WAIT Don't Care WRITE burst identified (WE# = LOW) Note: Non-default BCR settings for burst mode WRITE (4-word burst): fixed or variable latency, latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 11 - W957D6HB The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of 4, 8, 16, or 32 words. Continuous bursts have the ability to start at a specified address and burst to the end of the address. It goes back to the first address and continues to burst when continuous bursts meet the end of address. The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and ADMUX PSRAM device. The initial latency for READ operations can be configured as fixed or variable (WRITE operations always use fixed latency). Variable latency allows the ADMUX PSRAM to be configured for minimum latency at high clock frequencies, but the controller must monitor WAIT to detect any conflict with refresh cycles. Fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions. The initial latency time and clock speed determine the latency count setting. Fixed latency is used when the controller cannot monitor WAIT. Fixed latency also provides improved performance at lower clock frequencies. The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out of) the memory. WAIT will again be asserted at the boundary of the row, unless wrapping within the burst length. With wrap off, the ADMUX PSRAM device will restore the previous row's data and access the next row, WAIT will be deasserted, and the burst can continue across the row boundary. If the burst is to terminate at the row boundary, CE# must go HIGH within 2 clocks of the last data. CE# must go HIGH before any clock edge following the last word of a defined-length burst WRITE. The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. If a burst suspension will cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle. 8.2.2.3 Refresh Collision During Variable-Latency READ Operation CLK VIH VIL A[max:16] VIH VIL Valid Address ADV# VIH VIL CE# VIH VIL OE# VIH VIL WE# VIH VIL LB#/UB# VIH VIL A/DQ[15:0] VIH VIL WAIT VOH VOL Valid Address VOH D0 D1 D2 D3 VOL High-Z Additional WAIT satates inserted to allow refresh completion Undefined Don't Care Note: Non-default BCR settings for refresh collision during variable-latency READ operation: latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 12 - W957D6HB 8.2.3 Mixed-Mode Operation The device supports a combination of synchronous WRITE / READ and asynchronous WRITE / READ operations when the BCR is configured for synchronous operation. The asynchronous WRITE operations require that the clock (CLK) remain static (HIGH or LOW) during the entire sequence. The ADV# signal can be used to latch the target address, or it can remain LOW during the entire WRITE operation. CE# can remain LOW when transitioning between mixed-mode operations with fixed latency enabled; however, the CE# LOW time must not exceed tCEM. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory controllers. 8.2.4 WAIT Operation The WAIT output on a ADMUX PSRAM device is typically connected to a shared, system level WAIT signal. The shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. 8.2.4.1 Wired-OR WAIT Configuration External Pull-Up/ Pull-Down Resistor CellularRAM WAIT READY Processor WAIT WAIT Other Device Other Device When a READ or WRITE operation has been initiated, WAIT goes active to indicate that the ADMUX PSRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the ADMUX PSRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges. During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE# HIGH during this initial latency may cause data corruption. When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for burst READ operations launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the refresh has completed. When the refresh operation has completed, the burst READ operation will continue normally. WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary. The WAIT assertion allows time for the new row to be accessed. WAIT will be asserted after OE# goes LOW during asynchronous READ operations. WAIT will be High-Z during asynchronous WRITE operations. WAIT should be ignored during all asynchronous operations. By using fixed initial latency (BCR[14] = 1), this ADMUX PSRAM device can be used in burst mode without monitoring the WAIT signal. However, WAIT can still be used to determine when valid data is available at the start of the burst and at the end of the row. If WAIT is not monitored, the controller must stop burst accesses at row boundaries on its own. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 13 - W957D6HB 8.2.5 LB#/ UB# Operation The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE operations, any disabled bytes will not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. LB# and UB# must be LOW during READ cycles. When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW. 8.3 Low Power Operation 8.3.1 Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of a READ or WRITE operation, or when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the address or control inputs. 8.3.2 Temperature Compensated Refresh Temperature-compensated refresh (TCR) allows for adequate refresh at different temperatures. This ADMUX PSRAM device includes an on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The device continually monitors the temperature to select an appropriate self-refresh rate. 8.3.3 Partial-Array Refresh Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map. READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When additional portions of the array need to be re-enabled, the new portions are available immediately after the completion of the WRITE cycle that updates the RCR with the new configuration. 8.3.4 Deep Power-Down Operation Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage provided by the AD MUX PSRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the AD MUX PSRAM device will require 150s to perform an initialization procedure before normal operations can resume. During this 150s period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. DPD can be enabled by writing to the RCR using CRE or the software access sequence; DPD starts when CE# goes HIGH. DPD is disabled the next time CE# goes LOW and stays LOW for at least 10s. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 14 - W957D6HB 8.4 Registers Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the ADMUX PSRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up, and can be updated any time the devices are operating in a standby state. A DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device configuration. The DIDR is read-only. 8.4.1 Access Using CRE The registers can be accessed using either a synchronous or an asynchronous operation when the control register enable (CRE) input is HIGH. When CRE is LOW, a READ or WRITE operation will access the memory array. The configuration register values are written via addresses A[max:16] and ADQ[15:0]. In an asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV#,CE#, or WE#, whichever occurs first; LB# and UB# are "Don't Care." The BCR is accessed when A[19:18] are 10b; the RCR is accessed when A[19:18] are 00b. The DIDR is read when A[19:18] are 01b. For reads, address inputs other than A[19:18] are "Don't Care", and register bits 15:0 are output on DQ[15:0]. Immediately after performing a configuration register READ or WRITE operation, reading the memory array is highly recommended. 8.4.1.1 Configuration Register WRITE Asynchronous Mode Followed by READ Operation A[max:16] (except A[19:18]) tAVH tAVS 1 Address OPCODE Select controlr register A[19:18] CRE Address tAVS tAVH ADV# tVP CE# tCPH Initiate control register access tCW OE# tWP Write address bus value to control register WE# LB#/UB# A/DQ[15:0] OPCODE Address Valid Data Don't Care Note: 1. A[19:18] = 00b to load RCR, and 10b to load BCR. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 15 - W957D6HB 8.4.1.2 Configuration Register WRITE Synchronous Mode Followed by READ Operation CLK Latch control register value A[max:16] (except A[19:18]) tHD tSP A[19:18] Address OPCODE Latch control register address 2 Address tSP CRE tHD tSP ADV# tHD tCBPH tCSP CE# Notes 3 OE# tSP WE# tHD LB#/UB# A/DQ[15:0] WAIT Address OPCODE High-Z Valid Data tKHTL High-Z Don't Care Notes: 1. Non-default BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. 2. A[19:18] = 00b to load RCR, and 10b to load BCR. 3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored--additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 16 - W957D6HB 8.4.1.3 Configuration Register READ Asynchronous Mode Followed by READ ARRAY Operation A[max:16] (except A[19:18]) Address tAVS tAVH 1 A[19:18] Address Select control register tAA tAVH CRE tAVS tAA ADV# tVP tCPH tAAVD CE# Initiate control register access tCPH tHZ tCO OE# tOE WE# tOHZ tBA tBHZ tOLZ LB#/UB# A/DQ[15:0] Valid CR Address Don't Care Valid Data Undefined Note: A[19:18] = 00b to read RCR, 10b to read BCR , and 01b to read DIDR. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 17 - W957D6HB 8.4.1.4 Configuration Register READ Synchronous Mode Followed by READ ARRAY Operation CLK Latch control register value A[max:16] (except A[19:18]) A[19:18] Address Latch control register address tSP 2 Address tHD tSP CRE tHD tSP ADV# tHD tABA tCBPH tCSP CE# Note 3 tHZ OE# tOHZ WE# tSP tBOE tHD LB#/UB# tOLZ tACLK tKOH A/DQ[15:0] WAIT Valid CR High-Z tKHTL Valid Data Address High-Z Don't Care Undefined Notes: 1. Non-default BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code 2 (3 clocks): WAIT active LOW; WAIT asserted during delay. 2. A[19:18]=00b to read RCR,10b to read BCR, and 01b to read DIDR. 3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored--additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 18 - W957D6HB 8.4.2 Software Access Software access of the registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be modified and all registers can be read using the software sequence. The configuration registers are loaded using a four-step sequence consisting of two asynchronous READ operations followed by two asynchronous WRITE operations. The read sequence is virtually identical except that an asynchronous READ is performed during the fourth operation. The address used during all READ and WRITE operations is the highest address of the ADMUX PSRAM device being accessed; the contents of this address are not changed by using this sequence. The data value presented during the third operation (WRITE) in the sequence defines whether the BCR, RCR, is to be accessed. If the data is 0000h, the sequence will access the RCR; if the data is 0001h, the sequence will access the BCR. During the fourth operation, ADQ[15:0] transfer data in to or out of bits 15:0 of the registers. The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However, the software nature of this access mechanism eliminates the need for CRE. If the software mechanism is used, CRE can simply be tied to VSS. The port line often used for CRE control purposes is no longer required. 8.4.2.1 Load Configuration Register READ CE# READ WRITE WRITE OE# WE# LB#/UB# ADV# A[max:16] Address (MAX) A/DQ[15:0] Address (MAX) Address (MAX) Address (MAX) Address (MAX) 0ns (min) XXXX Address (MAX) XXXX Address (MAX) Address (MAX) RCR:0000h BCR:0001h CR Value In Don't Care Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 19 - W957D6HB 8.4.2.2 Read Configuration Register READ CE# READ WRITE READ OE# WE# LB#/UB# ADV# A[max:16] Address (MAX) A/DQ[15:0] Address (MAX) Address (MAX) Address (MAX) Address (MAX) 0ns (min) XXXX Address (MAX) XXXX Address (MAX) Address (MAX) RCR:0000h BCR:0001h DIDR:0002h CR Value Out Don't Care 8.4.3 Bus Configuration Register The BCR defines how the ADMUX PSRAM device interacts with the system memory bus. At power-up, the BCR is set to 9D1Fh. The BCR is accessed with CRE HIGH and A[19:18] = 10b, or through the register access software sequence with A/DQ = 0001h on the third cycle. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 20 - W957D6HB 8.4.3.1 Bus Configuration Register Definition A[max:20] A[19:18] max-20 19-18 Register Reserved Select 17-16 Reserved A/DQ14 A/DQ[13:11] 14-11 15 Operating Latency Initial Latency Mode Counter Must be set to "0" Variable All must be set to "0" A/DQ15 A[17:16] 10 WAIT Polarity A/DQ9 A/DQ8 9 Reserved 8 A/DQ7 A/DQ6 7 WAIT Configuration (WC) Must be set to "0" A/DQ5 6 5 Reserved Reserved Must be set to "0" Must be set to "0" A/DQ3 A/DQ4 4 A/DQ[2:0] 3 2-0 Burst Wrap(BW)* Drive Strength Burst Length(BL)* Latency BCR[14] BCR[13] BCR[12] BCR[11] 0 0 1 0 Code 2 BCR[3] Burst Wraps (Note1) 0 0 1 1 Code 3 (default) 0 Burst wraps within the burst length 0 1 0 0 Code 4 1 Burst no wraps (default) 0 Fixed A/DQ10 All others Reserved 1 0 1 0 1 0 1 1 Code 3 1 1 0 0 Code 4 1 1 0 1 1 1 1 1 0 0 1 Code 2 Drive Strength BCR[5] BCR[4] 0 0 Full Code 5 0 1 1/2 (default) 0 Code 6 1 0 1/4 0 Code 8 1 1 Reserved All others Reserved WAIT Polarity BCR[8] WAIT Configuration 0 Active Low 0 Asserted during delay 1 Active HIGH (default) 1 Asserted one data cycle before delay (default) BCR[10] BCR[15] Operating Mode 0 Synchronous burst access mode 1 Asynchronous access mode (default) BCR[19] BCR[18] Register Select 0 0 Select RCR 1 0 Select BCR 0 1 Select DIDR BCR[2] BCR[1] BCR[0] 0 0 1 4 words 0 1 0 8 words 0 1 1 16 words 1 0 0 32 words 1 1 Continuous burst (default) 1 Others Burst Length (Note1) Reserved Notes: 1. Burst wrap and length apply to both READ and WRITE operations. 2. Reserved bits must be set to zero. Reserved bits not set to zero will affect device functionality. BCR[15:0] will be read back as written. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 21 - W957D6HB 8.4.3.2 Burst Length (BCR[2:0]) Default = Continuous Burst Burst lengths define the number of words the device outputs during burst READ and WRITE operations. The device supports a burst length of 4, 8, 16, or 32 words. The device can also be set in continuous burst mode where data is output sequentially without regard to address boundaries; the internal address wraps to 000000h if the device is read past the last address. 8.4.3.3 Burst Wrap (BCR[3]) Default = No Wrap The burst-wrap option determines if a 4-, 8-, 16-, or 32-word READ or WRITE burst wraps within the burst length, or steps through sequential addresses. If the wrap option is not enabled, the device accesses data from sequential addresses without regard to address boundaries; the internal address wraps to 000000h if the device is read past the last address. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 22 - W957D6HB 8.4.3.4 Sequence and Burst Length Burst Wrap Start Addr 4-Word Burst Length 8-Word Burst Length 16-Word Burst Length 32-Word Burst Length Continuous Burst BCR[3] Wrap Decimal Linear Linear Linear Linear Linear 0 1 Yes No 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-...-29-30-31 0-1-2-3-4-5-6-... 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-...-30-31-0 1-2-3-4-5-6-7-... 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-...-31-0-1 2-3-4-5-6-7-8-... 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-...-0-1-2 3-4-5-6-7-8-9-... 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-...-1-2-3 4-5-6-7-8-9-10-... 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-...-2-3-4 5-6-7-8-9-10-11-... 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-...-3-4-5 6-7-8-9-10-11-12- 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-...-4-5-6 7-8-9-10-11-12-13-... ... ... ... ... 14 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-...-11-12-13 14-15-16-17-18-19-20-... 15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-...-12-13-14 15-16-17-18-19-20-21-... ... ... ... 30 30-31-0-...-27-28-29 30-31-32-33-34-... 31 31-0-1-...-28-29-30 31-32-33-34-35-... 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2...--29-30-31 0-1-2-3-4-5-6-... 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-...-30-31-32 1-2-3-4-5-6-7-... 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-...-31-32-33 2-3-4-5-6-7-8-... 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-...-32-33-34 3-4-5-6-7-8-9-... 4 4-5-6-7-8-9-1011 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-...-33-34-35 4-5-6-7-8-9-10-... 5 5-6-7-8-9-10-115-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20 12 5-6-7-...-34-35-36 5-6-7-8-9-10-11... 6 6-7-8-9-10-1112-13 7 7-8-9-10-11-127-8-9-10-11-12-13-14-...-17-18-19-20-21-22 13-14 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21 6-7-8-...-35-36-37 6-7-8-9-10-11-12... 7-8-9-...-36-37-38 7-8-9-10-11-12-13... ... ... ... ... 14 14-15-16-17-18-19-...-23-24-25-26-27-28-29 14-15-16-...-43-44-45 14-15-16-17-18-19-20-... 15 15-16-17-18-19-20-...-24-25-26-27-28-29-30 15-16-17-...-44-45-46 15-16-17-18-19-20-21-... ... ... ... 30 30-31-32-...-59-60-61 30-31-32-33-34-35-36-... 31 31-32-33-...-60-61-62 31-32-33-34-35-36-37-... Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 23 - W957D6HB 8.4.3.5 Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. The reduced-strength options are intended for stacked chip (Flash + ADMUX PSRAM) environments when there is a dedicated memory bus. The reduced-drive-strength option minimizes the noise generated on the data bus during READ operations. Full output drive strength should be selected when using a discrete ADMUX PSRAM device in a more heavily loaded data bus environment. Outputs are configured at half-drive strength during testing. 8.4.3.6 Table of Drive Strength BCR[5] BCR[4] Drive Strength Impedance Typ () Use Recommendation 0 0 Full 25-30 CL = 30pF to 50pF 0 1 1/2 (default) 50 CL = 15pF to 30pF 1 0 1/4 100 CL = 15pF or lower 1 1 Reserved 8.4.3.7 WAIT Configuration. (BCR[8]) Default =WAIT Transitions 1 Clock Before Data Valid/ Invalid The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively. When BCR[8] = 1, the WAIT signal transitions one clock period prior to the data bus going valid or invalid. 8.4.3.8 WAIT Polarity (BCR[10]) Default = WAIT Active HIGH The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state. The default value is BCR[10]=1, indicating WAIT active HIGH. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 24 - W957D6HB 8.4.3.9 WAIT Configuration During Burst Operation CLK BCR[8]=0 Data valid in current cycle WAIT BCR[8]=1 Data valid in next cycle WAIT A/DQ[15:0] Initial latency D1 D0 D2 D3 End of row Don't Care Note: Signals shown are for WAIT active LOW, no wrap. 8.4.3.10 Latency Counter (BCR[13:11]) Default = Three Clock Latency The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred. For allowable latency codes, see the following tables and figures. 8.4.3.11 Initial Access Latency (BCR[14]) Default = Variable Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be monitored to detect delays caused by collisions with refresh operations. Fixed initial access latency outputs the first data at a consistent time that allows for worst-case refresh collisions. The latency counter must be configured to match the initial latency and the clock frequency. It is not necessary to monitor WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency counter. 8.4.3.12 Allowed Latency Counter Settings in Variable Latency Mode Latency *1 Max Input CLK Frequency (MHz) BCR[13:11] Latency Configuration Code Normal Maximum with Refresh Collision 133 104 010 2 (3 clocks) 2 4 66 (15ns) 66 (15ns) 011 3(4clocks)--default 3 6 104 (9.62ns) 104 (9.62ns) 100 4 (5 clocks) 4 8 133 (7.5ns) -- Others Reserved -- -- -- -- Note: 1. Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 25 - W957D6HB 8.4.3.13 Latency Counter (Variable Initial Latency, No Refresh Collision) CLK A[max:16] Valid Address ADV# Code 2 A/DQ[15:0] Valid Output Valid Address Code 3 A/DQ[15:0] Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output (Default) Valid Address Code 4 A/DQ[15:0] Valid Address Don't Care Undefined 8.4.3.14 Allowed Latency Counter Settings in Fixed Latency Mode Max Input CLK Frequency (MHz) BCR[13:11] Latency Configuration Code Latency Count (N) 133 104 010 2 (3 clocks) 2 33 (30ns) 33 (30ns) 011 3 (4 clocks)--default 3 52 (19.2ns) 52 (19.2ns) 100 4 (5 clocks) 4 66 (15ns) 66 (15ns) 101 110 000 Others 5 (6 clocks) 6 (7 clocks) 8 (9 clocks) Reserved 5 6 8 -- 75 (13.3ns) 104 (9.62ns) 133 (7.5ns) -- 75 (13.3ns) 104 (9.62ns) -- -- Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 26 - W957D6HB 8.4.3.15 Latency Counter (Fixed Latency) N-1 Cycles Cycle N CLK tAA A[max:16] Valid Address tAADV ADV# tCO CE# tACLK A/DQ[15:0] (READ) Valid Output Valid Output Valid Output Valid Output Valid Output tSP tHD A/DQ[15:0] (WRITE) Valid Address Valid Input Burst Identified ADV# = LOW Valid Input Valid Input Don't Care Valid Input Valid Input Undefined 8.4.3.16 Operating Mode (BCR[15]) Default = Asynchronous Operation The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 27 - W957D6HB 8.4.4 Refresh Configuration Register The refresh configuration register (RCR) defines how the ADMUX PSRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. At power-up, the RCR is set to 0010h. The RCR is accessed with CRE HIGH and A[19:18] = 00b; or through the register access software sequence with A/DQ = 0000h on the third cycle. 8.4.4.1 Refresh Configuration Register Mapping A[max:20] A[19:18] max-20 19-18 Reserved Register Select All must be set to "0" RCR[19] RCR[18] 0 0 A[17:16], ADQ[15: 7] 6 17-7 5 A/DQ4 A/DQ3 4 3 DPD Ignored Reserved All must be set to "0" Register Select A/DQ6 A/DQ5 A/DQ2 A/DQ1 2 1 A/DQ0 0 PAR Reserved Must be set to "0" Setting is ignored RCR[4] Deep Power-Down 0 DPD Enable 1 DPD Disable (default) Selsect RCR RCR[2] RCR[1] RCR[0] Refersh Coverage 0 0 0 Full array (default) 1 0 Selsect BCR 0 0 1 Bottom 1/2 array 0 1 Selsect DIDR 0 1 0 Bottom 1/4 array 0 1 1 Bottom 1/8 array 1 0 0 None of array 1 0 1 Top 1/2 array 1 1 0 Top 1/4 array 1 1 1 Top 1/8 array Note: Reserved bits must be set to zero. Reserved bits not set to zero will affect device functionality. RCR[15:0] will be read back as written. 8.4.4.2 Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 28 - W957D6HB 8.4.4.3 Address Patterns for PAR (RCR [4] = 1) RCR[2] RCR[1] RCR[0] Active Section Address Space Size Density 0 0 0 Full die 000000h-7FFFFFh 8 Meg x 16 128Mb 0 0 1 One-half of die 000000h-3FFFFFh 4 Meg x 16 64Mb 0 1 0 One-quarter of die 000000h-1FFFFFh 2 Meg x 16 32Mb 0 1 1 One-eighth of die 000000h-0FFFFFh 1 Meg x 16 16Mb 1 0 0 None of die 0 0 Meg x 16 0Mb 1 0 1 One-half of die 400000h-7FFFFFh 4 Meg x 16 64Mb 1 1 0 One-quarter of die 600000h-7FFFFFh 2 Meg x 16 32Mb 1 1 1 One-eighth of die 700000h-7FFFFFh 1 Meg x 16 16Mb 8.4.4.4 Deep Power-Down (RCR[4]) Default = DPD Disabled The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage provided by the ADMUX PSRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the ADMUX PSRAM device will require 150s to perform an initialization procedure before normal operations can resume. Deep power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. DPD can be enabled using CRE or the software sequence to access the RCR. Taking CE# LOW for at least 10s disables DPD and sets RCR[4] = 1; it is not necessary to write to the RCR to disable DPD. BCR and RCR values (other than RCR[4]) are preserved during DPD. 8.4.5 Device Identification Register The DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device configuration. This register is read-only. The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the register access software sequence with ADQ = 0002h on the third cycle. 8.4.5.1 Device Identification Register Mapping Bit Field DIDR[15] DIDR[14:11] DIDR[10:8] DIDR[7:5] DIDR[4:0] Field name Row length Device version Device density CellularRAM generation Vendor ID Options Length Bit Setting 256 words 1b Version Bit Setting 1st 0000b 2nd 0001b Density Bit Setting Generation Bit Setting Vendor Bit Setting 128Mb 011b CR1.5 010b Winbond 00110b Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 29 - W957D6HB 9. ELECTRICAL CHARACTERISTIC 9.1 Absolute Maximum DC, AC Ratings Parameter Min Max Unit Operating temperature (case) Wireless -40 +85 C Storage temperature (plastic) -55 +150 C Soldering temperature and time 10s (solder ball only) +260 C Voltage to any ball except VCC, VCCQ relative to VSS -0.3 VCCQ +0.3 V Voltage on VCC supply relative to VSS -0.20 +2.45 V Voltage on VCCQ supply relative to VSS -0.20 +2.45 V Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 9.2 Electrical Characteristics and Operating Conditions Description Conditions Symbol Min Max Unit VCC 1.7 1.95 V I/O supply voltage VCCQ 1.7 1.95 V Input high voltage VIH VCCQ-0.4 VCCQ+0.2 V 1 Input low voltage VIL -0.20 0.4 V 2 0.8xVCCQ V 3 3 Supply voltage Typical Note Output high voltage IOH=-0.2mA VOH Output low voltage IOL=+0.2mA VOL 0.2xVCCQ V Input leakage current VIN=0 to VCCQ ILI 1 A Output leakage current OE#=VIH or chip disabled ILO 1 A mA 4 mA 4 mA 4 mA 4 A 5, 6 Operating Current Asynchronous random READ/WRITE ICC1 Initial access, burst READ/WRITE ICC2 Continuous burst READ VIN = VCCQ or 0V, Chip enabled, IOUT=0 Continuous burst WRITE Standby Current ICC3R ICC3W VIN = VCCQ or 0V, CE# = VCCQ ISB RC/WC=70ns - 35 133MHz - 45 104MHz - 40 133MHz - 40 104MHz - 35 133MHz - 40 104MHz - 40 Standard - 300 Notes: 1. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions. 2. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions. 3. BCR[5:4] = 01b (default setting of one-half drive strength). 4. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 5. ISB (max) values measured with PAR set to FULL ARRAY and at +85C. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS. ISB might be slightly higher for up to 500ms after power-up, or when entering standby mode. . Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 30 - W957D6HB 9.3 Deep Power-Down Specifications Description Conditions Symbol Typical Unit Deep Power-Down VIN = VCCQ or 0V; VCC, VCCQ = 1.95V; +85C IZZ 10 A Note: Typical (TYP) IZZ value applies across all operating temperatures and voltages. 9.4 Partial Array Self Refresh Standby Current Description Conditions Partial-array refresh Standby current Array Partition Full 1/2 1/4 1/8 Symbol VIN = VCCQ or 0V, CE# = VCCQ Standard power (no designation) IPAR Max Unit 300 280 270 265 A 9.5 Capacitance Description Input Capacitance Input/Output Capacitance (A/DQ) Conditions Symbol Min Max Unit Note TC = +25C; f = 1 MHz; VIN = 0V CIN 2.0 6 pF 1 CIO 3.0 6.5 pF 1 Note 1: These parameters are verified in device characterization and are not 100% tested. 9.6 AC Input-Output Reference Wave form VCCQ Intput 1 VCCQ/2 2 VCCQ/23 Output Test Points VSSQ Notes: 1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) <1.6ns. 2. Input timing begins at VCCQ/2. 3. Output timing ends at VCCQ/2. 9.7 AC Output Load Circuit Test Point 50 Ohm VCCQ/2 DUT 30pF Note: All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b). Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 31 - W957D6HB 10. TIMING REQUIRMENTS 10.1 Read, Write Timing Requirements 10.1.1 Asynchronous READ Cycle Timing Requirements All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b). Parameter Symbol Address access time ADV# access time Min Max Unit tAA 70 ns tAADV 70 ns Address hold from ADV# HIGH tAVH 2 ns Address setup to ADV# HIGH tAVS 5 ns LB#/UB# access time tBA 70 ns LB#/UB# disable to DQ High-Z Output tBHZ 7 ns Chip select access time tCO 70 ns CE# LOW to ADV# HIGH tCVS 7 Note 1 ns Chip disable to DQ and WAIT High-Z output tHZ 7 ns Output enable to valid output tOE 20 ns 7.5 ns 7 ns 1 2 OE# LOW to WAIT valid tOEW Output disable to DQ High-Z output tOHZ Output enable to Low-Z output tOLZ 3 ns tVP 5 ns ADV# pulse width 1 1 Notes: 1. Low-Z to High-Z timings are tested with AC Output Load Circuit. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 2. High-Z to Low-Z timings are tested with the circuit. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 32 - W957D6HB 10.1.2 Burst READ Cycle Timing Requirements All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b). 133MHz Parameter 104MHz Symbol Unit Min Address access time (fixed latency) Max Min tAA 70 70 ns tAADV 70 70 ns tABA 34.75 34.75 ns CLK to output delay tACLK 5.5 7 ns Address hold from ADV# HIGH (fixed latency) tAVH Burst OE# LOW to output delay tBOE ADV# access time (fixed latency) Burst to READ access time (variable latency) 2 2 20 5 ns 20 5 ns CE# HIGH between subsequent burst or mixed-mode operations tCBPH Maximum CE# pulse width tCEM CLK period tCLK Chip select access time (fixed latency) tCO CE# setup time to active CLK edge tCSP 2.5 3 ns Hold time from active CLK edge tHD 1.5 2 ns Chip disable to DQ and WAIT High-Z output tHZ 7 7 ns CLK rise or fall time tKHKL 1.2 1.6 ns CLK to WAIT valid tKHTL 5.5 7 ns Output HOLD from CLK tKOH 2 2 ns CLK HIGH or LOW time tKP 3 3 ns 4 7.5 4 9.62 70 Output disable to DQ High-Z output tOHZ Output enable to Low-Z output tOLZ 3 Setup time to active CLK edge tSP 2 ns 1 s 1 ns 70 7 Note Max 7 ns 2 ns 2 3 ns 3 3 ns Notes: 1. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. 2. Low-Z to High-Z timings are tested with the circuit. The High-Z timings measure a 100mV transition from either V OH or VOL toward VCCQ/2. 3. High-Z to Low-Z timings are tested with the circuit. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 33 - W957D6HB 10.1.3 Asynchronous WRITE Cycle Timing Requirements Parameter Symbol Min tAS 0 ns Address HOLD from ADV# going HIGH tAVH 2 ns Address setup to ADV# going HIGH tAVS 5 ns Address valid to end of WRITE tAW 70 ns LB#/UB# select to end of WRITE tBW 70 ns CE# HIGH between subsequent asynchronous operations tCPH 5 ns CE# LOW to ADV# HIGH tCVS 7 ns Chip enable to end of WRITE tCW 70 ns Data HOLD from WRITE time tDH 0 ns Data WRITE setup time tDW 20 ns Chip disable to WAIT High-Z output tHZ ADV# pulse width tVP 5 ns ADV# setup to end of WRITE tVS 70 ns WRITE pulse width tWP 45 ns WRITE recovery time tWR 0 ns Address and ADV# LOW setup time Max 7 Unit ns Note 1 2 Notes: 1. Low-Z to High-Z timings are tested with AC Output Load Circuit. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 2. WE# LOW time must be limited to tCEM (4s). Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 34 - W957D6HB 10.1.4 Burst WRITE Cycle Timing Requirements 133MHz Parameter 104MHz Symbol Min Address and ADV# LOW setup time Max Min Unit Note 1 Max tAS 0 0 ns tAVH 2 2 ns CE# HIGH between subsequent burst or mixed-mode operations tCBPH 5 5 ns 2 Maximum CE# pulse width tCEM s 2 Clock period tCLK 7.5 9.62 ns CE# setup to CLK active edge tCSP 2.5 3 ns Hold time from active CLK edge tHD 1.5 2 ns Chip disable to WAIT High-Z output tHZ 7 7 ns CLK rise or fall time tKHKL 1.2 1.6 ns Clock to WAIT valid tKHTL 5.5 7 ns Output HOLD from CLK tKOH 2 2 ns CLK HIGH or LOW time tKP 3 3 ns Setup time to activate CLK edge tSP 2 3 ns Address HOLD from ADV# HIGH (fixed latency) 4 4 3 Notes: 1. tAS required if tCSP > 20ns. 2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. 3. Low-Z to High-Z timings are tested with the circuit. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 35 - W957D6HB 10.2 TIMING DIAGRAMS 10.2.1 Initialization Period tPU VCC (MIN) VCC, VCCQ=1.7V Device ready for normal operation 10.2.2 DPD Entry and Exit Timing Parameters tDPD tDPDX tPU DPD Enabled DPD Exit Device Initialization CE# Write RCR [4] = 0 Device ready for normal operation 10.2.3 Initialization and DPD Timing Parameters Description CE# HIGH after Write RCR[4]=0 CE# LOW between DPD Enable and Device Initialization DPD Exit to next Operation Command Symbol Min Max Unit tDPD 150 - s tDPDX 10 - s tPU - 150 s Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 36 - W957D6HB 10.2.4 Asynchronous READ VIH A[max:16] Valid Address VIL tAA tAVS tAVH VIH ADV# VIL tAADV tVP VIH tHZ tCVS CE# VIL tCO tBA LB#/UB# tBHZ VIH VIL tOE tOHZ VIH OE# VIL VIH WE# tOLZ VIL tAVS tAVH VIH A/DQ[15:0] VOH Valid Output Valid Address High-z VOL VIL tAA tHZ tOEW VOH WAIT High-z High-z VOL Don't Care Undefined Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 37 - W957D6HB 10.2.5 Single Access Burst READ Operation - Variable Latency tCLK CLK VIL tSP A[max:16] VIH VIL tHD tKHKL tHD VIH VIL tHD tCEM tCSP CE# tKP Valid Address tSP ADV# tKP VIH tABA tHZ VIH VIL tBOE OE# tOHZ VIH VIL tOLZ tSP WE# VIH VIL VIH LB#/UB# tSP tHD VIL tSP A/DQ[15:0] tHD tHD VIL tACLK VOH VIH Valid Address HIGH-Z tKOH Valid Output VOL tKOH WAIT VOH VOL HIGH-Z HIGH-Z tKHTL tKHTL Don't Care READ burst identified (WE# = HIGH) Undefined Note: Non-default BCR settings: latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 38 - W957D6HB 10.2.6 Four Word Burst READ Operation-Variable Latency tKHKL CLK VIH VIL tHD tHD VIH VIL tCEM tCSP CE# OE# tKP Valid Address tSP ADV# tKP VIH VIL tSP A[max:16] tCLK tHD tABA VIH VIL tCBPH tHZ tBOE VIH VIL tOHZ tSP WE# tHD tOLZ VIH VIL tSP tHD VIH LB#/UB# VIL tSP A/DQ[15:0] WAIT VIH VIL VOH tHD tACLK VOH Valid Address VOL Valid Output tKOH Valid Output Valid Output Valid Output tKOH Note 3 HIGH-Z Note 2 HIGH-Z HIGH-Z VOL tKHTL tKHTL READ burst identified (WE# = HIGH) Don't Care Undefined Notes: 1. Non-default BCR settings: latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. 2. WAIT will remain de-asserted even if CE# remains LOW past the end of the defined burst length. 3. A/DQ[15:0] will output undefined data if CE# remains LOW past the end of the defined burst lengt h. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 39 - W957D6HB 10.2.7 Single-Access Burst READ Operation-Fixed Latency tCLK CLK tKP tKP VIH VIL tKHKL tSP VIH Valid Address A[max:16] VIL tAVH tSP tAA tHD VIH ADV# VIL tHD tAADV tCEM tHZ tCSP CE# VIH VIL tCO tOHZ tBOE OE# VIH VIL tSP WE# tOLZ tHD VIH VIL tSP tHD VIH LB#/UB# VIL tAVH tSP A/DQ[15:0] VIH Valid Address VIL tKOH tACLK VOH Valid Output VOL HIGH-Z tKOH WAIT VOH VOL HIGH-Z HIGH-Z tKHTL tKHTL Don't Care READ burst identified (WE# = HIGH) Undefined Note: Non-default BCR settings: fixed latency, latency code 4 (5 clocks), WAIT active LOW, WAIT asserted during delay. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 40 - W957D6HB 10.2.8 Four Word Burst READ Operation-Fixed Latency tCLK tKHKL CLK VIH VIL A[max:16] VIH VIL tKP tKP tSP Valid Address tAVH tAA tSP ADV# tHD VIH VIL tAADV tCEM tHD tCSP CE# VIH VIL tCBPH tHZ tCO tBOE OE# VIH VIL tSP WE# VIH VIL LB#/UB# VIH VIL tHD tOHZ tOLZ tHD tSP tSP A/DQ[15:0] VIH VIL tAVH Valid Address tACLK VOH VOL Valid Output tKOH Valid Output Valid Output Valid Output Note 3 HIGH-Z Note 2 HIGH-Z tKOH WAIT VOH VOL HIGH-Z tKHTL tKHTL READ burst identified (WE# = HIGH) Don't Care Undefined Notes: 1. Non-default BCR settings: fixed latency, latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. 2. WAIT will remain de-asserted even if CE# remains LOW past the end of the defined burst length. 3. A/DQ[15:0] will output undefined data if CE# remains LOW past the end of the defined burst length . Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 41 - W957D6HB 10.2.9 Burst READ Terminate at End-of-Row (Wrap Off) CLK VIH VIL tCLK A[max:16] ADV# VIH VIL VIH VIL VIH LB#/UB# VIL tHD tCSP Note 2 CE# VIH VIL VIH OE# VIL WE# VIH VIL End of Row A/DQ[15:0] VIH VIL Valid Output Valid Output tHZ tKHTL VOH WAIT VOL tHZ HIGH-Z tKOH Don't Care Undefined Notes: 1. Non-default BCR settings for burst READ at end of row: fixed or variable latency, WAIT active LOW, WAIT asserted during delay (shown as solid line). 2. For burst READs, CE# must go HIGH before the second CLK after the WAIT period begins (before the second CLK after WAIT asserts with BCR[8] = 0, or before the third CLK after WAIT asserts with BCR[8] = 1). Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 42 - W957D6HB 10.2.10 Burst READ Row Boundary Crossing CLK VIH VIL tCLK A[max:16] VIH VIL ADV# VIH VIL VIH LB#/UB# CE# OE# WE# A/DQ[15:0] VIL VIH VIL VIH VIL VIH VIL VOH VOL Valid Output Valid Output Valid Output End of Row Valid Output tKHTL tKHTL VOH WAIT Note 2 VOL tKOH tKOH Undefined Don't Care Notes: 1. Non-default BCR settings for burst READ at end of row: fixed or variable latency, WAIT active LOW, WAIT asserted during delay (shown as solid line). 2. WAIT will be asserted LC+1 cycles for variable latency or fixed latency. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 43 - W957D6HB 10.2.11 Asynchronous WRITE VIH Valid Address A[max:16] VIL tAVS tAVH tAW tVS VIH tVP ADV# tAS VIL tAS tCVS VIH tCW CE# VIL tBW VIH LB#/UB# VIL VIH OE# VIL VIH tWP WE# VIL tAS tAVS VIH A/DQ[15:0] VIL tAVH tDW Valid Address tDH Valid Input tAW WAIT VOH HIGH-Z VOL Don't Care Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 44 - W957D6HB 10.2.12 Burst WRITE Operation--Variable Latency Mode tCLK CLK tKHKL tKP VIL tSP A[max:16] tKP VIH VIH tHD Valid Address VIL 3 tAS tSP VIH tHD ADV# VIL 3 tAS tSP tHD VIH LB#/UB# VIL tCEM tHD tCSP VIH CE# Note 4 VIL OE# WE# tCBPH VIH VIL tSP tHD VIH VIL 3 tAS tSP VIH A/DQ[15:0] VIL tHD tSP Valid Address D1 WAIT D2 D3 tKHTL tKHTL VOH tHD D4 tHZ HIGH-Z HIGH-Z Note 2 tKOH VOL WRITE burst identified (WE# = LOW) Don't Care Undefined Notes: 1. Non-default BCR settings for burst WRITE operation in variable latency mode: latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay, burst length 4, burst wrap enabled. 2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]). 3. tAS is required if tCSP > 20ns. 4. CE# must go HIGH before any clock edge following the last word of a defined-length burst. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 45 - W957D6HB 10.2.13 Burst WRITE Operation-Fixed Latency Mode tKP tCLK CLK tKHKL tKP VIH VIL tSP VIH Valid Address A[max:16] VIL 3 tAS tAVH tSP VIH tHD ADV# VIL 3 tAS tSP tHD VIH LB#/UB# VIL tCEM tHD tCSP VIH CE# Note 4 VIL OE# tCBPH VIH VIL tSP tHD VIH WE# VIL tAVH 3 tAS tSP A/DQ[15:0] VIH VIL Valid Address tSP VOH WAIT tHD D1 D2 D3 D0 tKHTL tHZ tKHTL HIGH-Z HIGH-Z Note 2 tKOH VOL Don't Care WRITE burst identified (WE# = LOW) Undefined Notes: 1. Non-default BCR settings for burst WRITE operation in fixed latency mode: fixed latency, latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay, burst length 4, burst wrap enabled. 2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]). 3. tAS is required if tCSP > 20ns. 4. CE# must go HIGH before any clock edge following the last word of a defined-length burst. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 46 - W957D6HB 10.2.14 Burst WRITE Terminate at End of Row (Wrap Off) CLK A[max:16] VIH VIL VIL ADV# VIH VIL LB#/UB# VIH VIL WE# OE# CE# tCLK VIH VIH VIL VIH VIL VIH Note 2 VIL tSP A/DQ[15:0] tCSP tHD VIH VIL tHD Valid Input Valid Input Valid Input END OF ROW tHZ tHZ VOH WAIT VOL HIGH-Z tKOH tKHTL Don't Care Undefined Notes: 1. Non-default BCR settings for burst WRITE at end of row: fixed or variable latency, WAIT active LOW, WAIT asserted during delay (shown as solid line). 2. For burst WRITEs, CE# must go HIGH before the second CLK after the WAIT period begins (before the second CLK after WAIT asserts with BCR[8] = 0, or before the third CLK after WAIT asserts with BCR[8] = 1). Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 47 - W957D6HB 10.2.15 Burst WRITE Row Boundary Crossing CLK VIH VIL tCLK A[max:16] ADV# VIH VIL VIH VIL VIH LB#/UB# WE# VIL VIH VIL VIH OE# VIL CE# VIH VIL tSP A/DQ[15:0] VIH VIL End of row tHD Valid Input Valid Input Valid Input Valid Input tKHTL Valid Input tKHTL VOH WAIT VOL tKOH tKOH Note 2 Don't Care Undefined Notes: 1. Non-default BCR settings for burst WRITE at end of row: fixed or variable latency, WAIT active LOW, WAIT asserted during delay (shown as solid line). 2. WAIT will be asserted LC cycles for variable latency or fixed latency. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 48 - W957D6HB 10.2.16 Burst WRITE Followed by Burst READ tCLK CLK A[max:16] VIH VIL tSP tHD tSP tHD Valid Address Valid Valid Address Address VIH VIL tHD ADV# VIH VIL tSP tSP tHD tHD tSP VIH LB#/UB# VIL tCSP CE# tHD tCBPH VIH Note 2 VIL tCSP tOHZ VIH OE# tHD VIL WE# VIH tSP tHD tSP VIL tSP A/DQ[15:0] IN/OUT VIH tSP tHD tSP tHD Valid D0 D1 D2 D3 output VIL tHD VOH WAIT Valid Address tKOH tBOE VOH VOL Valid Output Valid Output Valid Output Valid Output tACLK HIGH-Z HIGH-Z VOL Don't Care Undefined Notes: 1. Non-default BCR settings for burst WRITE followed by burst READ: fixed or variable latency, latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. 2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 49 - W957D6HB 10.2.17 Asynchronous WRITE Followed by Burst READ tCLK CLK VIH VIL tSP A[max:16] VIH VIL ADV# VIH VIL LB#/UB# VIH VIL tAVS tAS tVP tAVH tSP tHD tAS tSP tBW tCBPH CE# VIH VIL tHD Valid Address Valid Address tHD tCSP tCW Note 2 OE# VIH VIL tWC tSP tHD tWP WE# VIH VIL tAS A/DQ[15:0] tOHZ VIH VIL Valid Address tAVS VOH WAIT VOL tBOE tSP tHD Data tAVH tDW Valid Address tDH tKHTL VOH Valid Output VOL tACLK Valid Output Valid Output Valid Output tKOH HIGH-Z Don't Care Undefined Notes: 1. Non-default BCR settings for asynchronous WRITE, with ADV# LOW, followed by burst READ: fixed or variable latency, latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. 2. When the device is transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when the device is transitioning to fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 50 - W957D6HB 10.2.18 Burst READ Followed by Asynchronous WRITE tCLK CLK VIH VIL A[max:16] VIH VIL tSP tHD Valid Address Valid Address tAVS tAVH tAW tAS tSP ADV# tHD tVS VIH tVP VIL tHD tCSP CE# tAS tCW VIH VIL Note 2 tOHZ tBOE OE# tCBPH tHZ VIH VIL tSP WE# VIH VIL LB#/UB# VIH VIL tOLZ tHD tWP tHD tSP tSP A/DQ[15:0] VIH VIL tHD VOH Valid Address Valid Output VOL tBW tAS tKOH tACLK tWPH tAVS VIH VIL tAVH Valid Address tDW tDH Valid Input tKOH VOH WAIT VOL HIGH-Z HIGH-Z tKHTL tKHTL READ burst identified (WE# = HIGH) Don't Care Undefined Notes: 1. Non-default BCR settings for burst READ followed by asynchronous WRITE using ADV#: fixed or variable latency, latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. 2. When the device is transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when the device is transitioning from fixed-latency burst READs; asynchronous operation begins at the falling edge of ADV#. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 51 - W957D6HB 10.2.19 Asynchronous WRITE Followed by Asynchronous READ A[max:16] VIH Valid Address Valid Address VIL tAVS tAS tAVH tVS ADV# VIL tAA tAADV tAW tWR tVP VIH tAVH tAVS tVP tAS tBHZ tCVS LB#/UB# CE# VIH tBW tBA VIL tCVS VIH tCPH tHZ tCO tCW Note 1 VIL tOLZ OE# tOHZ tOE VIH VIL tWP WE# VIH VIL tAS VIH A/DQ[15:0] VIL Valid Address tAVS Valid Input tAVH tDW Valid Address tDH tAVS VOH Valid Output VOL tAVH tAA tAW tOEW WAIT VOH tHZ HIGH-Z VOL Don't Care Undefined Note: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh interval. Otherwise, tCPH is only required after CE#-controlled WRITEs. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 52 - W957D6HB 11. PACKAGE DESCRIPTION 11.1 Package Dimension VFBGA 54Ball (6x8 mm2, Ball pitch: 0.75mm, O =0.4mm) 6 5 3 4 E1 2 1 A PIN A1 INDEX eE A1 // bbb PIN A1 INDEX E A eD B C D1 D D E F G H J b aaa ddd ccc SEATING PLANE M M BALL LAND SYMBOL A A1 D D1 E E1 b aaa bbb ccc ddd eee e DIMENSION (mm) MIN. NOM. MAX. ----1.00 0.29 0.34 0.24 8.00 7.90 8.10 6.00 BSC. 6.00 5.90 6.10 3.75 BSC. 0.40 0.35 0.45 0.15 0.20 ----0.10 0.15 0.08 0.75 1 BALL OPENING Note: 1. Ball land: 0.45mm, Ball opening: 0.35mm, PCB Ball land suggested 0.35mm Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 53 - W957D6HB 12. REVISION HISTORY Version Date Page Description A01-001 Feb. 22, 2013 All A01-002 Mar. 26, 2013 2 1~38 Update ordering information Add DPD mode A01-003 May 09, 2013 All, 2 Update part # A01-004 Jun. 27, 2013 32 A01-005 All 8 34 52 Aug. 17, 2016 3, 19, 20, 25, 29, 36 31 43 48 Create new document Remove note 6 in section 9.2 Refine format Refine 8.1.1 power-up initialization timing diagram Removing redundant tWHZ parameter Correcting typo in 10.2.19 timing diagram (change tDS to tDW ) Correcting typos Defined 9.4 Partial Array Self Refresh standby current values Revise note2 of 10.2.10 Burst READ Row Boundary Crossing Revise note2 of 10.2.15 Burst WRITE Row Boundary Crossing Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation where in personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 54 -