LM3424
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SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
LM3424 Constant Current N-Channel Controller with Thermal Foldback for Driving LEDs
Check for Samples: LM3424
1FEATURES DESCRIPTION
The LM3424 is a versatile high voltage N-channel
2• LM3424Q is an Automotive Grade Product that MosFET controller for LED drivers . It can be easily
is AEC-Q100 Grade 1 Qualified (-40°C to configured in buck, boost, buck-boost and SEPIC
+125°C Operating Junction Temperature) topologies. In addition, the LM3424 includes a
• VIN Range from 4.5V to 75V thermal foldback feature for temperature
management of the LEDs. This flexibility, along with
• High-side Adjustable Current Sense an input voltage rating of 75V, makes the LM3424
• 2Ω, 1A Peak MosFET Gate Driver ideal for illuminating LEDs in a large family of
• Input Under-voltage and Output Over-voltage applications.
Protection Adjustable high-side current sense voltage allows for
• PWM and Analog Dimming tight regulation of the LED current with the highest
• Cycle-by-cycle Current Limit efficiency possible. The LM3424 uses standard peak
current-mode control providing inherent input voltage
• Programmable Slope Compensation feed-forward compensation for better noise immunity.
• Programmable, Synchronizable Switching It is designed to provide accurate thermal foldback
Frequency with a programmable foldback breakpoint and slope.
• Programmable Thermal Foldback In addition, a 2.45V reference is provided.
• Programmable Softstart The LM3424 includes a high-voltage startup regulator
• Precision Voltage Reference that operates over a wide input range of 4.5V to 75V.
The internal PWM controller is designed for
• Low Power Shutdown and Thermal Shutdown adjustable switching frequencies of up to 2.0 MHz
and external synchronization is possible. The
APPLICATIONS controller is capable of high speed PWM dimming
• LED Drivers - Buck, Boost, Buck-Boost, and and analog dimming. Additional features include
SEPIC slope compensation, softstart, over-voltage and
under-voltage lock-out, cycle-by-cycle current limit,
• Indoor and Outdoor Area SSL and thermal shutdown.
• Automotive The LM3424Q is an Automotive Grade product that is
• General Illumination AEC-Q100 grade 1 qualified.
• Constant-Current Regulators
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
VIN (V)
EFFICIENCY (%)
100
95
90
85
8010 15 20 25 30
SS
TGAIN
OVP
LM3424
nDIM
VIN
GND
TSENSE
TREF
DDRV
VS
DAP
GATE
EN
COMP
VIN
CSH
RT/SYNC
IS
HSN
SLOPE
VCC
HSP
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
ILED
PWM
TEMP
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
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Typical Boost Application Circuit
Figure 1. Boost Evaluation Board
9 Series LEDs at 1A
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VIN
nDIM
TGAIN
TSENSE
CSH
RT GATE
1
COMP HSN
DAP
SLOPE
2
3
4
5
6
7
20
19
18
17
16
15
14 DDRV
GND
HSP
VCC
21
8
9
10
13
12
11 OVP
VS
IS
TREF
SS
EN
LM3424
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SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
Connection Diagram
Figure 2. 20-Lead HTSSOP EP
PIN DESCRIPTIONS
Pin Name Description Application Information
Bypass with 100 nF capacitor to GND
1 VIN Input Voltage as close to the device as possible.
Connect to > 2.4V to enable the
2 EN Enable device or to < 0.8V for low power
shutdown.
Connect a capacitor to GND to
3 COMP Compensation compensate control loop.
Connect a resistor to GND to set the
signal current. Can also be used to
4 CSH Current Sense High analog dim as explained in the
THERMAL FOLDBACK / ANALOG
DIMMING section.
Connect a resistor to GND to set the
switching frequency. Can also be
5 RT Resistor Timing used to synchronize external clock as
explained in the SWITCHING
FREQUENCY section.
Connect a PWM signal for dimming
as detailed in the PWM DIMMING
Dimming Input /
6 nDIM section and/or a resistor divider from
Under-Voltage Protection VIN to program input under-voltage
lockout.
Connect a capacitor to GND to
7 SS Soft-start extend start-up time.
Connect a resistor to GND to set the
8 TGAIN Temp Foldback Gain foldback slope.
Connect a resistor/ thermistor divider
from VSto sense the temperature as
9 TSENSE Temp Sense Input explained in the THERMAL
FOLDBACK / ANALOG DIMMING
section.
Connect a resistor divider from VSto
10 TREF Temp Foldback Reference set the foldback reference voltage.
2.45V reference for temperature
11 VSVoltage Reference foldback circuit and other external
circuitry.
Connect a resistor divider from VOto
12 OVP Over-Voltage Protection program output over-voltage lockout.
13 DDRV Dimming Gate Drive Output Connect to gate of dimming MosFET.
Connect to DAP to provide proper
14 GND Ground system GND
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PIN DESCRIPTIONS (continued)
Pin Name Description Application Information
Connect to gate of main switching
15 GATE Main Gate Drive Output MosFET.
Bypass with a 2.2 µF – 3.3 µF,
16 VCC Internal Regulator Output ceramic capacitor to GND.
Connect to the drain of the main N-
channel MosFET switch for RDS-ON
17 IS Main Switch Current Sense sensing or to a sense resistor
installed in the source of the same
device.
Connect a resistor to GND to set
18 SLOPE Slope Compensation slope of additional ramp.
Connect through a series resistor to
19 HSN LED Current Sense Negative LED current sense resistor
(negative).
Connect through a series resistor to
20 HSP LED Current Sense Positive LED current sense resistor (positive).
Connect to GND. Refer to (1) for
DAP DAP Thermal pad on bottom of IC thermal considerations.
(1) Junction-to-ambient thermal resistance is highly board-layout dependent. The numbers listed in the table are given for a reference layout
wherein the 20L HTSSOP EP package has its DAP pad populated with 9 vias. In applications where high maximum power dissipation
exists, namely driving a large MosFET at high switching frequency from a high input voltage, special care must be paid to thermal
dissipation issues during board design. In high-power dissipation applications, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the
maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the package in
the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). In most applications there is little need for
the full power dissipation capability of this advanced package. Under these circumstances, no vias would be required and the thermal
resistances would be 104 °C/W for the 20L HTSSOP EP. It is possible to conservatively interpolate between the full via count thermal
resistance and the no via count thermal resistance with a straight line to get a thermal resistance for any number of vias in between
these two limits.
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SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
VIN, EN, nDIM -0.3V to 76.0V
-1 mA continuous
OVP, HSP, HSN -0.3V to 76.0V
-100 µA continuous
IS -0.3V to 76.0V
-2V for 100 ns
-1 mA continuous
VCC -0.3V to 8.0V
VS, TREF, TSENSE, TGAIN, COMP, CSH, RT, SLOPE, SS -0.3V to 6.0V
SS -30 µA to +30 µA continuous
GATE, DDRV -0.3V to VCC
-2.5V for 100 ns
VCC+2.5V for 100 ns
-1 mA to +1 mA continuous
GND -0.3V to 0.3V
-2.5V to 2.5V for 100 ns
Maximum Junction Temperature Internally Limited
Storage Temperature Range −65°C to +150°C
Maximum Lead Temperature (Reflow and Solder) (3) 260°C
Continuous Power Dissipation Internally Limited
ESD Susceptibility (4) Human Body Model 2 kV
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Operating Ratings is not implied. The recommended Operating Ratings indicate
conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are with respect
to the potential at the GND pin, unless otherwise specified.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Refer to TI’s packaging website for more detailed information and mounting techniques, http://www.ti.com/packaging.
(4) Human Body Model, applicable std. JESD22-A114-C.
OPERATING CONDITIONS(1)
Operating Junction Temperature Range −40°C to +125°C
Input Voltage VIN 4.5V to 75V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Operating Ratings is not implied. The recommended Operating Ratings indicate
conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are with respect
to the potential at the GND pin, unless otherwise specified.
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SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
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ELECTRICAL CHARACTERISTICS(1)
Specifications in standard type face are for TJ= 25°C and those with boldface type apply over the full Operating
Temperature Range ( TJ=−40°C to +125°C). Minimum and Maximum limits are specified through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ= +25°C, and are provided for reference purposes
only. Unless otherwise stated the following condition applies: VIN = +14V. Min Typ Max
Symbol Parameter Conditions Units
(2) (3) (2)
STARTUP REGULATOR (VCC)
VCC-REG VCC Regulation ICC = 0 mA 6.30 6.90 7.35 V
ICC-LIM VCC Current Limit VCC = 0V 20 25 mA
IQQuiescent Current EN = 3.0V, Static 2.0 3.0
ISD Shutdown Current EN = 0V 0.1 1.0 µA
VCC-UVLO VCC UVLO Threshold VCC Increasing 4.17 4.50
VCC Decreasing 3.70 4.08 V
VCC-HYS VCC UVLO Hysteresis 0.1
ENABLE (EN)
VEN-ST EN Startup Threshold EN Increasing 1.75 2.40
EN decreasing 0.80 1.63 V
VEN-HYS EN Startup Hysteresis 0.1
REN EN Pull-down Resistance 0.45 0.82 1.30 MΩ
OVER-VOLTAGE PROTECTION (OVP)
VTH-OVP OVP OVLO Threshold OVP Increasing 1.185 1.240 1.285 V
IHYS-OVP OVP Hysteresis Source OVP Active (high) 13 20 27 µA
Current
ERROR AMPLIFIER
VCSH CSH Reference Voltage With Respect to GND 1.210 1.235 1.260 V
Error Amplifier Input Bias -0.6 0 0.6
Current µA
COMP Sink / Source 17 26 35
Current
Transconductance 100 µA/V
Linear Input Range (4) ±125 mV
Transconductance -6dB Unloaded Response (4) 1.0 MHz
Bandwidth
OSCILLATOR (RT)
fSW Switching Frequency RT= 36 kΩ164 207 250 kHz
RT= 12 kΩ525 597 669
VRT-SYNC Sync Threshold 3.5 V
PWM COMPARATOR
VCP-BASE COMP to PWM Offset - 750 900 1050 mV
No Slope Compensation
SLOPE COMPENSATION (SLOPE)
ΔVCP Slope Compensation Additional COMP to PWM Offset - SLOPE 85 mV
Amplitude sinking 100 µA
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Operating Ratings is not implied. The recommended Operating Ratings indicate
conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are with respect
to the potential at the GND pin, unless otherwise specified.
(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(3) Typical numbers are at 25°C and represent the most likely norm.
(4) These electrical parameters are specified by design, and are not verified by test.
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ELECTRICAL CHARACTERISTICS(1) (continued)
Specifications in standard type face are for TJ= 25°C and those with boldface type apply over the full Operating
Temperature Range ( TJ=−40°C to +125°C). Minimum and Maximum limits are specified through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ= +25°C, and are provided for reference purposes
only. Unless otherwise stated the following condition applies: VIN = +14V. Min Typ Max
Symbol Parameter Conditions Units
(2) (3) (2)
CURRENT LIMIT (IS)
VLIM Current Limit Threshold 215 245 275 mV
VLIM Delay to Output 35 75 ns
tON-MIN Leading Edge Blanking 140 240 340
Time
HIGH SIDE TRANSCONDUCTANCE AMPLIFIER
Input Bias Current 10 µA
Transconductance 20 mA/V
Input Offset Current -1.5 01.5 µA
Input Offset Voltage -5 05mV
Transconductance ICSH = 100 µA (5) 500 kHz
Bandwidth
GATE DRIVER (GATE)
RSRC-GATE GATE Sourcing GATE = High 2.0 6.0
Resistance Ω
RSNK-GATE GATE Sinking Resistance GATE = Low 1.3 4.5
UNDER-VOLTAGE LOCKOUT and DIM INPUT (nDIM)
VTH-nDIM nDIM / UVLO Threshold 1.185 1.240 1.285 V
IHYS-nDIM nDIM Hysteresis Current 13 20 27 µA
DIM DRIVER (DDRV)
RSRC-DDRV DDRV Sourcing DDRV = High 13.5 30.0
Resistance Ω
RSNK-DDRV DDRV Sinking Resistance DDRV = Low 3.5 10.0
nDIM rising to DDRV 700
rising ns
nDIM rising to DDRV 360
falling
SOFT-START (SS)
ISS Soft-start current 10 µA
THERMAL CONTROL
VSVSVoltage IVS = 0A 2.40 2.45 2.50 V
IVS = 1 mA
TREF input bias current VTREF = 1.5V 0.1
VTSENSE = 1.5V
TSENSE Input Bias VTREF = 1.5V 0.1
Current VTSENSE = 1.5V
ITGAIN-MAX TGAIN Maximum VTGAIN = 2V 200 600
Sourcing Current µA
ITF CSH Current with High- RTGAIN = VTREF = 1.5V 100
side Amplifier Disabled 10 kΩVTSENSE = 0.5V
VTREF = 1.5V 10
VTSENSE = 1.4V
VTREF = 1.5V 2
VTSENSE = 1.5V
(5) These electrical parameters are specified by design, and are not verified by test.
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ELECTRICAL CHARACTERISTICS(1) (continued)
Specifications in standard type face are for TJ= 25°C and those with boldface type apply over the full Operating
Temperature Range ( TJ=−40°C to +125°C). Minimum and Maximum limits are specified through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ= +25°C, and are provided for reference purposes
only. Unless otherwise stated the following condition applies: VIN = +14V. Min Typ Max
Symbol Parameter Conditions Units
(2) (3) (2)
THERMAL SHUTDOWN
TSD Thermal Shutdown (6) 165
Threshold °C
THYS Thermal Shutdown (6) 25
Hysteresis
THERMAL RESISTANCE
θJA Junction to Ambient 20L HTSSOP EP (7) 34 °C/W
(6) These electrical parameters are specified by design, and are not verified by test.
(7) Junction-to-ambient thermal resistance is highly board-layout dependent. The numbers listed in the table are given for a reference layout
wherein the 20L HTSSOP EP package has its DAP pad populated with 9 vias. In applications where high maximum power dissipation
exists, namely driving a large MosFET at high switching frequency from a high input voltage, special care must be paid to thermal
dissipation issues during board design. In high-power dissipation applications, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the
maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the package in
the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). In most applications there is little need for
the full power dissipation capability of this advanced package. Under these circumstances, no vias would be required and the thermal
resistances would be 104 °C/W for the 20L HTSSOP EP. It is possible to conservatively interpolate between the full via count thermal
resistance and the no via count thermal resistance with a straight line to get a thermal resistance for any number of vias in between
these two limits.
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DUTY CYCLE (%)
ILED (A)
25 kHz
1 kHz
100806040200
0.8
0.2
0.4
0.6
0.8
1.0
ICSH (éA)
ILED (A)
1.0
0.8
0.6
0.4
0.2
0.00 20 40 60 80 100
VIN (V)
ILED (A)
1.02
1.01
1.00
0.99
0.980 16 32 48 64 80
VIN (V)
ILED (A)
1.010
1.005
1.000
0.995
0.9905 10 15 20 25 30
VIN (V)
EFFICIENCY (%)
100
95
90
85
8010 15 20 25 30
VIN (V)
EFFICIENCY (%)
100
95
90
85
80
75
700 16 32 48 64 80
LM3424
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SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
TYPICAL PERFORMANCE CHARACTERISTICS
TA=+25°C and VIN = 14V unless otherwise specified
Boost Efficiency vs. Input Voltage Buck-Boost Efficiency vs. Input Voltage
VO= 32V (9 LEDs) (1) VO= 21V (6 LEDs) (2)
Figure 3. Figure 4.
Boost LED Current vs. Input Voltage Buck-Boost LED Current vs. Input Voltage
VO= 32V (9 LEDs) (1) VO= 21V (6 LEDs) (2)
Figure 5. Figure 6.
Analog Dimming PWM Dimming
VO= 21V (6 LEDs); VIN = 24V (2) VO= 32V (9 LEDs); VIN = 24V (1)
Figure 7. Figure 8.
(1) The measurements were made using the standard boost evaluation board from AN-1969 (literature number SNVA398).
(2) The measurements were made using the standard buck-boost evaluation board from AN-1967 (literature number SNVA397).
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TEMPERATURE (°C)
tON-MIN (ns)
255
250
245
240
235
230
225
-50 -14 22 58 94 130
TEMPERATURE (°C)
fSW (kHz)
1000
100
-50 -14 22 58 94 130
RT = 12 kÖ
RT = 36 kÖ
TEMPERATURE (°C)
VLIM (mV)
248
246
244
242
240
-50 -14 22 58 94 130
TEMPERATURE (°C)
VS (V)
2.500
2.450
2.400
-50 -14 22 58 94 130
TEMPERATURE (°C)
VCSH (V)
1.250
1.245
1.240
1.235
1.230
1.225
1.220
-50 -14 22 58 94 130
TEMPERATURE (°C)
VCC (V)
7.20
7.10
7.00
6.90
6.80
6.70
-50 -14 22 58 94 130
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA=+25°C and VIN = 14V unless otherwise specified
VCSH vs. Junction Temperature VCC vs. Junction Temperature
Figure 9. Figure 10.
VSvs. Junction Temperature VLIM vs. Junction Temperature
Figure 11. Figure 12.
tON-MIN vs. Junction Temperature fSW vs. Junction Temperature
Figure 13. Figure 14.
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TEMPERATURE (°C)
ILED (A)
1.25
1.00
0.75
0.50
0.25
0.000 25 50 75 100 125
RGAIN = 15 k:
RGAIN = 5 k:
RGAIN = 10 k:
TEMPERATURE (°C)
ILED (A)
1.25
1.00
0.75
0.50
0.25
0.000 25 50 75 100 125
RBIAS = 43.2 k:
RBIAS = 84.5 k:
RBIAS = 24.3 k:
fSW (Hz)
RT (Ö)
1M
100k
10k
1k
10k 100k 1M 10M
TEMPERATURE (°C)
ITF (éA)
100.3
100.1
99.9
99.7
99.5
-50 -14 22 58 94 130
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA=+25°C and VIN = 14V unless otherwise specified
ITF vs. Junction Temperature
RGAIN = 10 kΩ; VTSENSE = 0.5V; VTREF = 1.5V fSW vs. RT
Figure 15. Figure 16.
Ideal Thermal Foldback - Varied Slope Ideal Thermal Foldback - Varied Breakpoint
RREF1 = RREF2 = 49.9 kΩ; RNTC-BK = RBIAS = 43.2 kΩRREF1 = RREF2 = 49.9 kΩ; RGAIN = 10 kΩ
Figure 17. Figure 18.
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IS
PWM
Clock
nDIM
COMP
REFERENCE
CURRENT
LIMIT
CSH
HSN
HSP
EN
OVP
HYSTERESIS
S
R
Q
UVLO
DDRV
GATE
GND
OVP
OVLO
Regulator
Thermal
Limit
TLIM
OVLO
Standby
Dimming
Reset
Dominant
RT
820k
LEB
1.24V
6.9V LDO
(4.1V)
LEB
W = 240 ns
UVLO
HYSTERESIS
1.24V
VCC
1.24V
VCC
1.24V
0.245V
VCC
VCC UVLO
VIN
20 PA
20 PA
Oscillator
10 PA
90k
1.7k
100k100k
100k 100k
100k
100k
1.24V
10 PACOMP
STANDBY
Artificial Ramp
VS
TREF
TSENSE
TGAIN
SS
SLOPE
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BLOCK DIAGRAM
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D=INO VV +
O
V
D= INO VV -
O
V
D= O
V
IN
V
t
iL (t)
ÂiL-PP
IL-MAX
IL-MIN
IL
0
TS
tON = DTStOFF = (1-D)TS
LM3424
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SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
THEORY OF OPERATION
The LM3424 is an N-channel MosFET (NFET) controller for buck, boost and buck-boost current regulators which
are ideal for driving LED loads. The controller has wide input voltage range allowing for regulation of a variety of
LED loads. The high-side differential current sense, with low adjustable threshold voltage, provides an excellent
method for regulating output current while maintaining high system efficiency. The LM3424 uses peak current
mode control providing good noise immunity and an inherent cycle-by-cycle current limit. The adjustable current
sense threshold provides the capability to amplitude (analog) dim the LED current and the thermal foldback
circuitry allows for precise temperature management of the LEDs. Tthe output enable/disable function coupled
with an internal dimming drive circuit provides high speed PWM dimming through the use of an external MosFET
placed at the LED load. When designing, the maximum attainable LED current is not internally limited because
the LM3424 is a controller. Instead it is a function of the system operating point, component choices, and
switching frequency allowing the LM3424 to easily provide constant currents up to 5A. This simple controller
contains all the features necessary to implement a high efficiency versatile LED driver.
Figure 19. Ideal CCM Regulator Inductor Current iL(t)
CURRENT REGULATORS
Current regulators can be designed to accomplish three basic functions: buck, boost, and buck-boost. All three
topologies in their most basic form contain a main switching MosFET, a recirculating diode, an inductor and
capacitors. The LM3424 is designed to drive a ground referenced NFET which is perfect for a standard boost
regulator. Buck and buck-boost regulators, on the other hand, usually have a high-side switch. When driving an
LED load, a ground referenced load is often not necessary, therefore a ground referenced switch can be used to
drive a floating load instead. The LM3424 can then be used to drive all three basic topologies as shown in the
Basic Topology Schematics section. Other topologies such as the SEPIC and flyback converter (both derivatives
of the buck-boost) can be implemented as well.
Looking at the buck-boost design, the basic operation of a current regulator can be analyzed. During the time
that the NFET (Q1) is turned on (tON), the input voltage source stores energy in the inductor (L1) while the output
capacitor (CO) provides energy to the LED load. When Q1 is turned off (tOFF), the re-circulating diode (D1)
becomes forward biased and L1 provides energy to both COand the LED load. Figure 19 shows the inductor
current (iL(t)) waveform for a regulator operating in CCM.
The average output LED current (ILED) is proportional to the average inductor current (IL) , therefore if ILis tightly
controlled, ILED will be well regulated. As the system changes input voltage or output voltage, the ideal duty cycle
(D) is varied to regulate ILand ultimately ILED. For any current regulator, D is a function of the conversion ratio:
Buck
(1)
Boost
(2)
Buck-boost
(3)
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VSNS = 1.24V x RCSH
RHSP
ICSH = RHSP
VSNS
RT
LM3424
RT Start tON
Oscillator
RFLT CAC
CFLT
External Synchronization
PWM
fSW = 1.40e-10 x RT - 1.95e-8
1
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
PEAK CURRENT MODE CONTROL
Peak current mode control is used by the LM3424 to regulate the average LED current through an array of
HBLEDs. This method of control uses a series resistor in the LED path to sense LED current and can use either
a series resistor in the MosFET path or the MosFET RDS-ON for both cycle-by-cycle current limit and input voltage
feed forward. The controller has a fixed switching frequency set by an internal programmable oscillator which
means current mode instability can occur at duty cycles higher than 50%. To mitigate this standard problem, an
aritifical ramp is added to the control signal internally. The slope of this ramp is programmable to allow for a
wider range of component choices for a given design. A detailed explanation of this control method is presented
in the following sections.
SWITCHING FREQUENCY
The switching frequency of the LM3424 is programmed using an external resistor (RT) connected from the RT pin
to GND as shown in Figure 20.
Alternatively, an external PWM signal can be applied to the RT pin through a filter (RFLT and CFLT) and an AC
coupling capacitor (CAC) to synchronize the part to an external clock as shown in Figure 20. If the external PWM
signal is applied at a frequency higher than the base frequency set by the RTresistor, the internal oscillator is
bypassed and the switching frequency becomes the synchronized frequency. The external synchronization signal
should have a pulse width of 100ns, an amplitude between 3V and 6V, and be AC coupled to the RT pin with a
ceramic capacitor (CAC = 100pF). A 10MHz RC filter (RFLT = 150Ωand CFLT = 100 pF) should be placed between
the PWM signal and CAC to eliminate unwanted high frequency noise from coupling into the RT pin.
The switching frequency is defined:
(4)
See the Typical Performance Characteristics section for a plot of RTvs. fSW.
Figure 20. Timing Circuitry
AVERAGE LED CURRENT
To first understand how the LM3424 regulates LED current, the thermal foldback functionality will be ignored.
Figure 21 shows the physical implementation of the LED current sense circuitry assuming the thermal foldback
circuitry is a simple current source which, for now, will be set to zero (ITF = 0A). The LM3424 uses an external
current sense resistor (RSNS) placed in series with the LED load to convert the LED current (ILED) into a voltage
(VSNS). The HSP and HSN pins are the inputs to the high-side sense amplifier which are forced to be equal
potential (VHSP=VHSN) through negative feedback. Because of this, the VSNS voltage is forced across RHSP which
generates a current that is summed with the thermal foldback current (ITF) to generate the signal current (ICSH)
which flows out of the CSH pin and through the RCSH resistor. The error amplifier will regulate the CSH pin to
1.24V and assuming ITF = 0A, ICSH can be calculated:
(5)
This means VSNS will be regulated as follows:
(6)
14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
RSNS
ILED RHSP
RHSN HSN
HSP High-Side
Sense Amplifier
CSH
1.24V
CCMP
RCSH
COMP
Error Amplifier
VSNS
To PWM
Comparator
LM3424
ICSH
ITF
100k100k
100k 100k
TREF
TSENSE
TGAIN
2.45VVS
RREF2
RREF1 RBIAS
RNTC
RGAIN
VDIF
LM94022
Precision Temp Sensor
NTC
RSNS
ILED RHSP
RHSN HSN
HSP High-Side
Sense Amplifier
CSH
1.24V
CCMP
RCSH
COMP
Error Amplifier
VSNS
To PWM
Comparator
LM3424
ITF
Thermal Foldback Current
ICSH
ILED = RSNS
1.24V
RSNS
VSNS RCSH
RHSP
= x
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
ILED can then be calculated:
(7)
The selection of the three resistors (RSNS, RCSH, and RHSP) is not arbitrary. For matching and noise performance,
the suggested signal current ICSH is approximately 100 µA. This current does not flow in the LEDs and will not
affect either the off-state LED current or the regulated LED current. ICSH can be above or below this value, but
the high-side amplifier offset characteristics may be affected slightly. In addition, to minimize the effect of the
high-side amplifier voltage offset on LED current accuracy, the minimum VSNS is suggested to be 50 mV. Finally,
a resistor (RHSN = RHSP) should be placed in series with the HSN pin to cancel out the effects of the input bias
current (~10 µA) of both inputs of the high-side sense amplifier.
Note that he CSH pin can also be used as a low-side current sense input regulated to 1.24V. The high-side
sense amplifier is disabled if HSP and HSN are tied to GND.
Figure 21. LED Current Sense Circuitry
Figure 22. Thermal Foldback Circuitry
THERMAL FOLDBACK / ANALOG DIMMING
Thermal foldback is necessary in many applications due to the extreme temperatures created in LED
environments. In general, two functions are necessary: a temperature breakpoint (TBK) after which the nominal
operating current needs to be reduced, and a slope corresponding to the amount of LED current decrease per
temperature increase as shown in Figure 23. The LM3424 allows the user to program both the breakpoint and
slope of the thermal foldback profile.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM3424
ITF = VTREF - VTSENSE
RGAIN
=
RREF1
RREF1 + RREF2
RNTC-BK
RNTC-BK + RBIAS
T
ILED
0TBK TEND
v1
RGAIN
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
Figure 23. Ideal Thermal Foldback Profile
Foldback is accomplished by adding current (ITF) to the CSH summing node. As more current is added, less
current is needed from the high side amplifier and correspondingly, the LED current is regulated to a lower value.
The final temperature (TEND) is reached when ITF = ICSH causing no current to be needed from the high-side
amplifier, yielding ILED = 0A.
Figure 22 shows how the thermal foldback circuitry is physically implemented in the system. ITF is set by placing
a differential voltage (VDIF = VTREF – VTSENSE) across TSENSE and TREF. VTREF can be set with a simple resistor
divider (RREF1 and RREF2) supplied from the VSvoltage reference (typical 2.45V). VTSENSE is set with a
temperature dependant voltage (as temperature increases, voltage should decrease).
An NTC thermistor is the most cost effective device used to sense temperature. As the temperature of the
thermistor increases, its resistance decreases (albeit non-linearly). Usually, the NTC manufacturer's datasheet
will detail the resistance-temperature characteristic of the thermistor. The thermistor will have a different
resistance (RNTC) at each temperature. The nominal resistance of an NTC is the resistance when the
temperature is 25°C (R25) and in many datasheets this will be given a multiplier of 1. Then the resistance at a
higher temperature will have a multiplier less than 1 (i.e. R85 multiplier is 0.161 therefore R85 = 0.161 x R25).
Given a desired TBK and TEND, the corresponding resistances at those temperatures (RNTC-BK and RNTC-END) can
be found.
Using the NTC method, a resistor divider from VScan be implemented with a resistor connected between VSand
TSENSE and the NTC thermistor placed at the desired location and connected from TSENSE to GND. This will
ensure that the desired temperature-voltage characteristic occurs at TSENSE.
If a linear decrease over the foldback range is necessary, a precision temperature sensor such as the LM94022
can be used instead as shown in Figure 22. Either method can be used to set VTSENSE according to the
temperature. However, for the rest of this datasheet, the NTC method will be used for thermal foldback
calculations.
During operation, if VDIF < 0V, then the sensed temperature is less than TBK and the differential sense amplifier
will regulate its output to zero forcing ITF = 0. This maintains the nominal LED current and no foldback is
observed.
At TBK, VDIF = 0V exactly and ITF is still zero. Looking at the manufacturer's datasheet for the NTC thermistor,
RNTC-BK can be obtained for the desired TBK and the voltage relationship at the breakpoint (VTSENSE-BK = VTREF)
can be defined:
(8)
A general rule of thumb is to set RREF1 = RREF2 simplifying the breakpoint relationship to RBIAS = RNTC-BK.
If VDIF > 0V (temperature is above TBK), then the amplifier will regulate its output equal to the input forcing VDIF
across the resistor (RGAIN) connected from TGAIN to GND. RGAIN ultimately sets the slope of the LED current
decrease with respect to increasing temperature by changing ITF:
(9)
If an analog temperature sensor such as the LM94022 is used, then RBIAS and the NTC are not necessary and
VTENSE will be the direct voltage output of the sensor.
16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
ILED = (ICSH - IADD) x RHSP
RSNS¸
¹
·
¨
©
§
RADJ x VREF
IADD = RADJ + RMAX - VBE-Q6
¸
¹
·
¨
©
§
RBIAS
CSH
RCSH
LM3424
VCC
RBIAS
RMAX
Q6
Q7
RADJ
Q8
RADJ
Variable Current Source
Variable
Resistance
VS
ILED = (ICSH - ITF) x RHSP
RSNS¸
¹
·
¨
©
§
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
Since the NTC is not usually local to the controller, a bypass capacitor (CNTC) is suggested from TSENSE to
GND. If a capacitor is used at TSENSE, then a capacitor (CREF) of equal or greater value should be placed from
TREF to GND in order to ensure the controller does not start-up in foldback. Alternatively, a smaller CREF can be
used to create a fade-up function at start-up (see APPLICATIONS INFORMATION section).
Thermal foldback is simply analog dimming according to a specific profile, therefore any method of controlling the
differential voltage between TREF and TSENSE can be use to analog dim the LED current. The corresponding
LED current for any VDIF > 0V is defined:
(10)
The CSH pin can also be used to analog dim the LED current by adjusting the current sense voltage (VSNS),
similar to thermal foldback. There are several different methods to adjust VSNS using the CSH pin:
1. External variable resistance : Adjust a potentiometer placed in series with RCSH to vary VSNS.
2. External variable current source: Source current (0 µA to ICSH) into the CSH pin to adjust VSNS.
Figure 24. Analog Dimming Circuitry
In general, analog dimming applications require a lower switching frequency to minimize the effect of the leading
edge blanking circuit. As the LED current is reduced, the output voltage and the duty cycle decreases.
Eventually, the minimum on-time is reached. The lower the switching frequency, the wider the linear dimming
range. Figure 24 shows how both CSH methods are physically implemented.
Method 1 uses an external potentiometer in the CSH path which is a simple addition to the existing circuitry.
However, the LEDs cannot dim completely because there is always some resistance causing signal current to
flow. This method is also susceptible to noise coupling at the CSH pin since the potentiometer increases the size
of the signal current loop.
Method 2 provides a complete dimming range and better noise performance, though it is more complex. Like
thermal foldback, it simply sources current into the CSH pin, decreasing the amount of signal current that is
necessary. This method consists of a PNP current mirror and a bias network consisting of an NPN, 2 resistors
and a potentiometer (RADJ), where RADJ controls the amount of current sourced into the CSH pin. A higher
resistance value will source more current into the CSH pin causing less regulated signal current through RHSP,
effectively dimming the LEDs. Q7 and Q8 should be a dual pair PNP for best matching and performance. The
additional current (IADD) sourced into the CSH pin can be calculated:
(11)
The corresponding ILED for a specific IADD is:
(12)
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM3424
ILIM = 245 mV
RLIM
LM3424
IT
PWM
COMP
IS
RLIM
Q1 GATE
LEB
GND
0.245V
0.9V
Ramp
Ramp Ramp
Generator SLOPE
RDS-ON
Sensing
RLIM
Sensing
RSLP
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
THERMAL SHUTDOWN
The LM3424 includes thermal shutdown. If the die temperature reaches approximately 165°C the device will shut
down (GATE pin low), until it reaches approximately 140°C where it turns on again.
CURRENT SENSE/CURRENT LIMIT
The LM3424 achieves peak current mode control using a comparator that monitors the main MosFET (Q1)
transistor current, comparing it with the COMP pin voltage as shown in Figure 25. Further, it incorporates a
cycle-by-cycle over-current protection function. Current limit is accomplished by a redundant internal current
sense comparator. If the voltage at the current sense comparator input (IS) exceeds 245 mV (typical), the on
cycle is immediately terminated. The IS input pin has an internal N-channel MosFET which pulls it down at the
conclusion of every cycle. The discharge device remains on an additional 240 ns (typical) after the beginning of a
new cycle to blank the leading edge spike on the current sense signal. The leading edge blanking (LEB)
determines the minimum achievable on-time (tON-MIN).
Figure 25. Current Sense / Current Limit Circuitry
There are two possible methods to sense the transistor current. The RDS-ON of the main power MosFET can be
used as the current sense resistance because the IS pin was designed to withstand the high voltages present on
the drain when the MosFET is in the off state. Alternatively, a sense resistor located in the source of the MosFET
may be used for current sensing, however a low inductance (ESL) type is suggested. The cycle-by-cycle current
limit (ILIM) can be calculated using either method as the limiting resistance (RLIM):
(13)
In general, the external series resistor allows for more design flexibility, however it is important to ensure all of
the noise sensitive low power ground connections are connected together local to the controller and a single
connection is made to GND.
SLOPE COMPENSATION
The LM3424 has programmable slope compensation in order to provide stability over a wide range of operating
conditions. Without slope compensation, a well-known condition called current mode instability (or sub-harmonic
oscillation) can result if there is a perturbation of the MosFET current sense voltage at the IS pin, due to noise or
a some type of transient.
Through a mathematical / geometrical analysis of the inductor current (IL) and the corresponding control current
(IC, it can be shown that if D < 0.5, the effect of the perturbation will decrease each switching cycle and the
system will remain stable. However, if D > 0.5 then the perturbation will grow as shown in Figure 26, eventually
causing a "period doubling" effect where the effect of the perturbation remains, yielding current mode instability.
Looking at Figure 25, the positive PWM comparator input is the IS voltage, a mirror of ILduring tON, plus a typical
900 mV offset. The negative input of the PWM comparator is the COMP pin which is proportional to IC, the
threshold at which the main MosFET (Q1) is turned off.
18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
1P =Z1+D
OD Cr x
3
=
0U
T=SNSCSH RR500VD xxx
c620VD x
c
( ) LIM
LED RID1 xx+
( ) LIMHSP RRD1 xx+
x
=
¨
¨
©
§+s
1Z1P ¸
¸
¹
·
0U
T
U
T¨
¨
©
§-s
1Z1Z ¸
¸
¹
·
t
iL (t) IC
0
TS
Ideal
iL (t)
Actual
iL (t)
2TS
=
MA=e5.7 12
1
L
2x
VO
RRR SNSSLPT xx
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
The LM3424 mitigates current mode instability by implementing an aritifical ramp (commonly called slope
compensation) which is summed with the sensed MosFET current at the IS pin as shown in Figure 25. This
combined signal is compared to the COMP pin to generate the PWM signal. An increase in the ramp that is
added to the sense voltage will increase the maximum achievable duty cycle. It should be noted that as the
artificial ramp is increased more and more, the control method approaches standard voltage mode control and
the benefits of current mode control are reduced.
To program the slope compensation, an external resistor, RSLP, is connected from SLOPE to GND. This sets the
slope of the artificial ramp that is added to the MosFET current sense voltage. A smaller RSLP value will increase
the slope of the added ramp. A simple calculation is suggested to ensure any duty cycle is attainable while
preventing the addition of excessive ramp. This method requires the artifical ramp slope (MA) to be equal to half
the inductor slope during tOFF:
(14)
Figure 26. "Period Doubling" due to Current Mode Instability
CONTROL LOOP COMPENSATION
The LM3424 control loop is modeled like any current mode controller. Using a first order approximation, the
uncompensated loop can be modeled as a single pole created by the output capacitor and, in the boost and
buck-boost topologies, a right half plane zero created by the inductor, where both have a dependence on the
LED string dynamic resistance. There is also a high frequency pole in the model, however it is near the switching
frequency and plays no part in the compensation design process therefore it will be neglected. Since ceramic
capacitance is recommended for use with LED drivers due to long lifetimes and high ripple current rating, the
ESR of the output capacitor can also be neglected in the loop analysis. Finally, there is a DC gain of the
uncompensated loop which is dependent on internal controller gains and the external sensing network.
A buck-boost regulator will be used as an example case. See the Design Guide section for compensation of all
topologies.
The uncompensated loop gain for a buck-boost regulator is given by the following equation:
(15)
Where the uncompensated DC loop gain of the system is described as:
(16)
And the output pole (ωP1) is approximated:
(17)
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM3424
RSNS
ILED RHSP
RHSN HSN
HSP High-Side
Sense Amplifier
CSH 1.24V
CCMP
RCSH
COMP
Error Amplifier
VSNS
To PWM
Comparator
LM3424
CFS
RFS
sets öP3
RO
sets öP2
Thermal Foldback Current
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
100
80
60
40
20
0
-20
-40
-60
135
90
45
0
-45
-90
-135
-180
-225
1e-1 1e1 1e3 1e5 1e7
0° Phase Margin
öP1
PHASE
GAIN
öZ1
=Dr 2
Dc
x
1Z
ZL1Dx
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
And the right half plane zero (ωZ1) is:
(18)
Figure 27. Uncompensated Loop Gain Frequency Response
Figure 27 shows the uncompensated loop gain in a worst-case scenario when the RHP zero is below the output
pole. This occurs at high duty cycles when the regulator is trying to boost the output voltage significantly. The
RHP zero adds 20dB/decade of gain while loosing 45°/decade of phase which places the crossover frequency
(when the gain is zero dB) extremely high because the gain only starts falling again due to the high frequency
pole (not modeled or shown in figure). The phase will be below -180° at the crossover frequency which means
there is no phase margin (180° + phase at crossover frequency) causing system instability. Even if the output
pole is below the RHP zero, the phase will still reach -180° before the crossover frequency in most cases yielding
instability.
Figure 28. Compensation Circuitry
To mitigate this problem, a compensator should be designed to give adequate phase margin (above 45°) at the
crossover frequency. A simple compensator using a single capacitor at the COMP pin (CCMP) will add a dominant
pole to the system, which will ensure adequate phase margin if placed low enough. At high duty cycles (as
shown in Figure 27), the RHP zero places extreme limits on the achievable bandwidth with this type of
compensation. However, because an LED driver is essentially free of output transients (except catastrophic
failures open or short), the dominant pole approach, even with reduced bandwidth, is usually the best approach.
20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
VCMP
0tVCC tCMP tCO
t
0tVCC tCMP-SS tCO
0.9V
tSS
0.9V
0.7V
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
80
60
40
20
0
-20
-40
-60
-80
90
45
0
-45
-90
-135
-180
-225
-270
1e-1 1e1 1e3 1e5 1e7
GAIN
60° Phase Margin
PHASE
öP2
öP3
öP1
öZ1
x= 0U
TT -1 ¸
¸
¹
·
¨
¨
©
§s
Z1
Z
xx +1 ¸
¸
¹
·
¨
¨
©
§s
Z3P
+1 ¸
¸
¹
·
¨
¨
©
§s
Z2P
+1 ¸
¸
¹
·
¨
¨
©
§s
Z1P
1
3P =Z
FSFS CR x
1
2P =Z
CMP
6Ce5 x
:
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
The dominant compensation pole (ωP2) is determined by CCMP and the output resistance (RO) of the error
amplifier (typically 5 MΩ):
(19)
It may also be necessary to add one final pole at least one decade above the crossover frequency to attenuate
switching noise and, in some cases, provide better gain margin. This pole can be placed across RSNS to filter the
ESL of the sense resistor at the same time. Figure 28 shows how the compensation is physically implemented in
the system.
The high frequency pole (ωP3) can be calculated:
(20)
The total system transfer function becomes:
(21)
The resulting compensated loop gain frequency response shown in Figure 29 indicates that the system has
adequate phase margin (above 45°) if the dominant compensation pole is placed low enough, ensuring stability:
Figure 29. Compensated Loop Gain Frequency Response
Figure 30. Start-up Waveforms
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM3424
1.24V
20 PA
LM3424
ROV2
ROV1
VO
OVLO
OVP
COSSSSCMPVCCSSSU ttttt +++= --
COCMPVCCSU tttt ++=
SSSSSS C20 kCt x:
=
x
=PA
10 V2.0
CMPCMPCMP - SS C28Ct x
k:
=
x
=PA
25
0.70V
OCO Ct x
=O
V
LED
I
CMPCMP
CMP C36Ct x
k:
=
x
=PA
25
0.9V
BYPBYPVCC C168Ct x:
=
x
=mA25 V2.4
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
START-UP REGULATOR and SOFT-START
The LM3424 includes a high voltage, low dropout bias regulator. When power is applied, the regulator is enabled
and sources current into an external capacitor (CBYP) connected to the VCC pin. The recommended bypass
capacitance for the VCC regulator is 2.2 µF to 3.3 µF. The output of the VCC regulator is monitored by an internal
UVLO circuit that protects the device from attempting to operate with insufficient supply voltage and the supply is
also internally current limited.
The LM3424 also has programmable soft-start, set by an external capacitor (CSS), connected from SS to GND.
For CSS to affect start-up, CREF > CNTC must be maintained so that the converter does not start in foldback mode.
Figure 30 shows the typical start-up waveforms for the LM3424 assuming CREF > CNTC.
First, CBYP is charged to be above VCC UVLO threshold (~4.2V). The CVCC charging time (tVCC) can be estimated
as:
(22)
Assuming there is no CSS or if CSS is less than 40% of CCMP , CCMP is then charged to 0.9V over the charging
time (tCMP) which can be estimated as:
(23)
Once CCMP = 0.9V, the part starts switching to charge COuntil the LED current is in regulation. The COcharging
time (tCO) can be roughly estimated as:
(24)
If CSS is greater than 40% of CCMP, the compensation capacitor will only charge to 0.7V over a smaller CCMP
charging time (tCMP-SS) which can be estimated as:
(25)
Then COMP will clamp to SS, forcing COMP to rise (the last 200 mV before switching begins) according to the
CSS charging time (tSS) which can be estimated as:
(26)
The system start-up time (tSU or tSU-SS) is defined as:
CSS < 0.4 x CCMP (27)
CSS > 0.4 x CCMP (28)
As a general rule of thumb, standard smooth startup operation can be achieved with CSS = CCMP.
OVER-VOLTAGE LOCKOUT (OVLO)
Figure 31. Over-Voltage Protection Circuitry
22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
1.24V
20 PA
LM3424
RUV2
RUV1
VIN
UVLO
nDIM
RUVH
(optional)
LM3424
OVP
ROV2
ROV1
LED+
LED-
2OVHYSO RA20V xP=
¸
¸
¹
·
¨
¨
©
§
x
=
-OFFTURN 24V.1V x+
OV1 OV2
R5.0 R
1OV
R
1¸
¸
¹
·
¨
¨
©
§
x
=
-OFFTURN 24V.1V 1OV
R+2OVOV RR
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
The LM3424 can be configured to detect an output (or input) over-voltage condition via the OVP pin. The pin
features a precision 1.24V threshold with 20 µA (typical) of hysteresis current as shown in Figure 31. When the
OVLO threshold is exceeded, the GATE pin is immediately pulled low and a 20 µA current source provides
hysteresis to the lower threshold of the OVLO hysteretic band.
If the LEDs are referenced to a potential other than ground (floating), as in the buck-boost and buck
configuration, the output voltage (VO) should be sensed and translated to ground by using a single PNP as
shown in Figure 32.
The over-voltage turn-off threshold (VTURN-OFF) is defined:
Ground Referenced
(29)
Floating
(30)
In the ground referenced configuration, the voltage across ROV2 is VO- 1.24V whereas in the floating
configuration it is VO- 620 mV where 620 mV approximates VBE of the PNP.
The over-voltage hysteresis (VHYSO) is defined: (31)
Figure 32. Floating Output OVP Circuitry
INPUT UNDER-VOLTAGE LOCKOUT (UVLO)
The nDIM pin is a dual-function input that features an accurate 1.24V threshold with programmable hysteresis as
shown in Figure 33. This pin functions as both the PWM dimming input for the LEDs and as a VIN UVLO. When
the pin voltage rises and exceeds the 1.24V threshold, 20 µA (typical) of current is driven out of the nDIM pin into
the resistor divider providing programmable hysteresis.
Figure 33. UVLO Circuit
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LM3424
LM3424
RUV2
RUV1
VIN
nDIM
RUVH
QDIM
DDIM
Inverted
PWM
Standard
PWM
x
PA20
=
HYS
V¨
¨
©
§+
2UV
R¸
¸
¹
·
1UV
R
(+
x1UV
R)
2UV
R
UVH
R
2UV
RA20 x
P
HYS
V=
1¸
¸
¹
·
¨
¨
©
§
x
=
-ONTURN 24V.1V 1UV
R+2UVUV RR
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
When using the nDIM pin for UVLO and PWM dimming concurrently, the UVLO circuit can have an extra series
resistor to set the hysteresis. This allows the standard resistor divider to have smaller resistor values minimizing
PWM delays due to a pull-down MosFET at the nDIM pin (see PWM DIMMING section). In general, at least 3V
of hysteresis is preferable when PWM dimming, if operating near the UVLO threshold.
The turn-on threshold (VTURN-ON) is defined as follows:
(32)
The hysteresis (VHYS) is defined as follows:
UVLO only (33)
PWM dimming and UVLO
(34)
PWM DIMMING
The active low nDIM pin can be driven with a PWM signal which controls the main NFET and the dimming FET
(dimFET). The brightness of the LEDs can be varied by modulating the duty cycle of this signal. LED brightness
is approximately proportional to the PWM signal duty cycle, (i.e. 30% duty cycle ~ 30% LED brightness). This
function can be ignored if PWM dimming is not required by using nDIM solely as a VIN UVLO input as described
in the INPUT UNDER-VOLTAGE LOCKOUT (UVLO) section or by tying it directly to VCC or VIN.
Figure 34. PWM Dimming Circuit
Figure 34 shows how the PWM signal is applied to nDIM:
1. Connect the dimming MosFET (QDIM) with the drain to the nDIM pin and the source to GND. Apply an
external logic-level PWM signal to the gate of QDIM.
2. Connect the anode of a Schottky diode (DDIM) to the nDIM pin. Apply an inverted external logic-level PWM
signal to the cathode of the same diode.
The DDRV pin is a PWM output that follows the nDIM PWM input signal. When the nDIM pin rises, the DDRV pin
rises and the PWM latch reset signal is removed allowing the main MosFET Q1 to turn on at the beginning of the
next clock set pulse. In boost and buck-boost topologies, the DDRV pin is used to control a N-channel MosFET
placed in series with the LED load, while it would control a P-channel MosFET in parallel with the load for a buck
topology.
The series dimFET will open the LED load, when nDIM is low, effectively speeding up the rise and fall times of
the LED current. Without any dimFET, the rise and fall times are limited by the inductor slew rate and dimming
frequencies above 1 kHz are impractical. Using the series dimFET, dimming frequencies up to 30 kHz are
achievable. With a parallel dimFET (buck topology), even higher dimming frequencies are achievable.
24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
RSNS
LM3424
DDRV
100 nF
100
k:
Q2
10V
RSNS
LED+
Q7
Q6 Q4
10V VIN
5 k:
LM3424
500:
DDRV
VCC
100 pF
Q2
100 nF
10:
tPULSE = 2 x ILED x VO X L1
VIN2
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
When using the PWM functionality in a boost regulator, the PWM signal drives a ground referenced FET.
However, with buck-boost and buck topologies, level shifting circuitry is necessary to translate the PWM dim
signal to the floating dimFET as shown in Figure 35 and Figure 36.
When using a series dimFET to PWM dim the LED current, more output capacitance is always better. A general
rule of thumb is to use a minimum of 40 µF when PWM dimming. For most applications, this will provide
adequate energy storage at the output when the dimFET turns off and opens the LED load. Then when the
dimFET is turned back on, the capacitance helps source current into the load, improving the LED current rise
time.
A minimum on-time must be maintained in order for PWM dimming to operate in the linear region of its transfer
function. Because the controller is disabled during dimming, the PWM pulse must be long enough such that the
energy intercepted from the input is greater than or equal to the energy being put into the LEDs. For boost and
buck-boost regulators, the minimum dimming pulse length in seconds (tPULSE) is:
(35)
Even maintaining a dimming pulse greater than tPULSE, preserving linearity at low dimming duty cycles is difficult.
Several modifications are suggested for applications requiring low dimming duty cycles. Since nDIM rising
releases the latch but does not trigger the on-time specifically, there will be an effective jitter on the rising edge of
the LED current. This jitter can be easily removed by tying the PWM input signal through the synchronization
network at the RT pin (shown in Figure 20), forcing the on-time to synchronize with the nDIM pulse.
The second helpful modification is to remove the CFS capacitor and RFS resistor, eliminating the high frequency
compensation pole. This should not affect stability, but it will speed up the response of the CSH pin, specifically
at the rising edge of the LED current when PWM dimming, thus improving the achievable linearity at low dimming
duty cycles.
Figure 35. Buck-boost Level-Shifted PWM Circuit
Figure 36. Buck Level-Shifted PWM Circuit
Design Considerations
This section describes the application level considerations when designing with the LM3424. For corresponding
calculations, refer to the Design Guide section.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 25
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INDUCTOR
The inductor (L1) is the main energy storage device in a switching regulator. Depending on the topology, energy
is stored in the inductor and transferred to the load in different ways (as an example, buck-boost operation is
detailed in the CURRENT REGULATORS section). The size of the inductor, the voltage across it, and the length
of the switching subinterval (tON or tOFF) determines the inductor current ripple (ΔiL-PP ). In the design process, L1
is chosen to provide a desired ΔiL-PP. For a buck regulator the inductor has a direct connection to the load, which
is good for a current regulator. This requires little to no output capacitance therefore ΔiL-PP is basically equal to
the LED ripple current ΔiLED-PP. However, for boost and buck-boost regulators, there is always an output
capacitor which reduces ΔiLED-PP, therefore the inductor ripple can be larger than in the buck regulator case
where output capacitance is minimal or completely absent.
In general, ΔiLED-PP is recommended by manufacturers to be less than 40% of the average LED current (ILED).
Therefore, for the buck regulator with no output capacitance, ΔiL-PP should also be less than 40% of ILED. For the
boost and buck-boost topologies, ΔiL-PP can be much higher depending on the output capacitance value.
However, ΔiL-PP is suggested to be less than 100% of the average inductor current (IL) to limit the RMS inductor
current.
L1 is also suggested to have an RMS current rating at least 25% higher than the calculated minimum allowable
RMS inductor current (IL-RMS).
LED DYNAMIC RESISTANCE
When the load is a string of LEDs, the output load resistance is the LED string dynamic resistance plus RSNS.
LEDs are PN junction diodes, and their dynamic resistance shifts as their forward current changes. Dividing the
forward voltage of a single LED (VLED) by the forward current (ILED) leads to an incorrect calculation of the
dynamic resistance of a single LED (rLED). The result can be 5 to 10 times higher than the true rLED value.
Figure 37. Dynamic Resistance
Obtaining rLED is accomplished by referring to the manufacturer's LED I-V characteristic. It can be calculated as
the slope at the nominal operating point as shown in Figure 37. For any application with more than 2 series
LEDs, RSNS can be neglected allowing rDto be approximated as the number of LEDs multiplied by rLED.
OUTPUT CAPACITOR
For boost and buck-boost regulators, the output capacitor (CO) provides energy to the load when the recirculating
diode (D1) is reverse biased during the first switching subinterval. An output capacitor in a buck topology will
simply reduce the LED current ripple (ΔiLED-PP) below the inductor current ripple (ΔiL-PP). In all cases, COis sized
to provide a desired ΔiLED-PP. As mentioned in the INDUCTOR section, ΔiLED-PP is recommended by
manufacturers to be less than 40% of the average LED current (ILED-PP).
COshould be carefully chosen to account for derating due to temperature and operating voltage. It must also
have the necessary RMS current rating. Ceramic capacitors are the best choice due to their high ripple current
rating, long lifetime, and good temperature performance. An X7R dieletric rating is suggested.
26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
LM3424
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SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
INPUT CAPACITORS
The input capacitance (CIN) provides energy during the discontinuous portions of the switching period. For buck
and buck-boost regulators, CIN provides energy during tON and during tOFF, the input voltage source charges up
CIN with the average input current (IIN). For boost regulators, CIN only needs to provide the ripple current due to
the direct connection to the inductor. CIN is selected given the maximum input voltage ripple (ΔvIN-PP) which can
be tolerated. ΔvIN-PP is suggested to be less than 10% of the input voltage (VIN).
An input capacitance at least 100% greater than the calculated CIN value is recommended to account for derating
due to temperature and operating voltage. When PWM dimming, even more capacitance can be helpful to
minimize the large current draw from the input voltage source during the rising transistion of the LED current
waveform.
The chosen input capacitors must also have the necessary RMS current rating. Ceramic capacitors are again the
best choice due to their high ripple current rating, long lifetime, and good temperature performance. An X7R
dieletric rating is suggested.
For most applications, it is recommended to bypass the VIN pin will an 0.1 µF ceramic capacitor placed as close
as possible to the pin. In situations where the bulk input capacitance may be far from the LM3424 device, a 10 Ω
series resistor can be placed between the bulk input capacitance and the bypass capacitor, creating a 150 kHz
filter to eliminate undesired high frequency noise.
MAIN MosFET / DIMMING MosFET
The LM3424 requires an external NFET (Q1) as the main power MosFET for the switching regulator. Q1 is
recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe
operation during the ringing of the switch node. In practice, all switching regulators have some ringing at the
switch node due to the diode parasitic capacitance and the lead inductance. The current rating is recommended
to be at least 10% higher than the average transistor current. The power rating is then verified by calculating the
power loss given the RMS transistor current and the NFET on-resistance (RDS-ON).
When PWM dimming, the LM3424 requires another MosFET (Q2) placed in series (or parallel for a buck
regulator) with the LED load. This MosFET should have a voltage rating equal to the output voltage (VO) and a
current rating at least 10% higher than the nominal LED current (ILED) . The power rating is simply VOmultiplied
by ILED, assuming 100% dimming duty cycle (continuous operation) will occur.
In general, the NFETs should be chosen to minimize total gate charge (Qg) when fSW is high and minimize RDS-ON
otherwise. This will minimize the dominant power losses in the system. Frequently, higher current NFETs in
larger packages are chosen for better thermal performance.
RE-CIRCULATING DIODE
A re-circulating diode (D1) is required to carry the inductor current during tOFF. The most efficient choice for D1 is
a Schottky diode due to low forward voltage drop and near-zero reverse recovery time. Similar to Q1, D1 is
recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe
operation during the ringing of the switch node and a current rating at least 10% higher than the average diode
current. The power rating is verified by calculating the power loss through the diode. This is accomplished by
checking the typical diode forward voltage from the I-V curve on the product datasheet and multiplying by the
average diode current. In general, higher current diodes have a lower forward voltage and come in better
performing packages minimizing both power losses and temperature rise.
CIRCUIT LAYOUT
The performance of any switching regulator depends as much upon the layout of the PCB as the component
selection. Following a few simple guidelines will maximimize noise rejection and minimize the generation of EMI
within the circuit.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LM3424
SS
TGAIN
OVP
LM3424
nDIM
VIN
GND
TSENSE
TREF
DDRV
VS
COUT
DAP
GATE
EN
COMP
VIN
CSH
RT/SYNC
IS
HSN
SLOPE
VCC
HSP
Q2
D1
L1
CIN
RSLP
CBYP
RLIM
Q1
CCMP
RCSH
RT
CSS
ROV2
ROV1
RUV2
RUV1
RGAIN
NTC
RREF1
RREF2 RBIAS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RHSP
RHSN
CNTC
ILED
RSNS
RFS
CFS
COV
CREF
Q3 PWM
RUVH
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
Discontinuous currents are the most likely to generate EMI, therefore care should be taken when routing these
paths. The main path for discontinuous current in the LM3424 buck regulator contains the input capacitor (CIN),
the recirculating diode (D1), the N-channel MosFET (Q1), and the sense resistor (RLIM). In the LM3424 boost
regulator, the discontinuous current flows through the output capacitor (CO), D1, Q1, and RLIM. In the buck-boost
regulator both loops are discontinuous and should be carefully layed out. These loops should be kept as small as
possible and the connections between all the components should be short and thick to minimize parasitic
inductance. In particular, the switch node (where L1, D1 and Q1 connect) should be just large enough to connect
the components. To minimize excessive heating, large copper pours can be placed adjacent to the short current
path of the switch node.
The RT, COMP, CSH, IS, TSENSE, TREF, HSP and HSN pins are all high-impedance inputs which couple
external noise easily, therefore the loops containing these nodes should be minimized whenever possible.
In some applications the LED or LED array can be far away (several inches or more) from the LM3424, or on a
separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large or
separated from the rest of the regulator, the output capacitor should be placed close to the LEDs to reduce the
effects of parasitic inductance on the AC impedance of the capacitor.
Basic Topology Schematics
BOOST REGULATOR (VIN < VO)
28 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
SS
TGAIN
OVP
LM3424
nDIM
VIN
GND
TSENSE
TREF
DDRV
VS
COUT
DAP
GATE
EN
COMP
VIN
CSH
RT/SYNC
IS
HSN
SLOPE
VCC
HSP
D1
CIN
RSLP
CBYP
RLIM
Q1
CCMP
RCSH
RT
CSS
ROV2
ROV1
RUV2
RUV1
RGAIN
NTC
RREF1
RREF2 RBIAS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RHSP
RHSN
CNTC
ILED
RSNS
RFS
CFS
COV
CREF
Q3 PWM
RUVH
Q2
D2
CDIM
L1 Q5
DIM
DIM
RPU
LM3424
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SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
BUCK REGULATOR (VIN > VO)
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: LM3424
SS
TGAIN
OVP
LM3424
nDIM
VIN
GND
TSENSE
TREF
DDRV
VS
COUT
DAP
GATE
EN
COMP
VIN
CSH
RT/SYNC
IS
HSN
SLOPE
VCC
HSP
Q7
D1
L1
CIN
RSLP
CBYP
RLIM
Q1
CCMP
RCSH
RT
CSS
ROV2
ROV1
RUV2
RUV1
RGAIN
NTC
RREF1
RREF2 RBIAS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RHSP
RHSN
CNTC
ILED
RSNS
RFS
CFS
COV
CREF
Q3 PWM
RUVH
Q6
Q5
LED+
Q4
D2
VIN
LED+
VIN
DIM
DIM
RPU
RSER
Q2
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
BUCK-BOOST REGULATOR
30 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
RT = 1 + 1.95e-8 x fSW
1.40e-10 x fSW
D=INO VV +
O
V
D= INO VV -
O
V
D= O
V
IN
V
rD = N x rLED
VO = N x VLED
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
Design Guide
Refer to Basic Topology Schematics section.
SPECIFICATIONS
Number of series LEDs: N
Single LED forward voltage: VLED
Single LED dynamic resistance: rLED
Nominal input voltage: VIN
Input voltage range: VIN-MAX, VIN-MIN
Switching frequency: fSW
Current sense voltage: VSNS
Average LED current: ILED
Inductor current ripple: ΔiL-PP
LED current ripple: ΔiLED-PP
Peak current limit: ILIM
Input voltage ripple: ΔvIN-PP
Output OVLO characteristics: VTURN-OFF, VHYSO
Input UVLO characteristics: VTURN-ON, VHYS
Thermal foldback characteristics: TBK, TEND
Total start-up time: tTSU
1. OPERATING POINT
Given the number of series LEDs (N), the forward voltage (VLED) and dynamic resistance (rLED) for a single LED,
solve for the nominal output voltage (VO) and the nominal LED string dynamic resistance (rD): (36)
(37)
Solve for the ideal nominal duty cycle (D):
Buck
(38)
Boost
(39)
Buck-boost
(40)
Using the same equations, find the minimum duty cycle (DMIN) using maximum input voltage (VIN-MAX) and the
maximum duty cycle (DMAX) using the minimum input voltage (VIN-MIN). Also, remember that D' = 1 - D.
2. SWITCHING FREQUENCY
Set the switching frequency (fSW) by solving for RT:
(41)
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 31
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IL-RMS = 1 + 1
12 xILED
'IL-PP x D' ¸
¹
·
¨
©
§2
D'
ILED x
IL-RMS = ILED x 1 + 1
12 xILED
'IL-PP
¸
¹
·
¨
©
§2
L1= IN DV x
i
üSWPP-L fx
1L =)
ODV x
-
(IN
V
SWPP-L füix
GAIN
R=2
1
1REF V45.2
Rx
-¸
¸
¹
·
¨
¨
©
§ENDNTC
R-
BIASENDNTC RR +
-REFREF RR +
CSH
I
RREF1
RBIAS = RNTC-BK x RREF2
1.24V
RHSP =RRI SNSCSHLED xx
SNS
R = SNS
V
LED
I
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
3. AVERAGE LED CURRENT
For all topologies, set the average LED current (ILED) knowing the desired current sense voltage (VSNS) and
solving for RSNS:
(42)
If the calculated RSNS is too far from a desired standard value, then VSNS will have to be adjusted to obtain a
standard value.
Setup the suggested signal current of 100 µA by assuming RCSH = 12.4 kΩand solving for RHSP:
(43)
If the calculated RHSP is too far from a desired standard value, then RCSH can be adjusted to obtain a standard
value.
4. THERMAL FOLDBACK
For all topologies, set the thermal foldback breakpoint (TBK) by finding corresponding RNTC-BK from manufacturer's
datasheet and solving for RBIAS:
(44)
The easiest approach is to set RREF1 = RREF2, therefore setting RBIAS = RNTC-BK will properly set TBK. Remember,
capacitance is recommended at the TSENSE and TREF pins, so ensure CREF > CNTC to prevent start-up in
foldback.
Then set the thermal foldback endpoint (TEND) by finding the corresponding RNTC-END from manufacturer's
datasheet and solving for RGAIN:
(45)
5. INDUCTOR RIPPLE CURRENT
Set the nominal inductor ripple current (ΔiL-PP) by solving for the appropriate inductor (L1):
Buck
(46)
Boost and Buck-boost
(47)
To set the worst case inductor ripple current, use VIN-MAX and DMIN when solving for L1.
The minimum allowable inductor RMS current rating (IL-RMS) can be calculated as:
Buck
(48)
Boost and Buck-boost
(49)
32 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
x
=
¨
¨
©
§+s
1Z1P ¸
¸
¹
·
0U
T
U
T¨
¨
©
§-s
1Z1Z ¸
¸
¹
·
x
=
¨
¨
©
§+s
1Z1P ¸
¸
¹
·
0U
T
U
T1
SLP
R=SNSTO RRV xx 1Lx
13
e5.1
LIM
R=LIM
I
245 mV
1-DMAX
DMAX
ICO-RMS = ILED x
IRMSCO =
-12PP-LED
iü
O
C = SWPP-LEDD füir xx LED DI x
O
C = PPL
i-
'
PPLEDDSW irf8 -
'xxx
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
6. LED RIPPLE CURRENT
Set the nominal LED ripple current (ΔiLED-PP), by solving for the output capacitance (CO):
Buck
(50)
Boost and Buck-boost
(51)
To set the worst case LED ripple current, use DMAX when solving for CO. Remember, when PWM dimming it is
recommended to use a minimum of 40 µF of output capacitance to improve performance.
The minimum allowable RMS output capacitor current rating (ICO-RMS) can be approximated:
Buck
(52)
Boost and Buck-boost
(53)
7. PEAK CURRENT LIMIT
Set the peak current limit (ILIM) by solving for the transistor path sense resistor (RLIM):
(54)
8. SLOPE COMPENSATION
For all topologies, the preferred method to set slope compensation is to ensure any duty cycle is attainable for
the nominal VOand chosen L by solving for RSLP:
(55)
9. LOOP COMPENSATION
Using a simple first order peak current mode control model, neglecting any output capacitor ESR dynamics, the
necessary loop compensation can be determined.
First, the uncompensated loop gain (TU) of the regulator can be approximated:
Buck
(56)
Boost and Buck-boost
(57)
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Links: LM3424
1
=
CFS 3P
10xZ
max
3P =
Z( ) 10, 1Z1P x
ZZ
1
CMP
C=6
2P e5
x
Z
1Z1P )
,min( Z
Z
5x0U
T
2P =
Z
=
0U
T=SNSCSH RR500VD xxx
c620VD x
c
( ) LIM
LED RID1 xx+
( ) LIMHSP RRD1 xx+
=
0U
T=SNSCSH RR500VD xxx
c310VD x
c
LIMLED RI x
LIMHSP RR2 xx
SNS 620V
RR500V =
xx CSH
LIMLED RI x
0U
T=LIMHSP RR x
=Dr 2
Dc
x
1Z
ZL1Dx
=Dr 2
Dc
x
1Z
ZL1
1P =Z1+D
OD Cr x
3
1P =Z2
OD Cr x
3
1P =Z1
OD Cr x
3
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
Where the pole (ωP1) is approximated:
Buck
(58)
Boost
(59)
Buck-boost
(60)
And the RHP zero (ωZ1) is approximated:
Boost
(61)
Buck-boost
(62)
And the uncompensated DC loop gain (TU0) is approximated:
Buck
(63)
Boost
(64)
Buck-boost
(65)
For all topologies, the primary method of compensation is to place a low frequency dominant pole (ωP2) which
will ensure that there is ample phase margin at the crossover frequency. This is accomplished by placing a
capacitor (CCMP) from the COMP pin to GND, which is calculated according to the lower value of the pole and the
RHP zero of the system (shown as a minimizing function):
(66)
(67)
If analog dimming is used, CCMP should be approximately 4x larger to maintain stability as the LEDs are dimmed
to zero.
A high frequency compensation pole (ωP3) can be used to attenuate switching noise and provide better gain
margin. Assuming RFS = 10Ω, CFS is calculated according to the higher value of the pole and the RHP zero of
the system (shown as a maximizing function):
(68)
(69)
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Product Folder Links: LM3424
OMAXINMAXT VVV +
=--
O
V
=
MAXT
V-
MAXINMAXT VV -- =
1-DMAX
DMAX
ICIN-RMS = ILED x
12
ICIN-RMS = 'iL-PP
(1-DMID)DII LEDRMSCIN xx=
-MID
CIN = 'VIN-PP x fSW
ILED x D
CIN = 8 x 'VIN-PP x fSW
'iL-PP
CIN = ILED x (1 - D) x D
'VIN-PP x fSW
x= 0U
TT -1 ¸
¸
¹
·
¨
¨
©
§s
Z1
Z
xx +1 ¸
¸
¹
·
¨
¨
©
§s
Z3P
+1 ¸
¸
¹
·
¨
¨
©
§s
Z2P
+1 ¸
¸
¹
·
¨
¨
©
§s
Z1P
x= 0U
TT 1
xx +1 ¸
¸
¹
·
¨
¨
©
§s
Z3P
+1 ¸
¸
¹
·
¨
¨
©
§s
Z2P
+1 ¸
¸
¹
·
¨
¨
©
§s
Z1P
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
The total system loop gain (T) can then be written as:
Buck
(70)
Boost and Buck-boost
(71)
10. INPUT CAPACITANCE
Set the nominal input voltage ripple (ΔvIN-PP) by solving for the required capacitance (CIN):
Buck
(72)
Boost
(73)
Buck-boost
(74)
Use DMAX to set the worst case input voltage ripple, when solving for CIN in a buck-boost regulator and DMID = 0.5
when solving for CIN in a buck regulator.
The minimum allowable RMS input current rating (ICIN-RMS) can be approximated:
Buck
(75)
Boost
(76)
Buck-boost
(77)
11. NFET
The NFET voltage rating should be at least 15% higher than the maximum NFET drain-to-source voltage (VT-
MAX):
Buck (78)
Boost (79)
Buck-boost (80)
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Links: LM3424
ROV1=R1.24V OV2
xVm620V OFFTURN -
-
ROV1 =1.24VV OFFTURN -
-
R1.24V OV2
x
ROV2 =VHYSO
A20P
FDDD VIP x=
ID-MAX = ILED
ID-MAX = (1 - DMIN) x ILED
VRD-MAX = VIN-MAX + VO
VRD-MAX = VO
VRD-MAX = VIN-MAX
DSON
2
RMSTT RIP x= -
IRMST =
-D
x
ILED
Dc
DIT- ILEDRMS x=
IT-MAX = x ILED
1 - DMAX
DMAX
IT-MAX = DMAX x ILED
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
The current rating should be at least 10% higher than the maximum average NFET current (IT-MAX):
Buck (81)
Boost and Buck-boost
(82)
Approximate the nominal RMS transistor current (IT-RMS) :
Buck
(83)
Boost and Buck-boost
(84)
Given an NFET with on-resistance (RDS-ON), solve for the nominal power dissipation (PT):
(85)
12. DIODE
The Schottky diode voltage rating should be at least 15% higher than the maximum blocking voltage (VRD-MAX):
Buck (86)
Boost (87)
Buck-boost (88)
The current rating should be at least 10% higher than the maximum average diode current (ID-MAX):
Buck (89)
Boost and Buck-boost (90)
Replace DMAX with D in the ID-MAX equation to solve for the average diode current (ID). Given a diode with forward
voltage (VFD), solve for the nominal power dissipation (PD): (91)
13. OUTPUT OVLO
For boost and buck-boost regulators, output OVLO is programmed with the turn-off threshold voltage (VTURN-OFF)
and the desired hysteresis (VHYSO). To set VHYSO, solve for ROV2:
(92)
To set VTURN-OFF, solve for ROV1:
Boost
(93)
Buck-boost
(94)
36 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
( )
BASESSSUTSUSS ttC --
-x
=V2.0 A10P
OCMPBYPBASESSSU CCk28C168t x
+
x:
+
x:
=
-- O
V
LED
I
COCMPVCCSU tttt ++=
( )
RR +x 2UV1UV
A20P
( )
xHYS A20V xP- R 2UV
R1UV
UVH
R =
RUV1 =1.24VV ONTURN -
-
R1.24V UV2
x
RUV2 =A20P
VHYS
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
A small filter capacitor (COVP = 47 pF) should be added from the OVP pin to ground to reduce coupled switching
noise.
14. INPUT UVLO
For all topologies, input UVLO is programmed with the turn-on threshold voltage (VTURN-ON) and the desired
hysteresis (VHYS).
Method #1: If no PWM dimming is required, a two resistor network can be used. To set VHYS, solve for RUV2:
(95)
To set VTURN-ON, solve for RUV1:
(96)
Method #2: If PWM dimming is required, a three resistor network is suggested. To set VTURN-ON, assume RUV2 =
10 kΩand solve for RUV1 as in Method #1. To set VHYS, solve for RUVH:
(97)
15. SOFT-START
For all topologies, if soft-start is desired, find the start-up time without CSS (tSU): (98)
Then, if the desired total start-up time (tTSU) is larger than tSU, solve for the base start-up time (tSU-SS-BASE),
assuming that a CSS greater than 40% of CCMP will be used:
(99)
Then solve for CSS:
(100)
16. PWM DIMMING METHOD
PWM dimming can be performed several ways:
Method #1: Connect the dimming MosFET (Q3) with the drain to the nDIM pin and the source to GND. Apply an
external PWM signal to the gate of QDIM. A pull down resistor may be necessary to properly turn off Q3.
Method #2: Connect the anode of a Schottky diode to the nDIM pin. Apply an external inverted PWM signal to
the cathode of the same diode.
The DDRV pin should be connected to the gate of the dimFET with or without level-shifting circuitry as described
in the PWM DIMMING section. The dimFET should be rated to handle the average LED current and the nominal
output voltage.
17. ANALOG DIMMING METHOD
Analog dimming can be performed several ways:
Method #1: Place a potentiometer in place of the thermistor in the thermal foldback circuit shown in the
THERMAL FOLDBACK / ANALOG DIMMING section.
Method #2: Place a potentiometer in series with the RCSH resistor to dim the LED current from the nominal ILED
to near zero.
Method #3: Connect a controlled current source as detailed in the THERMAL FOLDBACK / ANALOG DIMMING
section to the CSH pin. Increasing the current sourced into the CSH node will decrease the LEDs from the
nominal ILED to zero current in the same manner as the thermal foldback circuit.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Links: LM3424
SS
TGAIN
OVP
LM3424
nDIM
VIN
GND
TSENSE
TREF
DDRV
VS
COUT
DAP
GATE
EN
COMP
VIN
CSH
RT/SYNC
IS
HSN
SLOPE
VCC
HSP
D1
L1
CIN
RSLP
CBYP
RLIM
Q1
CCMP
RCSH
RT
CSS ROV2
ROV1
RUV2
RUV1
RGAIN
NTC
RREF1
RREF2 RBIAS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RHSP
RHSN
CNTC
1A
ILED
RSNS
RFS
CFS
COV
CREF
Q2
VIN
10V ± 70V
VIN
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
Design Example
DESIGN #1 - BUCK-BOOST Application
38 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
DMAX == 677.0
=
V21 V10V21 +
VO
VV IN-MINO +
21V
=21V + 70V = 0.231
DMIN = VO + VIN-MAX
VO
533.0467.01D1'D =
-
=
-
=
D== 467.0
=
V21 V24V21 +
VOVV INO +
:
=
:x
=
x
=95.1m3256rNr LEDD
V21V5.36VNV LEDO =
x
=
x
=
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
SPECIFICATIONS
N=6
VLED = 3.5V
rLED = 325 mΩ
VIN = 24V
VIN-MIN = 10V
VIN-MAX = 70V
fSW = 500 kHz
VSNS = 100 mV
ILED = 1A
ΔiL-PP = 700 mA
ΔiLED-PP = 12 mA
ΔvIN-PP = 100 mV
ILIM = 6A
VTURN-ON = 10V
VHYS = 3V
VTURN-OFF = 40V
VHYSO = 10V
TBK = 70°C
TEND= 120°C
tTSU = 30 ms
1. OPERATING POINT
Solve for VOand rD:(101)
(102)
Solve for D, D', DMAX, and DMIN:
(103)
(104)
(105)
(106)
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 39
Product Folder Links: LM3424
:
k243RBIAS =
:
k49.9RR REF2 ==
REF1
6.81RGAIN =:
k
:
=
x
-
=
x-
=
k68.6
2
1
R
R
GAIN
GAIN
¸
¸
¹
·
¸
¸
¹
·
¨
¨
©
§
¨
¨
©
§
V45.2
V45.2
PA100
ICSH
+RR 2REF1REF +
-RR BIASENDNTC
-
RENDNTC
R1REF
:+:k24.3k7.15 :k7.15
:
k4.21RCSH =
:
k1RR HSN ==
HSP
0.1R NSS =:
ILED = = k0.11.24V :xA0.1=
k4.121.0 :x:
RR CSHSNS xR1.24V HSP
x
=1.24V1.24V
=
RHSP :
=k0.1
:
x
:
x0.1k12.4A1
xx RRI SNSCSHLED
:
=== 1.0
1A
RSNS ILED
mV100
VSNS
RT = 14.3 k:
kHz504
1
1
fSW
==
=
e95.1k3.14e40.1 810 -
:x-
-
e95.1Re40.1 8
T
10 -
x--
fSW
:
== k4.14
=
RTx+ -f
e
95.11 SW
8x+ -kHz500e95.11 8
x
-fe40.1 SW
10 x
-kHz500e40.1 10
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
2. SWITCHING FREQUENCY
Solve for RT:
(107)
The closest standard resistor is 14.3 kΩtherefore fSW is:
(108)
The chosen component from step 2 is:
(109)
3. AVERAGE LED CURRENT
Solve for RSNS:
(110)
Assume RCSH = 12.4 kΩand solve for RHSP:
(111)
The closest standard resistor for RSNS is actually 0.1Ωand for RHSP is actually 1 kΩtherefore ILED is:
(112)
The chosen components from step 3 are:
(113)
4. THERMAL FOLDBACK
Find the resistances corresponding to TBK and TEND (RNTC-BK = 24.3 kΩand RNTC-END = 7.15 kΩ) from the
manufacturer's datasheet. Assuming RREF1 = RREF2 = 49.9 kΩ, then RBIAS = RNTC-BK= 24.3 kΩ.
Solve for RGAIN:
(114)
The chosen components from step 4 are:
(115)
40 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
0.04:RLIM =
:04.0 === 6.13A
mV245mV245
ILIM RLIM
:=== 041.0
6A
RLIM mV245mV245
ILIM
CO = 4 x 10 PF
x
A1
=ILED
IRMSCO- =
1- 0.677
677.0 1.45A
x1- DMAX
DMAX =
DILED x
=
'iPP-LED SW
fxrDxCO
2
= =
kHz04595.1 xx:1 mA
467.0A1 x F40P
'iPP-LED
f
'i
rSWPP-LEDD xx DILED x
CO=
2
= F39.6P=
kHz045mA195.1 xx:
467.0A1 x
CO
H331L P
=
A89.1
12
1
1
IRMSL =
+
x
=
-
I
ILED
RMSL x
=
-12
1
12
x
+¸
¸
¹
·
¨
¨
©
§Di PPL c
x
'-
ILED
Dc
533.0mA674 2
x¸
¸
¹
·
¨
¨
©
§A1
x
533.0 A1
PP- ==
LDVIN xf1L SW
xkHz045H33 xP
467.0V42 x mA674
=
'i
== DVIN xfSW
x467.0V42 x PH
32
=
1L PP-
'iLkHz045700 mAx
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
5. INDUCTOR RIPPLE CURRENT
Solve for L1:
(116)
The closest standard inductor is 33 µH therefore ΔiL-PP is:
(117)
Determine minimum allowable RMS current rating:
(118)
The chosen component from step 5 is:
(119)
6. OUTPUT CAPACITANCE
Solve for CO:
(120)
The closest capacitance totals 40 µF therefore ΔiLED-PP is:
(121)
Determine minimum allowable RMS current rating:
(122)
The chosen components from step 6 are:
(123)
7. PEAK CURRENT LIMIT
Solve for RLIM:
(124)
The closest standard resistor is 0.04 Ωtherefore ILIM is:
(125)
The chosen component from step 7 is:
(126)
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 41
Product Folder Links: LM3424
F27.0CFS P=
F0.33CCMP P=
:10RFS =
1
=F28.0
1P==CFS 10:xsec
rad
k360
10:3P
Zx
1010(max 1Z xZ
=
x
=,1Z1P ZZ
=
3P
Z
3P
Z
)
sec
rad
k36 sec
rad
k36010=
x
F30.0
1
1
CCMP P=== 675.0 e5
sec
rad 6
x:
e5 6
2P xZ:
= = sec
rad
675.0=
sec
rad
k19
56305x56305x 1P
Z
2P =Z),min( 1Z1P ZZ
T5 0U
x
=T 0U = 5630=
04.0A1467.1 :
xx V620533.0 x
( )
D1+RI LIMLED xx V620D x
c
sec
rad
k36=== 533.095.1 2
x:H33467.0 Px
Dr 2
Dc
xL1Dx
1Z
Z
sec
rad
k19=== 1.467 F40
1.95:Px
CO
rDxD1+
1P
Z
:
16.5RSLP k
=
=
RSLP x 1Le5.1 13
xx RRV SNSTO
= = :k5.16
Px H33e5.1 13
x:x k3.14V21 :1.0
RSLP
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
8. SLOPE COMPENSATION
Solve for RSLP:
(127)
The chosen component from step 8 is:
(128)
9. LOOP COMPENSATION
ωP1 is approximated:
(129)
ωZ1 is approximated:
(130)
TU0 is approximated:
(131)
To ensure stability, calculate ωP2:
(132)
Solve for CCMP:
(133)
To attenuate switching noise, calculate ωP3:
(134)
Assume RFS = 10Ωand solve for CFS:
(135)
The chosen components from step 9 are:
(136)
42 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
D1 o 12A, 100V, DPAK
mW600mV600A1VIP FDDD =
x
=
x
=
A1II LEDMAXD ==
-
V91V21V70VVV OMAXINMAXRD =
+
=
+
=--
Q1 o 32A, 100V, DPAK
mW82m50A28.1RIP 2
DSON
2
RMSTT =
:x
=
x
=-
x
IRMST =
-ILED
Dc=xA28.1
=
0.467
A1
533.0
D
=A2.1A1 =
x
677.01- 677.0
IMAXT-
V91V21V70VVV OMAXINMAXT =+=+= --
CIN = 4 x 4.7 PF
x
A1
=ILED
IRMSIN- =
1- 0.677
677.0 1.45A
x1- DMAX
DMAX =
CIN == kHz504mV100 x 467.0A1 x F27.9 P=
f
'vSWPPIN- x
DILED x
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
10. INPUT CAPACITANCE
Solve for the minimum CIN:
(137)
To minimize power supply interaction a 200% larger capacitance of approximately 20 µF is used, therefore the
actual ΔvIN-PP is much lower. Since high voltage ceramic capacitor selection is limited, four 4.7 µF X7R capacitors
are chosen.
Determine minimum allowable RMS current rating:
(138)
The chosen components from step 10 are:
(139)
11. NFET
Determine minimum Q1 voltage rating and current rating: (140)
(141)
A 100V NFET is chosen with a current rating of 32A due to the low RDS-ON = 50 mΩ. Determine IT-RMS and PT:
(142)
(143)
The chosen component from step 11 is:
(144)
12. DIODE
Determine minimum D1 voltage rating and current rating: (145)
(146)
A 100V diode is chosen with a current rating of 12A and VD= 600 mV. Determine PD:(147)
The chosen component from step 12 is:
(148)
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 43
Product Folder Links: LM3424
ROV1 = 15.8 k:
ROV2 = 499 k:
=
VOFFTURN =
-ROV1
k8.15 :
VOFFTURN-
()
RR1.24V OV2OV1+x 0.5x
( )
k499k8.151.24V :+:x 0.5xV= 39.8
:== k15.7
-
-0.62VV OFFTURN
xR1.24V OV2
=ROV1
:x k4991.24V- 0.62V40V
29.98VA20k499A20RV OVHYSO =
x:
=
x
=P
P
=== A
20
10V
ROV2 P:k500
VHYSO
A20P
k:501R 2UV =k:12R 1UV =
RUV1
()
RR1.24V UV2UV1+x
VONTURN =
-
= V10.1=
( )
k150k211.24V :+:xk21 :
VONTURN-
:== k2.21
-
-1.24VV ONTURN
xR1.24V UV2
=RUV1
:x k1501.24V-1.24V10V
3VA20k150A20RV 2UVHYS =
x:
=
x
=PP
=== A
20
3V
RUV2 P:k150
VHYS
A20P
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
13. INPUT UVLO
Solve for RUV2:
(149)
The closest standard resistor is 150 kΩtherefore VHYS is: (150)
Solve for RUV1:
(151)
The closest standard resistor is 21 kΩmaking VTURN-ON:
(152)
The chosen components from step 13 are:
(153)
14. OUTPUT OVLO
Solve for ROV2:
(154)
The closest standard resistor is 499 kΩtherefore VHYSO is: (155)
Solve for ROV1:
(156)
The closest standard resistor is 15.8 kΩmaking VTURN-OFF:
(157)
The chosen components from step 14 are:
(158)
44 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
F1CSS P
=
SS
C=nF975
( )
10.5 ms30 ms- =
( )
BASESSSUTSU tt --
-
k20 :=k20 :
ms5.10t BASESSSU =
CCk28C168 OCMPBYP x
+
x:
+
x:
=
BASESSSU
t-- ILED
VO
F40
F33.0k28F2.2168t BASESSSU Px
+
Px:
+
Px:
=
V21
A1
ms1.13tSU =
CCk36C168 OCMPBYP x
+
x:
+
x:
=
SU
tILED
VO
F40
F33.0k36F2.2168tSU Px
+
Px:
+
Px:
=V21
A1
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
15. SOFT-START
Solve for tSU:
(159)
If tSU is less than tTSU, solve for tSU-SS-BASE:
(160)
Solve for CSS:
(161)
The chosen component from step 15 is:
(162)
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 45
Product Folder Links: LM3424
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
DESIGN #1 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3424 Boost controller TI LM3424MH
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
2 CCMP, CNTC 0.33 µF X7R 10% 25V MURATA GRM21BR71E334KA01L
1 CFS 0.27 µF X7R 10% 25V MURATA GRM21BR71E274KA01L
4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K
4 CO10 µF X7R 10% 50V TDK C4532X7R1H106K
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 CREF, CSS 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L
1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF
1 L1 33 µH 20% 6.3A COILCRAFT MSS1278-333MLB
1 Q1 NMOS 100V 32A FAIRCHILD FDD3682
1 Q2 PNP 150V 600 mA FAIRCHILD MMBT5401
1 RBIAS 24.3 kΩ1% VISHAY CRCW080524K3FKEA
1 RCSH 12.4 kΩ1% VISHAY CRCW080512K4FKEA
1 RFS 10Ω1% VISHAY CRCW080510R0FKEA
1 RGAIN 6.81 kΩ1% VISHAY CRCW08056K81FKEA
2 RHSP, RHSN 1.0 kΩ1% VISHAY CRCW08051K00FKEA
1 RLIM 0.04Ω1% 1W VISHAY WSL2512R0400FEA
1 ROV1 15.8 kΩ1% VISHAY CRCW080515K8FKEA
1 ROV2 499 kΩ1% VISHAY CRCW0805499KFKEA
2 RREF1, RREF2 49.9 kΩ1% VISHAY CRCW080549K9FKEA
1 RSLP 16.5 kΩ1% VISHAY CRCW080516K5FKEA
1 RSNS 0.1Ω1% 1W VISHAY WSL2512R1000FEA
1 RT14.3 kΩ1% VISHAY CRCW080514K3FKEA
1 RUV1 21 kΩ1% VISHAY CRCW080521K0FKEA
1 RUV2 150 kΩ1% VISHAY CRCW0805150KFKEA
1 NTC Thermistor 100 kΩ5% TDK NTCG204H154J
46 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
SS
TGAIN
OVP
LM3424
nDIM
VIN
GND
TSENSE
TREF
DDRV
VS
COUT
DAP
GATE
EN
COMP
VIN
CSH
RT/SYNC
IS
HSN
SLOPE
VCC
HSP
D1
L1
CIN
RSLP
CBYP
RLIM
Q1
CCMP
RCSH
RT
CSS
ROV2
ROV1
RUV2
RUV1
RGAIN
NTC
RREF1
RREF2 RBIAS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RHSP
RHSN
CNTC
RSNS
RFS
CFS
COV
CREF
8V ± 28V
1A
ILED
RUVH
Q3 PWM
Q2
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
APPLICATIONS INFORMATION
The following designs are provided as reference circuits. For a specific design, the steps in the Design Guide
section should be performed. In all designs, an RC filter (0.1 µF, 10Ω) is recommended at VIN placed as close
as possible to the LM3424 device. This filter is not shown in the following designs.
DESIGN #2 - BOOST Application
Features
• Input: 8V to 28V
• Output: 9 LEDs at 1A
• 65°C - 100°C Thermal Foldback
• PWM Dimming up to 30kHz
• 700 kHz Switching Frequency
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 47
Product Folder Links: LM3424
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
DESIGN #2 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3424 Boost controller TI LM3424MH
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
1 CCMP 0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L
0 CFS DNP
4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K
4 COUT 10 µF X7R 10% 50V TDK C4532X7R1H106K
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
2 CNTC, CSS 0.27 µF X7R 10% 25V MURATA GRM21BR71E274KA01L
1 CREF 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L
1 D1 Schottky 60V 5A COMCHIP CDBC560-G
1 L1 33 µH 20% 6.3A COILCRAFT MSS1278-333MLB
2 Q1, Q2 NMOS 60V 8A VISHAY SI4436DY
1 Q3 NMOS 60V 115mA ON-SEMI 2N7002ET1G
1 RBIAS 19.6 kΩ1% VISHAY CRCW080519K6FKEA
2 RCSH, ROV1 12.4 kΩ1% VISHAY CRCW080512K4FKEA
1 RFS 0Ω1% VISHAY CRCW08050000Z0EA
1 RGAIN 6.49 kΩ1% VISHAY CRCW08056K49FKEA
2 RHSP, RHSN 1.0 kΩ1% VISHAY CRCW08051K00FKEA
1 RLIM 0.06Ω1% 1W VISHAY WSL2512R0600FEA
1 ROV2 499 kΩ1% VISHAY CRCW0805499KFKEA
2 RREF1, RREF2 49.9 kΩ1% VISHAY CRCW080549K9FKEA
1 RSNS 0.1Ω1% 1W VISHAY WSL2512R1000FEA
2 RSLP, RUV2 10.0 kΩ1% VISHAY CRCW080510K0FKEA
1 RT14.3 kΩ1% VISHAY CRCW080514K3FKEA
1 RUV1 1.82 kΩ1% VISHAY CRCW08051K82FKEA
1 RUVH 17.8 kΩ1% VISHAY CRCW080517K8FKEA
1 NTC Thermistor 100 kΩ5% TDK NTCG204H154J
48 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
SS
TGAIN
OVP
LM3424
nDIM
VIN
GND
TSENSE
TREF
DDRV
VS
COUT
DAP
GATE
EN
COMP
VIN
CSH
RT/SYNC
IS
HSN
SLOPE
VCC
HSP
D1
L1
CIN
RSLP
CBYP
RLIM
Q1
CCMP
RCSH
RT
CSS
ROV2
ROV1
RUV2
RUV1
RGAIN
RREF1
RREF2 RBIAS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RHSP
RHSN
CNTC
2A
ILED
RSNS
RFS
CFS
COV
CREF
Q5
VIN
10V ± 30V
RPOT
Q7
Q6 Q4
D2
VIN
DIM
RPU
RSER
DIM
Q3 PWM
RUVH
CB
CF
RF
Q2
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
DESIGN #3 - BUCK-BOOST Application
Features
• Input: 10V to 30V
• Output: 4 LEDs at 2A
• PWM Dimming up to 10kHz
• Analog Dimming
• 600 kHz Switching Frequency
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 49
Product Folder Links: LM3424
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
DESIGN #3 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3424 Boost controller TI LM3424MH
1 CB100 pF COG/NPO 5% 50V MURATA GRM2165C1H101JA01D
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
3 CCMP, CREF, CSS 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L
1 CF0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L
0 CFS DNP
4 CIN 6.8 µF X7R 10% 50V TDK C5750X7R1H685K
1 CNTC 0.47 µF X7R 10% 25V MURATA GRM21BR71E474KA01L
4 COUT 10 µF X7R 10% 50V TDK C4532X7R1H106K
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF
1 D2 Zener 10V 500mA ON-SEMI BZX84C10LT1G
1 L1 22 µH 20% 7.2A COILCRAFT MSS1278-223MLB
2 Q1, Q2 NMOS 60V 8A VISHAY SI4436DY
1 Q3 NMOS 60V 260mA ON-SEMI 2N7002ET1G
1 Q4 PNP 40V 200 mA FAIRCHILD MMBT5087
1 Q5 PNP 150V 600 mA FAIRCHILD MMBT5401
1 Q6 NPN 300V 600 mA FAIRCHILD MMBTA42
1 Q7 NPN 40V 200 mA FAIRCHILD MMBT6428
3 RBIAS, RREF1, RREF2 49.9 kΩ1% VISHAY CRCW080549K9FKEA
2 RCSH, RT12.4 kΩ1% VISHAY CRCW080512K4FKEA
1 RF10Ω1% VISHAY CRCW080510R0FKEA
1 RFS 0Ω1% VISHAY CRCW08050000Z0EA
2 RGAIN, RUV2 10.0 kΩ1% VISHAY CRCW080510K0FKEA
2 RHSP, RHSN 1.0 kΩ1% VISHAY CRCW08051K00FKEA
1 RLIM 0.04Ω1% 1W VISHAY WSL2512R0400FEA
1 ROV1 18.2 kΩ1% VISHAY CRCW080518K2FKEA
1 ROV2 499 kΩ1% VISHAY CRCW0805499KFKEA
1 RPOT 50 kΩpotentiometer BOURNS 3352P-1-503
1 RPU 4.99 kΩ1% VISHAY CRCW08054K99FKEA
1 RSER 499Ω1% VISHAY CRCW0805499RFKEA
1 RSLP 34.0 kΩ1% VISHAY CRCW080534K0FKEA
1 RSNS 0.05Ω1% 1W VISHAY WSL2512R0500FEA
1 RUV1 1.43 kΩ1% VISHAY CRCW08051K43FKEA
1 RUVH 17.4 kΩ1% VISHAY CRCW080517K4FKEA
50 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
SS
TGAIN
OVP
LM3424
nDIM
VIN
GND
TSENSE
TREF
DDRV
VS
COUT
DAP
GATE
EN
COMP
VIN
CSH
RT/SYNC
IS
HSN
SLOPE
VCC
HSP
D1
L1
CIN
RSLP
CBYP
RLIM
Q1
CCMP
RT
CSS
ROV2
ROV1
RUV2
RUV1
RGAIN
NTC
RREF1
RREF2 RBIAS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RHSP
RHSN
CNTC
RSNS
RFS
CFS
COV
CREF
18V ± 38V
700 mA
ILED
RBIAS2
RMAX
Q2
Q3
RADJ
Q4
RCSH VCC
VCC
VS
VS
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
DESIGN #4 - BOOST Application
Features
• Input: 18V to 38V
• Output: 12 LEDs at 700mA
• 85°C - 125°C Thermal Foldback
• Analog Dimming
• 700 kHz Switching Frequency
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 51
Product Folder Links: LM3424
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
DESIGN #4 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3424 Boost controller TI LM3424MH
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
3 CCMP, CREF, CSS 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L
1 CNTC 0.33 µF X7R 10% 25V MURATA GRM21BR71E334KA01L
1 CFS 0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L
4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K
4 COUT 10 µF X7R 10% 50V TDK C4532X7R1H106K
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 D1 Schottky 60V 5A COMCHIP CDBC560-G
1 L1 47 µH 20% 5.3A COILCRAFT MSS1278-473MLB
1 Q1 NMOS 60V 8A VISHAY SI4436DY
1 Q2 NPN 40V 200 mA FAIRCHILD MMBT3904
1 Q3, Q4 (dual pack) Dual PNP 40V 200mA FAIRCHILD FFB3906
1 RADJ 100 kΩpotentiometer BOURNS 3352P-1-104
1 RBIAS 9.76 kΩ1% VISHAY CRCW08059K76FKEA
1 RBIAS2 17.4 kΩ1% VISHAY CRCW080517K4FKEA
3 RCSH, ROV1, RUV1 12.4 kΩ1% VISHAY CRCW080512K4FKEA
1 RFS 10Ω1% VISHAY CRCW080510R0FKEA
1 RGAIN 6.55 kΩ1% VISHAY CRCW08056K55FKEA
3 RHSP, RHSN, RMAX 1.0 kΩ1% VISHAY CRCW08051K00FKEA
1 RLIM 0.06Ω1% 1W VISHAY WSL2512R0600FEA
1 ROV2 499 kΩ1% VISHAY CRCW0805499KFKEA
2 RREF1, RREF2 49.9 kΩ1% VISHAY CRCW080549K9FKEA
2 RSLP, RT10.0 kΩ1% VISHAY CRCW080510K0FKEA
1 RSNS 0.15Ω1% 1W VISHAY WSL2512R1500FEA
1 RUV2 100 kΩ1% VISHAY CRCW0805100KFKEA
1 NTC Thermistor 100 kΩ5% TDK NTCG204H154J
52 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
SS
TGAIN
OVP
LM3424
nDIM
VIN
GND
TSENSE
TREF
DDRV
VS
COUT
DAP
GATE
EN
COMP
VIN
CSH
RT/SYNC
IS
HSN
SLOPE
VCC
HSP
D1
L1
CIN
RSLP
CBYP
Q1
CCMP
RCSH
RT
CSS
ROV2
ROV1
RUV2
RUV1
RGAIN
RREF1
RREF2 RBIAS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RHSP
RHSN
CNTC
500 mA
ILED
RSNS
RFS
CFS
COV
CREF
Q5
VIN
10V ± 70V
Q7
Q6 Q4
D2
VIN
DIM
RPU
RSER
DIM
Q3 PWM
RUVH
CB
CF
RF
Q2
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
DESIGN #5 - BUCK-BOOST Application
Features
• Input: 10V to 70V
• Output: 6 LEDs at 500mA
• PWM Dimming up to 10 kHz
• 5 sec Fade-up
• MosFET RDS-ON Sensing
• 700 kHz Switching Frequency
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 53
Product Folder Links: LM3424
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
DESIGN #5 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3424 Boost controller TI LM3424MH
1 CB100 pF COG/NPO 5% 50V MURATA GRM2165C1H101JA01D
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
2 CCMP, CSS 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L
1 CREF 0.01 µF X7R 10% 25V MURATA GRM21BR71E103KA01L
1 CF0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L
0 CFS DNP
4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K
1 CNTC 10 µF X7R 10% 10V MURATA GRM21BR71A106KE51L
4 COUT 10 µF X7R 10% 50V TDK C4532X7R1H106K
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF
1 D2 Zener 10V 500mA ON-SEMI BZX84C10LT1G
1 L1 68 µH 20% 4.3A COILCRAFT MSS1278-683MLB
2 Q1, Q2 NMOS 100V 32A FAIRCHILD FDD3682
1 Q3 NMOS 60V 260mA ON-SEMI 2N7002ET1G
1 Q4 PNP 40V 200mA FAIRCHILD MMBT5087
1 Q5 PNP 150V 600 mA FAIRCHILD MMBT5401
1 Q6 NPN 300V 600mA FAIRCHILD MMBTA42
1 Q7 NPN 40V 200mA FAIRCHILD MMBT6428
3 RBIAS, RREF1, RREF2 49.9 kΩ1% VISHAY CRCW080549K9FKEA
1 RCSH 12.4 kΩ1% VISHAY CRCW080512K4FKEA
1 RFS 0Ω1% VISHAY CRCW08050000Z0EA
3 RGAIN, RT, RUV2 10.0 kΩ1% VISHAY CRCW080510K0FKEA
2 RHSP, RHSN 1.0 kΩ1% VISHAY CRCW08051K00FKEA
1 ROV1 15.8 kΩ1% VISHAY CRCW080515K8FKEA
1 ROV2 499 kΩ1% VISHAY CRCW0805499KFKEA
1 RPU 4.99 kΩ1% VISHAY CRCW08054K99FKEA
1 RSER 499Ω1% VISHAY CRCW0805499RFKEA
1 RSNS 0.2Ω1% 1W VISHAY WSL2512R2000FEA
1 RSLP 24.3 kΩ1% VISHAY CRCW080524K3FKEA
1 RUV1 1.43 kΩ1% VISHAY CRCW08051K43FKEA
1 RUVH 17.4 kΩ1% VISHAY CRCW080517K4FKEA
54 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
SS
TGAIN
OVP
LM3424
nDIM
VIN
GND
TSENSE
TREF
DDRV
VS
DAP
GATE
EN
COMP
VIN
CSH
RT/SYNC
IS
HSN
SLOPE
VCC
HSP
L1
CIN
RSLP
CBYP
RLIM
Q1
CCMP
RCSH
RT
CSS
ROV1
RUV2
RUV1
RGAIN
RREF1
RREF2 RBIAS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RHSP
RHSN
CNTC
COV
CREF
15V ± 50V
RPOT
Q3 PWM
RUVH
CO
D1
ROV2
1.25A
ILED
RSNS
RFS
CFS
Q2
D2
L1 Q4
RPU
CDIM
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
DESIGN #6 - BUCK Application
Features
• Input: 15V to 50V
• Output: 3 LEDS AT 1.25A
• PWM Dimming up to 50 kHz
• Analog Dimming
• 700 kHz Switching Frequency
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 55
Product Folder Links: LM3424
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
DESIGN #6 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3424 Boost controller TI LM3424MH
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
2 CCMP, CDIM 0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L
0 CFS DNP
1 CNTC 0.33 µF X7R 10% 25V MURATA GRM21BR71E334KA01L
4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K
0 COUT DNP
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 CREF, CSS 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L
1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF
1 D2 Zener 10V 500mA ON-SEMI BZX84C10LT1G
1 L1 22 µH 20% 7.3A COILCRAFT MSS1278-223MLB
1 Q1 NMOS 60V 8A VISHAY SI4436DY
1 Q2 PMOS 30V 6.2A VISHAY SI3483DV
1 Q3 NMOS 60V 115mA ON-SEMI 2N7002ET1G
1 Q4 PNP 150V 600 mA FAIRCHILD MMBT5401
3 RBIAS, RREF1, RREF2 49.9 kΩ1% VISHAY CRCW080549K9FKEA
1 RCSH 12.4 kΩ1% VISHAY CRCW080512K4FKEA
1 RFS 0Ω1% VISHAY CRCW08050000OZEA
1 RGAIN, RT10.0 kΩ1% VISHAY CRCW080510K0FKEA
2 RHSP, RHSN 1.0 kΩ1% VISHAY CRCW08051K00FKEA
1 RLIM 0.04Ω1% 1W VISHAY WSL2512R0400FEA
1 ROV1 21.5 kΩ1% VISHAY CRCW080521K5FKEA
1 ROV2 499 kΩ1% VISHAY CRCW0805499KFKEA
1 RPOT 50 kΩpotentiometer BOURNS 3352P-1-503
2 RPU, RUV2 100 kΩ1% VISHAY CRCW0805100KFKEA
1 RSLP 36.5 kΩ1% VISHAY CRCW080536K5FKEA
1 RSNS 0.08Ω1% 1W VISHAY WSL2512R0800FEA
1 RUV1 11.5 kΩ1% VISHAY CRCW080511K5FKEA
56 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
SS
TGAIN
OVP
LM3424
nDIM
VIN
GND
TSENSE
TREF
DDRV
VS
COUT
DAP
GATE
EN
COMP
VIN
CSH
RT/SYNC
IS
HSN
SLOPE
VCC
HSP
D1
L1
CIN
RSLP
CBYP
Q1
CCMP
RCSH
CSS
ROV2
ROV1
RUV2
RUV1
RGAIN
RREF2 RBIAS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RHSP
RHSN 2.5A
ILED
RSNS
RFS
CFS
COV
CREF
Q2
VIN
15V ± 60V
VIN
CAC
RT
CFLT
RFLT
SYNC
RREF1
NTC
CNTC
RLIM
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
DESIGN #7 - BUCK-BOOST Application
Features
• Input: 15V to 60V
• Output: 8 LEDs at 2.5A
• 80°C - 110°C Thermal Foldback
• 500 kHz Switching Frequency
• External Synchronization > 500 kHz
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 57
Product Folder Links: LM3424
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
DESIGN #7 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3424 Boost controller TI LM3424MH
2 CAC, CFLT 100 pF COG/NPO 5% 50V MURATA GRM2165C1H101JA01D
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
3 CCMP, CNTC, CSS 0.33 µF X7R 10% 25V MURATA GRM21BR71E334KA01L
1 CFS 0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L
4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K
4 COUT 10 µF X7R 10% 50V TDK C4532X7R1H106K
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 CREF 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L
1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF
1 L1 22 µH 20% 7.2A COILCRAFT MSS1278-223MLB
1 Q1 NMOS 100V 32A FAIRCHILD FDD3682
1 Q2 PNP 150V 600 mA FAIRCHILD MMBT5401
1 RBIAS 11.5 kΩ1% VISHAY CRCW080511K5FKEA
2 RCSH, ROV1 12.4 kΩ1% VISHAY CRCW080512K4FKEA
1 RFS 10Ω1% VISHAY CRCW080510R0FKEA
1 RFLT 150Ω1% VISHAY CRCW0805150RFKEA
1 RGAIN 5.49 kΩ1% VISHAY CRCW08055K49FKEA
2 RHSP, RHSN 1.0 kΩ1% VISHAY CRCW08051K00FKEA
2 RLIM, RSNS 0.04Ω1% 1W VISHAY WSL2512R0400FEA
1 ROV1 15.8 kΩ1% VISHAY CRCW080515K8FKEA
1 ROV2 499 kΩ1% VISHAY CRCW0805499KFKEA
2 RREF1, RREF2 49.9 kΩ1% VISHAY CRCW080549K9FKEA
1 RSLP 20.5 kΩ1% VISHAY CRCW080520K5FKEA
1 RT14.3 kΩ1% VISHAY CRCW080514K3FKEA
1 RUV1 13.7 kΩ1% VISHAY CRCW080513K7FKEA
1 RUV2 150 kΩ1% VISHAY CRCW0805150KFKEA
1 NTC Thermistor 100 kΩ5% TDK NTCG204H154J
58 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
SS
TGAIN
OVP
LM3424
nDIM
VIN
GND
TSENSE
TREF
DDRV
VS
COUT
DAP
GATE
EN
COMP
VIN
CSH
RT/SYNC
IS
HSN
SLOPE
VCC
HSP
D1
L1
CIN
RSLP
CBYP
RLIM
Q1
CCMP
RCSH
RT
CSS
ROV2
ROV1
RUV2
RUV1
RGAIN
NTC
RREF1
RREF2 RBIAS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RHSP
RHSN
CNTC
RSNS
RFS
CFS
COV
CREF
9V ± 36V
750 mA
ILED
RUVH
Q3 PWM
Q2
L2
CSEP
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
DESIGN #8 - SEPIC Application
Features
• Input: 9V to 36V
• Output: 5 LEDs at 750mA
• 60°C - 120°C Thermal Foldback
• PWM Dimming up to 30 kHz
• 500 kHz Switching Frequency
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 59
Product Folder Links: LM3424
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
www.ti.com
DESIGN #8 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3424 Boost controller TI LM3424MH
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
3 CCMP, CNTC, CSS 0.47 µF X7R 10% 25V MURATA GRM21BR71E474KA01L
0 CFS DNP
4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K
4 COUT 10 µF X7R 10% 50V TDK C4532X7R1H106K
1 CSEP 1.0 µF X7R 10% 100V TDK C4532X7R2A105K
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 CREF 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L
1 D1 Schottky 60V 5A COMCHIP CDBC560-G
2 L1, L2 68 µH 20% 4.3A COILCRAFT DO3340P-683
2 Q1, Q2 NMOS 60V 8A VISHAY SI4436DY
1 Q3 NMOS 60V 115 mA ON-SEMI 2N7002ET1G
1 RBIAS 23.7 kΩ1% VISHAY CRCW080523K7FKEA
1 RCSH 12.4 kΩ1% VISHAY CRCW080512K4FKEA
1 RFS 0Ω1% VISHAY CRCW08050000OZEA
1 RGAIN 9.31 kΩ1% VISHAY CRCW08059K31FKEA
2 RHSP, RHSN 750Ω1% VISHAY CRCW0805750RFKEA
1 RLIM 0.04Ω1% 1W VISHAY WSL2512R0400FEA
1 ROV1 15.8 kΩ1% VISHAY CRCW080515K8FKEA
1 ROV2 499 kΩ1% VISHAY CRCW0805499KFKEA
2 RREF1, RREF2 49.9 kΩ1% VISHAY CRCW080549K9FKEA
1 RSLP 20.0 kΩ1% VISHAY CRCW080520K0FKEA
1 RSNS 0.1Ω1% 1W VISHAY WSL2512R1000FEA
1 RT14.3 kΩ1% VISHAY CRCW080514K3FKEA
1 RUV1 1.62 kΩ1% VISHAY CRCW08051K62FKEA
1 RUV2 10.0 kΩ1% VISHAY CRCW080510K0FKEA
1 RUVH 16.9 kΩ1% VISHAY CRCW080516K9FKEA
1 NTC Thermistor 100 kΩ5% TDK NTCG204H154J
60 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM3424
PACKAGE OPTION ADDENDUM
www.ti.com 1-Jun-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM3424MH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3424
MH
LM3424MHX/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3424
MH
LM3424QMH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3424
QMH
LM3424QMHX/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3424
QMH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Jun-2014
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM3424, LM3424-Q1 :
•Catalog: LM3424
•Automotive: LM3424-Q1
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM3424MHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
LM3424QMHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Nov-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM3424MHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0
LM3424QMHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Nov-2014
Pack Materials-Page 2
MECHANICAL DATA
PWP0020A
www.ti.com
MXA20A (Rev C)
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