© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 1 1Publication Order Number:
NCP1240/D
NCP1240
Fixed Frequency Current
Mode Controller for Flyback
Converters
The NCP1240 is a new fixed−frequency current−mode controller
featuring the Dynamic Self−Supply. This function greatly simplifies
the design of the auxiliary supply and the VCC capacitor by activating
the internal startup current source to supply the controller during
start−up, transients, latch, stand−by etc. This device contains a special
HV detector which detect the application unplug from the AC input
line and triggers the X2 discharge current. This HV structure allows
the brown−out detection as well.
It features a timer−based fault detection that ensures the detection of
overload and an adjustable compensation to help keep the maximum
power independent of the input voltage.
Due to frequency foldback, the controller exhibits excellent
efficiency in light load condition while still achieving very low
standby power consumption. Internal frequency jittering, ramp
compensation, and a versatile latch input make this controller an
excellent candidate for the robust power supply designs.
A dedicated Off mode allows to reach the extremely low no load
input power consumption via “sleeping” whole device and thus
minimize the power consumption of the control circuitry.
Features
•Fixed−Frequency Current−Mode Operation (65 kHz and 100 kHz
frequency options)
•Frequency Foldback then Skip Mode for Maximized Performance in
Light Load and Standby Conditions
•Timer−Based Overload Protection with Latched (Options A and E) or
Auto−Recovery (Options B and F) Operation
•High−voltage Current Source with Brown−Out Detection and
Dynamic Self−Supply, Simplifying the Design of the VCC Circuitry
•Frequency Modulation for Softened EMI Signature
•Adjustable Overpower Protection Dependant on the Bulk Voltage
•Latch−off Input Combined with the Overpower Protection Sensing
Input
•VCC Operation up to 28 V, With Overvoltage Detection
•500/800 mA Source/Sink Drive Peak Current
Capability
•10 ms Soft−Start
•Internal Thermal Shutdown
•No−Load Standby Power < 30 mW
•X2 Capacitor in EMI Filter Discharging Feature
•These Devices are Pb−Free and Halogen Free/BFR Free
Typical Applications
•AC−DC Adapters for Notebooks, LCD, and Printers
•Offline Battery Chargers
•Consumer Electronic Power Supplies
•Auxiliary/Housekeeping Power Supplies
•Offline Adapters for Notebooks
SOIC−7
CASE 751U
MARKING
DIAGRAM
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40Xfff
ALYWX
G
1
8
40Xfff = Specific Device Code
X = A, B, E or F
fff = 065 or 100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
See detailed ordering and shipping information on page 44 o
f
this data sheet.
ORDERING INFORMATION
18
5
3
4
(Top View)
Latch
CS
HV
PIN CONNECTIONS
6
2
FB
GND DRV
VCC
NCP1240
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TYPICAL APPLICATION EXAMPLE
Figure 1. Flyback Converter Application Using the NCP1240
GND
GND
GND
GND NCP1240
GND
GND
PC817
GND
GND
GND
GND
NCP431
GND GND
GND
L2 L1
Q1
D2
D1
COUT
RSENSE
RCLAMP
CCLAMP
RLOAD
CBULK
D7
D6
D5
D4
LATCH
1
FB
2
CS
3
GND
4DRV 5
VCC 6
HV 8
IC1
TR
2
1
4
3
6
5
D3
C1
ROPP
D8
NTC
OK11
23
4
C2
R1R2
R4R3
IC2
C3
D9
D10
RHV
CX1
CX2
12
34
12
34
C4
+
+
W1
W2
W3
ac input
dc output
OPTIONS
Part Option Frequency OCP Fault
NCP1240
A65 kHz Latched
A100 kHz Latched
B65 kHz Autorecovery
B100 kHz Autorecovery
E65 kHz Latched
F65 kHz Autorecovery
PIN FUNCTION DESCRIPTION
Pin No Pin Name Function Pin Description
1 LATCH Latch−Off Input Pull the pin up or down to latch−off the controller. An internal current source
allows the direct connection of an NTC for over temperature detection.
2 FB Feedback + Shutdown pin An optocoupler collector to ground controls the output regulation. The part
goes to the low consumption Off mode if the FB input pin is pulled to GND.
3 CS Current Sense This Input senses the Primary Current for current−mode operation, and
offers an overpower compensation adjustment.
4 GND − The controller ground
5 DRV Drive output Drives external MOSFET
6 VCC VCC input This supply pin accepts up to 28 Vdc, with overvoltage detection. The pin is
connected to an external auxiliary voltage. It is not allowed to connect
another circuit to this pin to keep low input power consumption.
8 HV High−voltage pin Connects to the rectified AC line to perform the functions of Start−up
Current Source, Self−Supply, brown−out detection and X2 capacitor
discharge function and the HV sensing for the overpower protection
purposes. It is not allowed to connect this pin to DC voltage.
NCP1240
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SIMPLIFIED INTERNAL BLOCK SCHEMATIC
Figure 2. Simplified Internal Block Schematic
freq folback
jittering
Vskip
Skip_CMP
SkipB
Vramp_offset
1.4V
4uMho
Ramp_OTA
CSref
Division ratio 4
Internal resitance 40k
Soft Start timer
Reset
QSet
Qb
Clamp
FB
CS
DRV
GND
VCC
Rfb1
Rfb2Rfb3
FaultB
LatchB
PWM_CMP
Vfb(reg)
MAX_ton
Brown_OutB
PWM
V to I
Iopc = 0.5u*(Vhv−125)
Vfb(opc)
Von
Off_mode_CMP1
ICstart
FBbuffer
Vhv DC sample
2.2V
VCC
UVLO_CMP
VccOFF
9.3V
LATCH VccOVP
OTP
Votp
0.4V
Vovp
2.5V
OTP_CMP
OVP_CMP
Vclamp
1.2V
Rclamp
1k
HV
Brown_Out
VccOVP_CMP
VccOVP
26V
Intc
Vdd
Intc
SS_end
Set Q
Reset Qb
Latch
Brown_Out
RESET
OVP AC_Off
UVLO
VCC
5uA
Vcc_Int
IC stopB
Vhv DC sample
SG & X2 & Vcc
Vdd reg
Vdd
Vcc regulator
PowerOnReset_CMP
Vcc(reg)
VccRESET
10.8V5V
control
8 mA
current source
ICstartB
TSD
RESET
ON_CMP
STOP_CMP
VccONVccMIN
12V8.4V
VccON
VccMIN
GoToOffMode timer 500ms
Set Q
Reset Qb
0.8V
Voff
Off_mode_CMP2
FM input
OSC 65kHz
PFM input
Square output
Saw output
ton_max output
3.0V
Vdd
1uA
Fault timer
TSD
Latch management
Fault
Ilimit_CMP
Vilim
0.7V
LEB 120ns CSstop_CMP
VCSstop
1.05V
TSD
Latch
RESET
Ilimit
MAX_ton
Autorecovery timer
Brown_Out
Reset
QSet
Qb
IC stop
Transient timer up/down Fault
Itran_CMP
Vcs(tran)
0.5V
Itran
4 events timer
Reset
QSet
Qb
50 us
Filter
350 us
Filter
10 us
Filter Dual HV
Start−up
SoftStart_CMP
Enable
SS_end
NCP1240
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MAXIMUM RATINGS
Rating Symbol Value Unit
DRV
(pin 5) Maximum voltage on DRV pin
(Dc−Current self−limited if operated within the allowed range) (Note 1) –0.3 to 20
±1000 (peak) V
mA
VCC
(pin 6) VCCPower Supply voltage, VCC pin, continuous voltage
Power Supply voltage, VCC pin, continuous voltage (Note 1) –0.3 to 28
±30 (peak) V
mA
HV
(pin 8) Maximum voltage on HV pin
(Dc−Current self−limited if operated within the allowed range) –0.3 to 500
±20 V
mA
Vmax Maximum voltage on low power pins (except pin 5, pin 6 and pin 8)
(Dc−Current self−limited if operated within the allowed range) (Note 1) –0.3 to 10
±10 (peak) V
mA
RqJ−A Thermal Resistance SOIC−7
Junction-to-Air, low conductivity PCB (Note 2)
Junction-to-Air, medium conductivity PCB (Note 3)
Junction-to-Air, high conductivity PCB (Note 4)
162
147
115
°C/W
RqJ−C Thermal Resistance Junction−to−Case 73 °C/W
TJMAX Operating Junction Temperature −40 to +150 °C
TSTRGMAX Storage Temperature Range −60 to +150 °C
ESD Capability, HBM model (All pins except HV) per JEDEC Standard JESD22,
Method A1 14E > 2000 V
ESD Capability, Machine Model per JEDEC Standard JESD22, Method A115A > 200 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78.
2. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-1 conductivity test PCB. Test conditions were under natural convection or zero air flow.
3. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-2 conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-3 conductivity test PCB. Test conditions were under natural convection or zero air flow.
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,
VCC = 11 V unless otherwise noted)
Characteristics Test Condition Symbol Min Typ Max Unit
HIGH VOLTAGE CURRENT SOURCE
Minimum Voltage for Current Source
Operation VHV(min) − 30 40 V
Current Flowing Out of VCC Pin
(X2 discharge current value is equal to Istart2)VCC = 0 V
VCC = VCC(on) − 0.5 V Istart1
Istart2 0.2
50.5
80.8
11 mA
Off−state Leakage Current VHV = 500 V, VCC = 15 V Istart(off) 10 25 50 mA
Off−mode HV Supply Current VHV = 141 V,
VHV = 325 V,
VCC loaded by 4.7 mF cap
IHV(off) −
−45
50 60
70 mA
SUPPLY
HV Current Source Regulation Threshold VCC(reg) 811 − V
T urn−on Threshold Level, VCC Going Up
HV Current Source Stop Threshold VCC(on) 11.0 12.0 13.0 V
HV Current Source Restart Threshold VCC(min) 7.8 8.4 9.0 V
Turn−off Threshold (Note 5) VCC(off) 8.8 9.3 9.8 V
Overvoltage Threshold VCC(ovp) 25 26.5 28 V
5. VCC(off) < VCC(min) with the minimum gap 0.5 V.
6. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
7. Guaranteed by design.
8. CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,
VCC = 11 V unless otherwise noted)
Characteristics UnitMaxTypMinSymbolTest Condition
SUPPLY
Blanking Duration on VCC(off) and VCC(ovp)
Detection tVCC(blank) − 10 − ms
VCC Decreasing Level at Which the Internal
Logic Resets VCC(reset) 4.8 7.0 7.7 V
VCC Level for ISTART1 to ISTART2 Transition VCC(inhibit) 0.2 0.8 1.25 V
Internal Current Consumption (Note 6) DRV open, VFB = 3 V, 65 kHz
DRV open, VFB = 3 V, 100 kHz
Cdrv = 1 nF, VFB = 3 V, 65 kHz
Cdrv = 1 nF, VFB = 3 V, 100 kHz
Off mode (skip or before start−up)
Fault mode (fault or latch)
ICC1
ICC1
ICC2
ICC2
ICC3
ICC4
1.3
1.3
1.8
2.0
0.5
0.35
1.85
1.85
2.6
2.9
0.65
0.5
2.2
2.2
3.0
3.2
0.8
0.7
mA
BROWN−OUT
Brown−Out Thresholds VHV going up
VHV going down VHV(start)
VHV(stop) 102
94 111
103 120
112 V
Timer Duration for Line Cycle Drop−out tHV 35 50 75 ms
X2 DISCHARGE
Comparator Hysteresis Observed at HV Pin VHV(hyst) 1.5 3.5 5 V
HV Signal Sampling Period Tsample − 1.0 − ms
Timer Duration for No Line Detection tDET 43 64 86 ms
Discharge Timer Duration tDIS 43 64 86 ms
OSCILLATOR
Oscillator Frequency fOSC 58
87 65
100 72
109 kHz
Maximum On Time for TJ = 25°C to +125°C
Only fOSC = 65 kHz
fOSC = 100 kHz tONmax(65kHz)
tONmax(100kHz) 11.5
7.5 12.3
8.0 13.1
8.5 ms
Maximum On Time fOSC = 65 kHz
fOSC = 100 kHz tONmax(65kHz)
tONmax(100kHz) 11.3
7.4 12.3
8.0 13.1
8.5 ms
Maximum Duty Cycle (corresponding to
maximum on time at maximum switching
frequency)
fOSC = 65 kHz
fOSC = 100 kHz DMAX − 80 − %
Frequency Jittering Amplitude, in Percentage
of FOSC Ajitter ±3±5.5 ±8 %
Frequency Jittering Modulation Frequency Fjitter 85 125 165 Hz
FREQUENCY FOLDBACK
Feedback Voltage Threshold Below Which
Frequency Foldback Starts TJ = 25°C VFB(foldS) 2.35 2.5 2.6 V
Feedback Voltage Threshold Below Which
Frequency Foldback is Complete TJ = 25°C VFB(foldE) 1.4 1.5 1.6 V
Minimum Switching Frequency(NCP1240A/B)
(NCP1240E/F)
VFB = Vskip(in) + 0.1 fOSC(min) 23
21 27
27 32
32
kHz
5. VCC(off) < VCC(min) with the minimum gap 0.5 V.
6. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
7. Guaranteed by design.
8. CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
NCP1240
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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,
VCC = 11 V unless otherwise noted)
Characteristics UnitMaxTypMinSymbolTest Condition
OUTPUT DRIVER
Rise Time, 10% to 90% of VCC VCC = VCC(min) + 0.2 V,
CDRV = 1 nF trise − 40 70 ns
Fall Time, 90% to 10% of VCC VCC = VCC(min) + 0.2 V,
CDRV = 1 nF tfall − 40 70 ns
Current Capability VCC = VCC(min) + 0.2 V,
CDRV = 1 nF
DRV high, VDRV = 0 V
DRV low, VDRV = VCC IDRV(source)
IDRV(sink) −
−500
800 −
−
mA
Clamping Voltage (maximum gate voltage) VCC = VCCmax – 0.2 V, DRV high,
RDRV = 33 kW, Cload = 220 pF VDRV(clamp) 11 13.5 16 V
High−state Voltage Drop VCC = VCC(min) + 0.2 V,
RDRV = 33 kW, DRV high VDRV(drop) − − 1 V
CURRENT SENSE
Input Pull−up Current VCS = 0.7 V Ibias − 1 − mA
Maximum Internal Current Setpoint VFB > 3.5 V VILIM 0.66 0.70 0.74 V
Propagation Delay from VIlimit Detection to
DRV Off VCS = VILIM tdelay − 80 110 ns
Leading Edge Blanking Duration for VILIM tLEB 200 250 340 ns
Threshold for Fast Fault Protection Activation VCS(stop) 0.95 1.05 1.15 V
Leading Edge Blanking Duration for VCS(stop)
(Note 7) tBCS 90 120 150 ns
Soft−start Duration From 1st pulse to VCS = VILIM tSSTART 811 14 ms
INTERNAL SLOPE COMPENSATION
Slope of the Compensation Ramp Scomp(65kHz)
Scomp(100kHz) −
−−32.5
−50 −
−mV /
ms
FEEDBACK
Internal Pull−up Resistor TJ = 25°C RFB(up) 30 40 50 kW
VFB to Internal Current Setpoint Division
Ratio KFB − 4 − −
Internal Pull−up Voltage on the FB Pin
(Note 7) VFB(ref) 4.5 5 5.5 V
Feedback Voltage Below which the Peak
Current is Frozen TJ = 25°C VFB(off) − 0.8 − V
SKIP CYCLE MODE
Feedback Voltage Thresholds for Skip Mode VFB going down, TJ = 25°C
VFB going up, TJ = 25°CVskip(in)
Vskip(out) 1.1
1.2 1.2
1.3 1.3
1.4 V
REMOTE CONTROL ON FB PIN
The Voltage Above which the Part Enters the
On Mode VCC > VCC(off), VHV = 60 V VON − 2.2 − V
The Voltage Below which the Part Enters the
Off Mode VCC > VCC(off) VOFF 0.5 0.6 0.7 V
Minimum Hysteresis Between the VON and
VOFF VCC > VCC(off), VHV = 60 V VHYST 500 − − mV
Pull−up Current in Off Mode VCC > VCC(off) IOFF − 5 − mA
5. VCC(off) < VCC(min) with the minimum gap 0.5 V.
6. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
7. Guaranteed by design.
8. CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,
VCC = 11 V unless otherwise noted)
Characteristics UnitMaxTypMinSymbolTest Condition
REMOTE CONTROL ON FB PIN
Go To Off Mode Timer VCC > VCC(off) tGTOM 400 500 600 ms
OVERLOAD PROTECTION
Fault Timer Duration (NCP1240A/B)
(NCP1240E/F) tfault 44
9.1 64
14 84
23.2 ms
Autorecovery Mode Latch−off Time Duration tautorec 0.85 1.00 1.35 s
CS Threshold for Transient Peak Timer
Activation VCS(tran) 0.46 0.49 0.52 V
Transient Peak Power Timer Duration
(NCP1240A/B)
(NCP1240E/F)
VCS(peak) = VCS(tran) + 0.1 V from 1st
time VCS > VCS(tran) to DRV stop ttran 4.1
44 6.1
64 8.1
84 s
ms
OVERPOWER PROTECTION
VHV to IOPC Conversion Ratio KOPC − 0.54 − mA / V
Current Flowing out of CS Pin (Note 8) VHV = 125 V
VHV = 162 V
VHV = 325 V
VHV = 365 V
IOPC(125)
IOPC(162)
IOPC(325)
IOPC(365)
−
−
−
105
0
20
110
130
−
−
−
150
mA
FB Voltage Above which IOPC is Applied VHV = 365 V VFB(OPCF) − 2.6 − V
FB Voltage Below which is No IOPC Applied VHV = 365 V VFB(OPCE) − 2.1 − V
LATCH−OFF INPUT
High Threshold VLatch going up VOVP 2.35 2.5 2.65 V
Low Threshold VLatch going down VOTP − 0.4 − V
OTP Resistance Threshold (TJ = 25°C
)
(TJ = 80°C
)
(TJ = 110°C
)
External NTC resistance
is going down ROTP 6.6
−
−
7.7
8.5
9.5
8.6
−
−
kW
Current Source for Direct NTC Connection
During Sormal Operation
During Soft−start
VLatch = 0 V INTC
INTC(SSTART) 20
60 50
100 70
140
mA
Blanking Duration On High Latch Detection 65 kHz version
100 kHz version tLatch(OVP) 35
20 50
35 70
55 ms
Blanking Duration On Low Latch Detection tLatch(OTP) − 350 − ms
Clamping voltage ILatch = 0 mA
ILatch = 1 mA Vclamp0(Latch)
Vclamp1(Latch) 1.0
1.8 1.2
2.4 1.4
3.0 V
TEMPERATURE SHUTDOWN
Temperature shutdown TJ going up TTSD − 150 − °C
Temperature shutdown hysteresis TJ going down TTSD(HYS) − 30 − °C
5. VCC(off) < VCC(min) with the minimum gap 0.5 V.
6. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
7. Guaranteed by design.
8. CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NCP1240
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TYPICAL CHARACTERISTIC
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 3. Minimum Current Source Operation
VHV(min)
VHV(min) (V)
20
22
24
26
28
30
32
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 4. Off−State Leakage Current Istart(off)
Istart(off) (mA)
20
25
30
35
40
45
50
TEMPERATURE (°C)
Figure 5. Off−Mode HV Supply Current IHV(off)
IHV(off) (mA)
−50 −25 0 25 50 75 100 125
IHV(off) @ VHV = 325 V
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
TEMPERATURE (°C)
Figure 6. High Voltage Startup Current
Flowing Out of VCC Pin Istart2
−50 −25 0 25 50 75 100 125
Istart2 (mA)
120
TEMPERATURE (°C)
Figure 7. Brown−out Device Start Threshold
VHV(start)
VHV(start) (V)
−50 −25 0 25 50 75 100 125
120
TEMPERATURE (°C)
Figure 8. Brown−out Device Stop Threshold
VHV(stop)
−50 −25 0 25 50 75 100 125
VHV(stop) (V)
16
18
20
22
24
26
28
30
115
110
105
100
95
115
110
105
100
95
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TYPICAL CHARACTERISTIC
0.65
0.66
0.67
0.68
0.69
0.70
0.71
0.72
0.73
0.74
0.75
TEMPERATURE (°C)
Figure 9. Maximum Internal Current Setpoint
VILIM
VILIM (V)
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 10. Threshold for Transient Peak Power
Timer Activation VCS(tran)
VCS(tran) (V)
−50 −25 0 25 50 75 100 125
0.95
0.97
0.99
1.01
1.03
1.05
1.07
1.09
1.11
1.13
1.15
TEMPERATURE (°C)
Figure 11. Threshold for Immediate Fault
Protection Activation VCS(stop)
VCS(stop) (V)
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 12. Propagation Delay tdelay
tdelay (ns)
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 13. Leading Edge Blanking Duaration
tLEB
tLEB (ns)
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 14. Maximum Overpower
Compensating Current IOPC(365) Flowing Out
of CS Pin
IOPC(365) (mA)
−50 −25 0 25 50 75 100 125
0.46
0.47
0.48
0.49
0.50
0.51
0.52
30
40
50
60
70
80
90
250
260
270
280
290
300
310
320
110
112
114
116
118
120
122
124
126
128
130
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TYPICAL CHARACTERISTIC
TEMPERATURE (°C)
Figure 15. FB Pin Internal Pull−up Resistor
RFB(up)
RFB(up) (kW)
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 16. FB Pin Open Voltage VFB(ref)
VFB(ref) (V)
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 17. VFB to Internal Current Setpoint
Division Ratio KFB
KFB (−)
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 18. Offset Voltage VFB(off) between
FB Pin and Internal FB Divider
VFB(off) (V)
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 19. Latch Pin High Threshold VOVP
VOVP (V)
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 20. OTP Reistance Threshold ROTP at
Latch Pin
ROTP (kW)
−50 −25 0 25 50 75 100 125
30
32
34
36
38
40
42
44
46
48
50
4.60
4.70
4.80
4.90
5.00
5.10
5.20
3.50
3.60
3.70
3.80
3.90
4.00
4.10
4.20
4.30
4.40
4.50
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
2.35
2.40
2.45
2.50
2.55
2.60
2.65
6
7
8
9
10
11
12
NCP1240
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11
TYPICAL CHARACTERISTIC
TEMPERATURE (°C)
Figure 21. Current INTC Sourced from the
Latch Pin, Allowing Direct NTC Connection
INTC (mA)
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
INTC(SSTART) (mA)
−50 −25 0 25 50 75 100 125
Figure 22. Current INTC(SSTART) Sourced from
the Latch Pin, During Soft−Start
20
25
30
35
40
45
50
55
60
65
70
60
70
80
90
100
110
120
TEMPERATURE (°C)
Figure 23. Oscillator fOSC for the 65 kHz
Version (NCP1240A/B only)
fOSC (kHz)
−50 −25 0 25 50 75 100 125
Figure 24. Maximum ON Time tONmax for the
65 kHz Version (NCP1240A/B only)
fOSC (kHz)
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
90
91
92
93
94
95
96
97
98
99
100
7.5
7.6
7.7
7.8
7.9
8.0
8.1
8.2
8.3
8.4
8.5
TEMPERATURE (°C)
Figure 25. Maximum Duty Ratio DMAX
DMAX (%)
−50 −25 0 25 50 75 100 125
fOSC(min) (ms)
TEMPERATURE (°C)
Figure 26. Minimum Switching Frequency
fOSC(min)
−50 −25 0 25 50 75 100 125
72
73
74
75
76
77
78
79
80
81
82
22
23
24
25
26
27
28
29
30
NCP1240
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TYPICAL CHARACTERISTIC
TEMPERATURE (°C)
Figure 27. FB Pin Voltage Below Which
Frequency Foldback Starts VFB(foldS)
V
FB(foldS)
(V)
−50 −25 0 25 50 75 100 125
Figure 28. FB Pin Voltage Below Which
Frequency Foldback Complete VFB(foldE)
VFB(foldE) (V)
−50 −25 0 25 50 75 100 12
5
TEMPERATURE (°C)
Figure 29. FB Pin Skip−In Level Vskip(in)
V
skip(in)
(V)
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 30. FB Pin Skip−Out Level Vskip(out)
Vskip(on) (V)
−50 −25 0 25 50 75 100 12
5
Figure 31. FB Pin Level VFB(OPCF) Above
Which is the Overpower Compensation
Applied
TEMPERATURE (°C)
V
FB(OPCF)
(V)
−50 −25 0 25 50 75 100 12
5
Figure 32. FB Pin Level VFB(OPCE) Below
Which is No Overpower Compensation
Applied
VFB(OPCE) (V)
TEMPERATURE (°C)
−50 −25 0 25 50 75 100 125
2.20
2.30
2.40
2.50
2.60
2.70
2.80
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
1.50
1.60
1.70
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
NCP1240
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TYPICAL CHARACTERISTIC
Figure 33. VCC Turn−on Threshold Level, VCC
Going Up HV Current Source Stop Threshold
VCC(on)
VCC(on) (V)
TEMPERATURE (°C)
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
Figure 34. HV Current Source Restart
Threshold VCC(min)
VCC(min) (V)
TEMPERATURE (°C)
Figure 35. VCC Turn−off Threshold (UVLO)
VCC(off)
VCC(off) (V)
TEMPERATURE (°C)
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
Figure 36. VCC Decreasing Level at Which the
Internal Logic Resets VCC(reset)
VCC(reset) (V)
TEMPERATURE (°C)
Figure 37. Internal Current Consumption when
DRV Pin is Unloaded
ICC1 (mA)
TEMPERATURE (°C)
−50 −25 0 25 50 75 100 125
ICC2 (mA)
Figure 38. Internal Current Consumption when
DRV Pin is Loaded by 1 nF
TEMPERATURE (°C)
−50 −25 0 25 50 75 100 125
11.0
11.2
11.4
11.6
11.8
12.0
12.2
12.4
12.6
12.8
13.0
7.8
8.0
8.2
8.4
8.6
8.8
9.0
8.8
8.9
9.0
9.1
9.2
9.3
9.4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7.0
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.0
2.2
2.4
2.6
2.8
3.0
3.2
NCP1240
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TYPICAL CHARACTERISTIC
Figure 39. X2 Discharge Comparator
Hysteresis Observed at HV Pin VHV(hyst)
VHV(hyst) (V)
TEMPERATURE (°C)
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
Figure 40. HV Signal Sampling Period Tsample
TEMPERATURE (°C)
Tsample (ms)
−50 −25 0 25 50 75 100 125
Figure 41. Timer Duration for Line Cycle
Drop−out tHV
tHV (ms)
TEMPERATURE (°C) −50 −25 0 25 50 75 100 125
Figure 42. Fault Timer Duration tfault
(NCP1240A/B only)
tfault (V)
TEMPERATURE (°C)
−50 −25 0 25 50 75 100 125
Figure 43. Transient Peak Power Timer Timer
Duration ttran (NCP1240A/B only)
ttran (s)
TEMPERATURE (°C) −50 −25 0 25 50 75 100 125
Figure 44. Go To Off Mode Timer Duration
tGTOM
tGTOM (ms)
TEMPERATURE (°C)
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
0.90
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
35
40
45
50
55
60
65
70
75
50
55
60
65
70
75
80
4.00
4.50
5.00
5.50
6.00
6.50
7.00
7.50
8.00
400
420
440
460
480
500
520
540
560
580
600
NCP1240
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15
APPLICATION INFORMATION
Functional Description
The NCP1240 includes all necessary features to build a
safe and ef ficient power supply based on a fixed−frequency
flyback converter. The NCP1240 is a multimode controller
as illustrated in Figure 45. The mode of operation depends
upon line and load condition. Under all modes of operation,
the NCP1240 terminates the DRV signal based on the switch
current. Thus, the NCP1240 always operates in current
mode control so that the power MOSFET current is always
limited.
Under normal operating conditions, the FB pin commands
the operating mode of the NCP1240 at the voltage
thresholds shown in Figure 45. At normal rated operating
loads (from 100% to approximately 33% full rated power)
the NCP1240 controls the converter in fixed frequency
PWM mode. It can operate in the continuous conduction
mode (CCM) or discontinuous conduction mode (DCM)
depending upon the input voltage and loading conditions. If
the controller is used in CCM with a wide input voltage
range, the duty−ratio may increase up to 50%. The build−in
slope compensation prevents the appearance of
sub−harmonic oscillations in this operating area.
The converter operates in frequency foldback mode
(FFM) for loads that are between approximately 17% and
48% of full rated power.
Effectively, operation in FFM results in the application of
constant volt−seconds to the flyback transformer each
switching cycle. Voltage regulation in FFM is achieved by
varying the switching frequency in the range from 65 kHz
(or 100 kHz) to 27 kHz. For extremely light loads (below
approximately 6% full rated power), the converter is
controlled using bursts of 27 kHz pulses. This mode is called
as skip mode. The FFM, keeping constant peak current and
skip mode allows design of the power supplies with
increased efficiency under the light loading conditions.
Keep in mind that the aforementioned boundaries of
steady−state operation are approximate because they are
subject to converter design parameters.
VFB
3.6 V
2.2 V 2.5 V1.5 V
1.3 V
1.2 V0.8 V
FFM PWM at fOSC
Skip mode
0 V
Low consumption off mode
OFF
Figure 45. Mode Control with FB Pin Voltage
ON
There was implemented the low consumption off mode
allowing to reach extremely low no load input power. This
mode is controlled by the FB pin and allows the remote
control (or secondary side control) of the power supply
shut−down. Most of the device internal circuitry is unbiased
in the low consumption off mode. Only the FB pin control
circuitry and X2 cap dischar ging circuitry is operating in the
low consumption off mode. If the voltage at feedback pin
decreases below the 0.6 V the controller will enter the low
consumption o ff mode. The controller can start if the FB pin
voltage increases above the 2.2 V level.
See the detailed status diagrams for the versions fully
latched A and the autorecovery B on the following figures.
The basic status of the device after wake–up by the VCC is
the off mode and mode is used for the overheating protection
mode if the thermal shutdown protection is activated.
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Figure 46. Operating Status Diagram for the Fully Latched Versions A and E of the Device
Extra Low Consumption
Power On
Reset
Latch=0
Off Mode
Latch=X
Latch
Latch=1
Stop
Reset
Latch=0
BO+TSD
BO+TSD
Soft
Start Running
Skip
mode
Skip in Skip out
SSend
BO
BO
AC present
+
discharged
Efficient operating mode
Dynamic Self−Supply
(if not enoughgh auxiliary voltage is
present)
Regulated Self−Supply
VCC
fault
X2 cap
Discharge
Latch=0
No AC
VHV > VHV(NOAC)
VCC > VCCreset
VCC > VCCreset
(VFB < VOFF) * GTOMtimer*(VCC > VCCoff)
(VFB > VON)*Latch
(VFB > VON)*Latch
OVP+OTP+VCCovp+VCSstop
(VILIM +MaxDC)*tfault
VCC > VCCoff
(VCC > VCCon)*BO
(VCC < VCCoff
(VCC < VCCoff
NCP1240
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Figure 47. Operating Status Diagram for the Autorecovery Versions B and F of the Device
Extra Low Consumption
Power On
Reset
Latch=0
AutoRec=0
X2 cap
Discharge
Latch=0
AutoRec=0
Off Mode
Latch=X
AutoRec=X
Latch
Latch=1
Stop
Reset
Latch=0
AutoRec=0
Autorecovery
Latch
AutoRec=1
BO+TSD
BO+TSD
Soft
Start Running
Skip
mode
Skip in Skip out
SSend
BO
BO
BO
AC present
+
discharged
Efficient operating mode
Regulated Self−Supply Dynamic Self−Supply
(if not enough auxiliary voltage is
present)
V
CC
fault
No AC
(VFB < VOFF) * GTOMtimer*(VCC > VCCoff)
VHV > VHV(NOAC)
VCC < VCCreset
VCC > VCCreset
(VFB > VON)*Latch
(VFB > VON)*Latch*AutoRec
(VFB > VON)*AutoRec
OVP+OTP+VCCovp
BO+tautorec
VCSstop VCC < VCCoff
(VILIM + MaxDC)*tfault
(VCC > VCCon)*BO
VCC < VCCoff
VCC > VCCoff
NCP1240
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18
The information about the fault (permanent Latch or
Autorecovery) is kept during the low consumption off mode
due the safety reason. The reason is not to allow unlatch the
device by the remote control being in off mode.
Start−up of the Controller
At start−up, the current source turns on when the voltage
on the HV pin is higher than VHV(min), and turns off when
VCC reaches VCC(on), then turns on again when VCC reaches
VCC(min), until the input voltage is high enough to ensure a
proper start−up, i.e. when VHV reaches VHV(start). The
controller actually starts the next time VCC reaches VCC(on).
The controller then delivers pulses, starting with a soft−start
period tSSTART during which the peak current linearly
increases before the current−mode control takes over.
Even though the Dynamic Self−Supply is able to maintain
the VCC voltage between VCC(on) and VCC(min) by turning
the HV start−up current source on and of f, it can only be used
in light load condition, otherwise the power dissipation on
the die would be too much. As a result, an auxiliary voltage
source is needed to supply VCC during normal operation.
The Dynamic Self−Supply is useful to keep the controller
alive when no switching pulses are delivered, e.g. in
brown−out condition, or to prevent the controller from
stopping during load transients when the VCC might drop.
The NCP1240 accepts a supply voltage as high as 28 V, with
an overvoltage threshold VCC(ovp) that latches the controller
off.
Figure 48. VCC Start−up Timing Diagram
time
VHV
time
VCC
time
DRV
VHV(start)
VHV(min)
VCC(on)
VCC(min)
HV current
source = Istart1
HV current
source = Istart2
Waits next VCC(on)
before starting
VCC(inhibit)
NCP1240
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19
For safety reasons, the start−up current is lowered when
VCC is below VCC(inhibit), to reduce the power dissipation in
case the VCC pin is shorted to GND (in case of VCC capacitor
failure, or external pull−down on VCC to disable the
controller). There is only one condition for which the current
source doesn’t turn on when VCC reaches VCC(inhibit): the
voltage on HV pin is too low (below VHV(min)).
HV Sensing of Rectified AC Voltage
The NCP1240 features on its HV pin a true ac line
monitoring circuitry. It includes a minimum start−up
threshold and an autorecovery brown−out protection; both
of them independent of the ripple on the input voltage. It is
allowed only to work with an unfiltered, rectified ac input to
ensure the X2 capacitor dischar ge function as well, which is
described in following. The brown−out protection
thresholds are fixed, but they are designed to fit most of the
standard ac−dc conversion applications.
When the input voltage goes below VHV(stop), a
brown−out condition is detected, and the controller stops.
The HV current source maintains VCC at VCC(min) level until
the input voltage is back above VHV(start).
NCP1240
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time
HV stop
time
VCC
time
DRV
VCC(on)
VCC(min)
Waits next
VccON before
starting
time
VHV HV timer elapsed
VHV(start)
VHV(stop)
Brown−out
condition
resets the
Internal Latch
tHV
Brown−out
detected
Spike induced by
residual energy in
Figure 51. Ac Line Drop−out Timing Diagram with Parasitic Spike
When V HV crosses the VHV(start) threshold, the controller
can start immediately. When it crosses VHV(stop), it triggers
a timer of duration tHV, this ensures that the controller
doesn’t stop in case of line cycle drop−out. The device restart
after the ac line voltage drop-out is protected to the parasitic
restart initiated e.g. the spikes induced at HV pin
immediately after the device is stopped by the residual
energy in the EMI filter. The device restart is allowed only
after the 1st watch dog signal event. The basic principle is
shown at Figure 49 and detail of the device restart is shown
at Figure 52.
NCP1240
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24
X2 Cap Discharge Feature
The X2 capacitor discharging feature is offered by usage
of the NCP1240. This feature saves approximately 16 mW
− 25 mW input power depending on the EMI filter X2
capacitors volume and it saves the external components
count as well. The discharge feature is ensured via the
start−up current source with a dedicated control circuitry for
this function. The X2 capacitors are being discharged by
current defined as Istart2 when this discharge event is
detected.
There is used a dedicated structure called ac line unplug
detector inside the X2 capacitor discharge control circuitry.
See the Figure 53 for the block diagram for this structure and
Figures 54, 55, 56 and 57 for the timing diagrams. The basic
idea of ac line unplug detector lies in comparison of the
direct sample of the high voltage obtained via the high
voltage sensing structure with the delayed sample o f the high
voltage. The delayed signal is created by the sample & hold
structure.
The comparator used for the comparison of these signals
is without hysteresis inside. The resolution between the
slopes of the ac signal and dc signal is defined by the
sampling time TSAMPLE and additional internal offset NOS.
These parameters ensure the noise immunity as well. The
additional offset is added to the picture of the sampled HV
signal and its analog sum is stored in the C1 storage
capacitor. If the voltage level of the HV sensing structure
output crosses this level the comparator CMP output signal
resets the detection timer and no dc signal is detected. The
additional offset NOS can be measured as the VHV(hyst) on
the HV pin. If the comparator output produces pulses it
means that the slope of input signal is higher than set
resolution level and the slope is positive. If the comparator
output produces the low level it means that the slope of input
signal is lower than set resolution level or the slope is
negative. There is used the detection timer which is reset by
any edge of the comparator output. It means if no edge
comes before the timer elapses there is present only dc signal
or signal with the small ac ripple at the HV pin. This type of
the ac detector detects only the positive slope, which fulfils
the requirements for the ac line presence detection.
In case of the dc signal presence on the high voltage input,
the direct sample of the high voltage obtained via the high
voltage sensing structure and the delayed sample of the high
voltage are equivalent and the comparator produces the low
level signal during the presence of this signal. No edges are
present at the output of the comparator, that’s why the
detection timer is not reset and dc detect signal appears.
The minimum detectable slope by this ac detector is given
by the ration between the maximum hysteresis observed at
HV pin VHV(hyst),max and the sampling time:
Smin +
VHV(hyst),max
Tsample (eq. 1)
Than it can be derived the relationship between the
minimum detectable slope and the amplitude and frequency
of the sinusoidal input voltage:
Vmax +
VHV(hyst),max
2@p@f@Tsample +5
2@p@35 @1@10−3 (eq. 2)
+22.7 V
The minimum detectable AC RMS voltage is 16 V at
frequency 35 Hz, if the maximum hysteresis is 5 V and
sampling time is 1 ms.
The X2 capacitor discharge feature is available in any
controller operation mode to ensure this safety feature. The
detection timer is reused for the time limiting of the
discharge phase, to protect the device against overheating.
The discharging process is cyclic and continues until the ac
line is detected again or the voltage across the X2 capacitor
is lower than VHV(min). This feature ensures to discharge
quite big X2 capacitors used in the input line filter to the safe
level. It is important to note that it is not allowed to
connect HV pin to any dc voltage due this feature. e.g.
directly to bulk capacitor.
During the HV sensing or X2 cap dischar ging the VCC net
is kept above the VCC(off) voltage by the Self−Supply in any
mode of device operation to supply the control circuitry.
During the dischar ge sequence is not allowed to start−up the
device.
NCP1240
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28
Figure 57. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence When the Application is
Unplugged Under High Line Condition
The Low Consumption Off Mode
There was implemented the low consumption off mode
allowing to reach extremely low no load input power as
described i n previous chapters. If the voltage at feedback pin
decreases below the 0.6 V the controller enters the off mode.
The internal VCC is turned−off, the IC consumes extremely
low VCC current and only the voltage at external VCC
capacitor is maintained by the Self−Supply circuit. The
Self−Supply circuit keeps the VCC voltage at the VCC(reg)
level. The supply for the FB pin watch dog circuitry and FB
pin bias is provided via the low consumption current sources
from the external VCC capacitor. The controller can only
start, if the FB pin voltage increases above the 2.2 V level.
See Figure 58 for timing diagrams.
Only the X2 cap discharge and Self−Supply features is
enabled in the low consumption off mode. The X2 cap
discharging feature is enable due the safety reasons and the
Self−Supply is enabled to keep the VCC supply, but only
very low VCC consumption appears in this mode. Any other
features are disabled in this mode.
The information about the latch status of the device is kept
in the low consumption off mode and this mode is used for
the TSD protection as well. The protection timer
GoToOffMode tGTOM is used to protect the application
against the false activation of the low consumption off mode
by the fast drop outs of the FB pin voltage below the 0.6 V
level. E.g. in case when is present high FB pin voltage ripple
during the skip mode.
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Figure 58. Start−up, Shutdown and AC Line Unplug Time Diagram
Oscillator with Maximum On Time and Frequency
Jittering
The NCP1240 includes an oscillator that sets the
switching frequency 65 kHz or 100 kHz depending on the
version. The maximum on time is 12.3 ms (for 65 kHz
version) or 8 ms (for 100 kHz version) with an accuracy of
±7%. The maximum on time corresponds to maximum duty
cycle of the DRV pin is 80% at full switching frequency. In
order to improve the EMI signature, the switching frequency
jitters ±6 % around its nominal value, with a triangle−wave
shape and at a frequency of 125 Hz. This frequency jittering
is active even when the frequency is decreased to improve
the efficiency in light load condition. Figure 59. Frequency Modulation of the Maximum
Switching Frequency
NCP1240
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Low Load Operation Modes: Frequency Foldback
Mode (FFM) and Skip Mode
In order to improve the ef ficiency in light load conditions,
the frequency of the internal oscillator is linearly reduced
from its nominal value down to fOSC(min). This frequency
foldback starts when the voltage on FB pin goes below
VFB(foldS), and is complete when VFB reaches VFB(foldE).
The maximum on−time duration control is kept during the
frequency foldback mode to provide the natural transformer
core anti−saturation protection. The frequency jittering is
still active while the oscillator frequency decreases as well.
Figure 60. Frequency Foldback Mode Characteristic
When the FB voltage reaches Vskip(in) while decreasing,
skip mode is activated: the driver stops, and the internal
consumption of the controller is decreased. While VFB is
below Vskip(out), the controller remains in this state; but as
soon as VFB crosses the skip out threshold, the DRV pin
starts to pulse again.
Figure 61. Skip Mode Timing Diagram
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Figure 62. Technique Preventing Short Pulses in Skip Mode
Clamped Driver
The supply voltage for the NCP1240 can be as high as
28 V, but most of the MOSFETs that will be connected to the
DRV pin cannot accept more than 20 V on their gate. The
driver pin is therefore clamped safely below 16 V. This
driver has a typical capability of 500 mA for source current
and 800 mA for sink current.
Current−Mode Control With Slope Compensation and
Soft−Start
NCP1240 i s a current−mode controller, which means that
the FB voltage sets the peak current flowing in the
inductance and the MOSFET. This is done through a PWM
comparator: the current is sensed across a resistor and the
resulting voltage is applied to the CS pin. It is applied to one
input of the PWM comparator through a 250 ns LEB block.
On the other input the FB voltage divided by 5 sets the
threshold: when the voltage ramp reaches this threshold, the
output driver is turned off. The maximum value for the
current sense is 0.7 V, and it is set by a dedicated comparator.
Each time the controller is starting, i.e. the controller was
off and starts – or restarts – when VCC reaches VCC(on), a
soft−start is applied: the current sense setpoint is increased
by 15 discrete steps from 0 (the minimum level can be
higher than 0 because of the LEB and propagation delay)
until it reaches VILIM (after a duration of tSSTART), or until
the FB loop imposes a setpoint lower than the one imposed
by the soft−start (the two comparators outputs are OR’ed).
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Figure 63. Soft−Start Feature
Under some conditions, like a winding short−circuit for
instance, not all the energy stored during the on time is
transferred to the output during the off time, even if the on
time duration is at its minimum (imposed by the propagation
delay of the detector added to the LEB duration). As a result,
the current sense voltage keeps on increasing above VILIM,
because the controller is blind during the LEB blanking
time. Dangerously high current can grow in the system if
nothing is done to stop the controller. That’s what the
additional comparator, that senses when the current sense
voltage on CS pin reaches VCS(stop) ( = 1.5 x VILIM ), does:
the controller enters the protection mode as soon as this
comparator toggles four times consecutively.
In order to allow the NCP1240 to operate in CCM with a
duty cycle above 50%, the fixed slope compensation is
internally applied to the current−mode control. The slope
appearing on the internal voltage setpoint for the PWM
comparator is −32.5 mV/ms typical for the 65 kHz version,
and −50 mV/ms for the 100 kHz version. The slope
compensation can be observable as a value of the peak
current at CS pin.
The internal slope compensation circuitry uses a sawtooth
signal synchronized with the internal oscillator is subtracted
from the FB voltage divided by KFB.
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Figure 64. Slope Compensation Block Diagram
Figure 65. Slope Compensation Timing Diagram
Internal Overpower Protection
The power delivered by a flyback power supply is
proportional to the square of the peak current in
discontinuous conduction mode:
POUT +1
2@h@LP@FSW @IP2(eq. 3)
Unfortunately, due to the inherent propagation delay of
the logic, the actual peak current is higher at high input
voltage than at low input voltage, leading to a significant
difference in the maximum output power delivered by the
power supply.
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Figure 66. Needs for Line Compensation For True Overpower Protection
To compensate this and have an accurate overpower
protection, an offset proportional to the input voltage is
added on the CS signal by turning on an internal current
source: by adding an external resistor in series between the
sense resistor and the CS pin, a voltage offset is created
across it by the current. The compensation can be adjusted
by changing the value of the resistor.
But this offset is unwanted to appear when the current
sense signal is small, i.e. in light load conditions, where it
would be in the same order of magnitude. Therefore the
compensation current is only added when the FB voltage is
higher than VFB(OPCE). However, because the HV pin is
being connected to ac voltage, there is needed an additional
circuitry to read or at least closely estimate the actual voltage
on the bulk capacitor.
Figure 67. Overpower Protection Current Relation to Feedback Voltage
NCP1240
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Figure 68. Overpower Protection Current Relation to Peak of Rectified Input Line AC voltage
Figure 69. Block Schematic of Overpower Protection Circuit
Division ratio 4
Internal resitance 40k
FB
CS
Rfb1
Rfb2Rfb3
PWM_CMP
LEB 250ns
Vfb(reg)
PWM
I generator
Ictrl
Vfb(opcf)
FBbuffer
A/D 3 bit
Converter
Peak detector
+3 bit
Register
HV
CMP
Lo frq OSC
Out sq
Detection timer
reset
R1
DC detect
Sample & Hold
R2
Q1
C1
Nos
OPC control
Positive slope
A 3 bit A/D converter with the peak detector senses the ac
input, and its output is periodically sampled and reset, in
order to follow closely the input voltage variations. The
sample and reset events are given by the output from the ac
line unplug detector. The sensed HV pin voltage peak value
is validated when no HV edges from comparator are present
after last falling edge during two sample clocks. See
Figure 70 for details.
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Overcurrent Protection with Fault timer
The overload protection depends only on the current
sensing signal, making it able to work with any transformer,
even with very poor coupling or high leakage inductance.
When an overcurrent event occurs on the output of the
power supply, the FB loop asks for more power than the
controller can deliver, and the CS setpoint reaches VILIM.
When this event occurs, an internal tfault timer is started:
once the timer times out, DRV pulses are stopped and the
controller is either latched of f (latched protection, options A
and E) or this latch is released by the autorecovery mode
(options B and F), the controller tries to restart after tautorec.
Other possibilities of the latch release are the brown−out
condition o r the VCC power on reset. The timer is reset when
the CS setpoint goes back below VILIM before the timer
elapses. The fault timer is also started if the driver signal is
reset b y the maximum on time. The controller also enters the
same protection mode if the voltage on the CS pin reaches
1.5 times the maximum internal setpoint VCS(stop) (allows to
detect winding short−circuits) or there appears low VCC
supply. See Figures 71 and 72 for the timing diagram.
In autorecovery mode if the fault has gone, the supply
resumes operation; if not, the system starts a new burst cycle.
NCP1240
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time
VHVSAMPLE
time
Comparator
Output
TSAMPLE
2nd sample clock
pulse after last
HV edge initiates
the watch dog
signal
VHV(hyst)
time
Sample clock
time
Watch dog
signal
1st HV edge
resets the watch
dog and starts
the peak
detection of HV
pin signal
Sample
Sample
Reset
2nd sample clock
pulse after last
HV edge initiates
the watch dog
signal
time
Peak detector
time
IOPC
Figure 70. Overpower Compensation Timing Diagram
Reset
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38
PROTECTION MODES AND THE LATCH MODE RELEASES
Event Timer Protection Next Device Status Release to Normal Operation Mode
Overcurrent
VILIM > 0.7 V Fault timer Latch Autorecovery – B and F versions
Brown−out
VCC < VCC(reset)
Peak power
VILIM > 0.5 V Transient timer Latch Autorecovery – B and F versions
Brown−out
VCC < VCC(reset)
Maximum on time Fault timer Latch Autorecovery – B and F versions
Brown−out
VCC < VCC(reset)
Winding short
Vsense > VCS(stop) 4consecutive pulses Latch Autorecovery – B and F versions
Brown−out
VCC < VCC(reset)
Low supply
VCC < VCC(off) 10 ms timer Latch Autorecovery – B and F versions
Brown−out
VCC < VCC(reset)
External OTP, OVP 55 ms (35 ms at 100 kHz) Latch Brown−out
VCC < VCC(reset)
High supply
VCC > VCC(ovp) 10 ms timer Latch Brown−out
VCC < VCC(reset)
Brown−out
VHV < VHV(stop) HV timer Device stops (VHV > VHV(start)) & (VCC > VCC(on))
Internal TSD 10 ms timer Device stops, HV start−up
current source stops (VHV > VHV(start)) & (VCC > VCC(on)) & TSDb
Off mode
VFB < VOFF 150 ms timer (NCP1240A/B)
500 ms timer (NCP1240E/F) Device stops and internal
VCC is turned off (VHV > VHV(start)) & (VCC > VCC(on)) &
(VFB > VON)
NCP1240
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Figure 72. Timer−Based Protection Mode with Autorecovery Release from Latch−off (Options B/F)
VCC(on)
VCC(min)
Duel−Level Overcurrent Protection
For some applications (e.g. limited power supplies), it is
necessary that the controller maintains regulation while it
has detected a first level of overload. This is to authorize a
transient peak power higher than the maximum continuous
output power. This is implemented by adding another
comparator whose threshold is VCS(tran), a CS voltage level
lower than VILIM, which starts the counting of another timer ,
with a duration ttran longer than tfault (6 s is the typical value).
If the timer reaches its maximum duration, the controller
enters protection mode which is latched or autorecovery
released depending on the option.
NCP1240
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Latch−Off Input
Figure 75. Latch Detection Schematic
The Latch pin is dedicated to the latch−off function: it
includes two levels of detection that define a working
window, between a high latch and a low latch: within these
two thresholds, the controller is allowed to run, but as soon
as either the low or the high threshold is crossed, the
controller is latched off. The lower threshold is intended to
be used with an NTC thermistor, thanks to an internal current
source INTC.
An active clamp prevents the voltage from reaching the
high threshold if it is only pulled up by the INTC current. To
reach the high threshold, the pull−up current has to be higher
than the pull−down capability of the clamp (typically
1.5 mA at VOVP).
To avoid any false triggering, spikes shorter than 50 ms
(for the high latch and 65 kHz version) or 350 ms (for the low
latch) are blanked and only longer signals can actually latch
the controller.
Reset occurs when a brown−out condition is detected or
the VCC is cycled down to a reset voltage, which in a real
application can only happen if the power supply is
unplugged from the ac line.
Upon startup, the internal references take some time
before being at their nominal values; so one of the
comparators could toggle even if it should not. Therefore the
internal logic does not take the latch signal into account
before the controller is ready to start: once VCC reaches
VCC(on), the latch pin High latch state is taken into account
and the DRV switching starts only if it is allowed; whereas
the Low latch (typically sensing an over temperature) is
taken into account only after the soft−start is finished. In
addition, the NTC current is doubled to INTC(SSTART) during
the soft−start period, to speed up the charging of the Latch
pin capacitor. The maximum value of Latch pin capacitor is
given by the following formula (The standard start−up
condition is considered and the NTC current is neglected):
CLATCH max +
tSSTART min @INTC(SSTART) min
Vclamp0 min +8.0 @10−3 @130 @10−6
1.0 F+1.04 mF(eq. 4)
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Figure 76. Latch Timing Diagram
VCC(on)
VCC(min)
Temperature Shutdown
The NCP1240 includes a temperature shutdown
protection with a trip point typically at 150°C and the typical
hysteresis of 30°C. When the temperature rises above the
high threshold, the controller stops switching
instantaneously, and goes to the off mode with extremely
low power consumption. There is kept the VCC supply to
keep the TSD information. When the temperature falls
below t h e l o w t h r e shold, the start−up of the device is enabled
again, and a regular start−up sequence takes place. See the
status diagrams at the Figures 46 and 47.
ORDERING INFORMATION
Ordering Part No. Overload Protection Switching Frequency Package Shipping†
NCP1240AD065R2G Latched 65 kHz SOIC−7
(Pb−Free) 2500 / Tape & Reel
NCP1240BD065R2G Autorecovery
NCP1240ED065R2G Latched 65 kHz SOIC−7
(Pb−Free) 2500 / Tape & Reel
NCP1240FD065R2G Autorecovery
NCP1240AD100R2G Latched 100 kHz SOIC−7
(Pb−Free) 2500 / Tape & Reel
NCP1240BD100R2G Autorecovery
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP1240
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45
PACKAGE DIMENSIONS
SOIC−7
CASE 751U
ISSUE E
SEATING
PLANE
14
58
R
J
X 45_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
S
D
H
C
DIM
AMIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−A−
−B−
G
M
B
M
0.25 (0.010)
−T−
B
M
0.25 (0.010) TSAS
M
7 PL
____
1.52
0.060
7.0
0.275
0.6
0.024 1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent− Marking.pdf. S CILLC r eserves the right t o make changes without further n otice to any product s herein. S CILLC makes no warrant y, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all l iabilit y, including without limitation special, consequential or i ncident al d amages. “Typical” parameters which may be p rovided i n SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application b y c ust omer’s technical e xperts. SCILLC does not c onvey a ny license under its p atent rights n or the rights of o thers. SCILLC products are n ot d esigned, i ntended,
or authorized for use as c omponent s i n s yst ems i nt ended f or s urgic al i m plant i nt o the body, or other applications intended t o s upport o r s ust ain life, or for any other a pplicat ion in w hich
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC an d it s officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and r easonable a ttorney f ees a rising o ut of, directly or i ndirectly, a ny c laim o f p ersonal i njury o r d eat h a ssociat ed w ith s uch u nintended o r u naut horized u se, e ven if such c laim
alleges that SCILLC was negligent regarding the d esign or manufacture of the p art. S CILLC i s a n E qual O pportunity/Af firmative Act ion Employer. T his literature is s ubject t o all applicable
copyright laws and is not for resale in any manner.
P
UBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
NCP1240/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loc
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