TJA1041AT/VM,518-CUT TAPE - NXP SEMICONDUCTORS

1. General description

The TJA1041A provides an advanced interface between the protocol controller and the

physical bus in a Controller Area Network (CAN) node. The TJA1041A is primarily

intended for automotive high-speed CAN applications (up to 1 Mbit/s). The transceiver

provides differential transmit capability to the bus and differential receive capability to the

CAN controller. The TJA1041A is fully compatible to the ISO 11898 standard, and offers

excellent ElectroMagnetic Compatibility (EMC) performance, very low power

consumption, and passive behavior when supply voltage is off. The advanced features

include:

•Low-power management, supporting local and remote wake-up with wake-up source

recognition and the capability to control the power supply in the rest of the node

•Several protection and diagnosis functions including short circuits of the bus lines and

ﬁrst battery connection

•Automatic adaptation of the I/O-levels, in line with the supply voltage of the controller

2. Features

2.1 Optimized for in-vehicle high-speed communication

nFully compatible with the ISO 11898 standard

nCommunication speed up to 1 Mbit/s

nVery low ElectroMagnetic Emission (EME)

nDifferential receiver with wide common-mode range, offering high

ElectroMagnetic Immunity (EMI)

nPassive behavior when supply voltage is off

nAutomatic I/O-level adaptation to the host controller supply voltage

nRecessive bus DC voltage stabilization for further improvement of EME behavior

nListen-only mode for node diagnosis and failure containment

nAllows implementation of large networks (more than 110 nodes)

2.2 Low-power management

nVery low-current in Standby and Sleep mode, with local and remote wake-up

nCapability to power down the entire node, still allowing local and remote wake-up

nWake-up source recognition

2.3 Protection and diagnosis (detection and signalling)

nTXD dominant clamping handler with diagnosis

TJA1041A

High-speed CAN transceiver

Rev. 04 — 29 July 2008 Product data sheet

Product data sheet Rev. 04 — 29 July 2008 2 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

nRXD recessive clamping handler with diagnosis

nTXD-to-RXD short circuit handler with diagnosis

nOvertemperature protection with diagnosis

nUndervoltage detection on pins VCC, VI/O and VBAT

nAutomotive environment transient protected bus pins and pin VBAT

nShort circuit proof bus pins and pin SPLIT (to battery and to ground)

nBus line short circuit diagnosis

nBus dominant clamping diagnosis

nCold start diagnosis (ﬁrst battery connection)

3. Quick reference data

[1] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor (6 kV level with pin GND

connected to ground).

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

VCC DC voltage on

pin VCC

operating range 4.75 - 5.25 V

VI/O DC voltage on

pin VI/O

operating range 2.8 - 5.25 V

IBAT VBAT input current normal or pwon/listen-only mode 15 30 40 µA

standby mode;

VCC > 4.75 V; VI/O = 2.8 V;

VINH =V

WAKE =V

BAT =12V

10 20 30 µA

sleep mode;

VINH =V

CC =V

I/O =0V;

VWAKE =V

BAT =12V

10 20 30 µA

VCANH DC voltage on pin

CANH 0 V < VCC < 5.25 V; no time limit −27 - +40 V

VCANL DC voltage on pin

CANL 0 V < VCC < 5.25 V; no time limit −27 - +40 V

VSPLIT DC voltage on pin

SPLIT 0 V < VCC < 5.25 V; no time limit −27 - +40 V

Vesd electrostatic

discharge voltage Human Body Model (HBM) [1]

pins CANH, CANL and SPLIT −6 - +6 kV

pins TXD, RXD, VI/O and STB −3 - +3 kV

all other pins −4 - +4 kV

tPD(TXD-RXD) propagation delay

TXD to RXD VSTB = 0 V 40 - 255 ns

Tvj virtual junction

temperature −40 - +150 °C

Product data sheet Rev. 04 — 29 July 2008 3 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

4. Ordering information

5. Block diagram

Table 2. Ordering information

Type number Package

Name Description Version

TJA1041AT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

TJA1041AU - bare die; 1920 ×3190 ×380 µm-

Fig 1. Block diagram

TJA1041A

WAKE

TXD

310

STB

ERR

VI/O

RXD

mnb115

WAKE

COMPARATOR

LEVEL

ADAPTOR

TIME-OUT

VI/O

GND

VCC VBAT

VBAT

VCC

VBAT

VCC

RXD

RECESSIVE

DETECTION

TEMPERATURE

PROTECTION

DRIVER

SPLIT SPLIT

CANL

CANH

INH

NORMAL

RECEIVER

LOW POWER

RECEIVER

MODE

CONTROL

FAILURE

DETECTOR

WAKE-UP

DETECTOR

VI/O

Product data sheet Rev. 04 — 29 July 2008 4 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

The primary function of a CAN transceiver is to provide the CAN physical layer as

described in the ISO 11898 standard. In the TJA1041A this primary function is

complemented with a number of operating modes, fail-safe features and diagnosis

features, which offer enhanced system reliability and advanced power management

functionality.

Fig 2. Pin conﬁguration

TJA1041A

TXD STB

GND CANH

VCC CANL

RXD SPLIT

VI/O VBAT

EN WAKE

INH ERR

001aag910

7 8

Table 3. Pin description

Symbol Pin Description

TXD 1 transmit data input

GND 2 ground

VCC 3 transceiver supply voltage input

RXD 4 receive data output; reads out data from the bus lines

VI/O 5 I/O-level adapter voltage input

EN 6 enable control input

INH 7 inhibit output for switching external voltage regulators

ERR 8 error and power-on indication output (active LOW)

WAKE 9 local wake-up input

VBAT 10 battery voltage input

SPLIT 11 common-mode stabilization output

CANL 12 LOW-level CAN bus line

CANH 13 HIGH-level CAN bus line

STB 14 standby control input (active LOW)

Product data sheet Rev. 04 — 29 July 2008 5 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

7.1 Operating modes

The TJA1041A can be operated in ﬁve modes, each with speciﬁc features. Control

pins STB and EN select the operating mode. Changing between modes also gives access

to a number of diagnostics ﬂags, available via pin ERR. The following sections describe

the ﬁve operating modes. Table 4 shows the conditions for selecting these modes.

Figure 3 illustrates the mode transitions when VCC, VI/O and VBAT are present.

[1] Setting the pwon ﬂag or the wake-up ﬂag will clear the UVNOM ﬂag.

[2] The transceiver directly enters Sleep mode and pin INH is set ﬂoating when the UVNOM ﬂag is set (so after

the undervoltage detection time on either VCC or VI/O has elapsed before that voltage level has recovered).

[3] When Go-to-sleep command mode is selected for longer than the minimum hold time of the go-to-sleep

command, the transceiver will enter Sleep mode and pin INH is set ﬂoating.

[4] On entering Normal mode the pwon ﬂag and the wake-up ﬂag will be cleared.

Table 4. Operating mode selection

Control pins Internal ﬂags Operating mode Pin INH

STB EN UVNOM UVBAT pwon;

wake-up

X X set X X[1] Sleep mode[2] ﬂoating

cleared set one or both set Standby mode H

both cleared no change from Sleep mode ﬂoating

Standby mode from any

other mode H

L L cleared cleared one or both set Standby mode H

both cleared no change from Sleep mode ﬂoating

Standby mode from any

other mode H

L H cleared cleared one or both set Standby mode H

both cleared no change from Sleep mode ﬂoating

Go-to-sleep command mode

from any other mode[3] H[3]

H L cleared cleared X Pwon/Listen-only mode H

H H cleared cleared X Normal mode[4] H

Product data sheet Rev. 04 — 29 July 2008 6 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

7.1.1 Normal mode

Normal mode is the mode for normal bidirectional CAN communication. The receiver will

convert the differential analog bus signal on pins CANH and CANL into digital data,

available for output to pin RXD. The transmitter will convert digital data on pin TXD into a

differential analog signal, available for output to the bus pins. The bus pins are biased at

0.5VCC (via Ri(cm)). Pin INH is active, so voltage regulators controlled by pin INH

(see Figure 4) will be active too.

7.1.2 Pwon/Listen-only mode

In Pwon/Listen-only mode the transmitter of the transceiver is disabled, effectively

providing a transceiver listen-only behavior. The receiver will still convert the analog bus

signal on pins CANH and CANL into digital data, available for output to pin RXD. As in

Normal mode the bus pins are biased at 0.5VCC, and pin INH remains active.

Fig 3. Mode transitions when VCC, VI/O and VBAT are present

mgu983

STANDBY

MODE

NORMAL

MODE

GO-TO-SLEEP

COMMAND

MODE

LEGEND:

= H, = L

flag set

flags cleared

logical state of pin

setting pwon and/or wake-up flag

pwon and wake-up flag both cleared

SLEEP

MODE

PWON/LISTEN-

ONLY MODE

flags cleared

and

t > th(min)

STB = H and EN = H

and

UVNOM cleared

STB = H and EN = L

and

UVNOM cleared

STB = L

and

flag set

STB = L

and

(EN = L or flag set)

STB = L and EN = H

and

flags cleared

STB = H

and

EN = H

STB = H

and

EN = L

STB = L

and

(EN = L or flag set) STB = L and EN = H

and

flags cleared

STB = L

and

EN = H

STB = H

and

EN = H

STB = L

and

EN = L

STB = H

and

EN = L

STB = H

and

EN = H

STB = H

and

EN = L

Product data sheet Rev. 04 — 29 July 2008 7 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

7.1.3 Standby mode

The Standby mode is the ﬁrst-level power saving mode of the transceiver, offering reduced

current consumption. In Standby mode the transceiver is not able to transmit or receive

data and the low-power receiver is activated to monitor bus activity. The bus pins are

biased at ground level (via Ri(cm)). Pin INH is still active, so voltage regulators controlled

by this pin INH will be active too.

Pins RXD and ERR will reﬂect any wake-up requests (provided that VI/O and VCC are

present).

7.1.4 Go-to-sleep command mode

The Go-to-sleep command mode is the controlled route for entering Sleep mode. In

Go-to-sleep command mode the transceiver behaves as if in Standby mode, plus a

Go-to-sleep command is issued to the transceiver. After remaining in Go-to-sleep

command mode for the minimum hold time (th(min)), the transceiver will enter Sleep mode.

The transceiver will not enter the Sleep mode if the state of pins STB or EN is changed or

the UVBAT, pwon or wake-up ﬂag is set before th(min) has expired.

7.1.5 Sleep mode

The Sleep mode is the second-level power saving mode of the transceiver. Sleep mode is

entered via the Go-to-sleep command mode, and also when the undervoltage detection

time on either VCC or VI/O elapses before that voltage level has recovered. In Sleep mode

the transceiver still behaves as described for Standby mode, but now pin INH is set

ﬂoating. Voltage regulators controlled by pin INH will be switched off, and the current into

pin VBAT is reduced to a minimum. Waking up a node from Sleep mode is possible via the

wake-up ﬂag and (as long as the UVNOM ﬂag is not set) via pin STB.

7.2 Internal ﬂags

The TJA1041A makes use of seven internal ﬂags for its fail-safe fallback mode control and

system diagnosis support. Table 4 shows the relation between ﬂags and operating modes

of the transceiver. Five of the internal ﬂags can be made available to the controller via

pin ERR. Table 5 shows the details on how to access these ﬂags. The following sections

describe the seven internal ﬂags.

Table 5. Accessing internal ﬂags via pin ERR

Internal

ﬂag Flag is available on pin ERR[1] Flag is cleared

UVNOM no by setting the pwon or wake-up ﬂag

UVBAT no when VBAT has recovered

pwon in Pwon/Listen-only mode (coming from

Standby mode, Go-to-sleep command

mode, or Sleep mode)

on entering Normal mode

wake-up in Standby mode, Go-to-sleep command

mode, and Sleep mode (provided that VI/O

and VCC are present)

on entering Normal mode, or by setting

the pwon or UVNOM ﬂag

Product data sheet Rev. 04 — 29 July 2008 8 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

[1] Pin ERR is an active-LOW output, so a LOW-level indicates a set ﬂag and a HIGH-level indicates a cleared

ﬂag. Allow pin ERR to stabilize for at least 8 µs after changing operating modes.

[2] Allow for a TXD dominant time of at least 4 µs per dominant-recessive cycle.

7.2.1 UVNOM ﬂag

UVNOM is the VCC and VI/O undervoltage detection ﬂag. The ﬂag is set when the voltage

on pin VCC drops below VCC(sleep) for longer than tUV(VCC) or when the voltage on pin VI/O

drops below VI/O(sleep) for longer than tUV(VI/O). When the UVNOM ﬂag is set, the transceiver

will enter Sleep mode to save power and not disturb the bus. In Sleep mode the voltage

regulators connected to pin INH are disabled, avoiding the extra power consumption in

case of a short circuit condition. After a waiting time (ﬁxed by the same timers used for

setting UVNOM) any wake-up request or setting of the pwon ﬂag will clear UVNOM and the

timers, allowing the voltage regulators to be reactivated at least until UVNOM is set again.

7.2.2 UVBAT ﬂag

UVBAT is the VBAT undervoltage detection ﬂag. The ﬂag is set when the voltage on

pin VBAT drops below VBAT(stb). When UVBAT is set, the transceiver will try to enter

Standby mode to save power and not disturb the bus. UVBAT is cleared when the voltage

on pin VBAT has recovered. The transceiver will then return to the operating mode

determined by the logic state of pins STB and EN.

7.2.3 Pwon ﬂag

Pwon is the VBAT power-on ﬂag. This ﬂag is set when the voltage on pin VBAT has

recovered after it dropped below VBAT(pwon), particularly after the transceiver was

disconnected from the battery. By setting the pwon ﬂag, the UVNOM ﬂag and timers are

cleared and the transceiver cannot enter Sleep mode. This ensures that any voltage

regulator connected to pin INH is activated when the node is reconnected to the battery. In

Pwon/Listen-only mode the pwon ﬂag can be made available on pin ERR. The ﬂag is

cleared when the transceiver enters Normal mode.

7.2.4 Wake-up ﬂag

The wake-up ﬂag is set when the transceiver detects a local or a remote wake-up request.

A local wake-up request is detected when a logic state change on pin WAKE remains

stable for at least twake. A remote wake-up request is detected after two bus dominant

states of at least tBUSdom (with each dominant state followed by a recessive state of at

least tBUSrec). The wake-up ﬂag can only be set in Standby mode, Go-to-sleep command

mode or Sleep mode. Setting of the ﬂag is blocked during the UVNOM ﬂag waiting time. By

setting the wake-up ﬂag, the UVNOM ﬂag and timers are cleared. The wake-up ﬂag is

wake-up

source in Normal mode (before the fourth

dominant to recessive edge on pin TXD[2])on leaving Normal mode, or by setting

the pwon ﬂag

bus failure in Normal mode (after the fourth dominant

to recessive edge on pin TXD[2])on reentering Normal mode

local failure in Pwon/Listen-only mode (coming from

Normal mode) on entering Normal mode or when RXD

is dominant while TXD is recessive

(provided that all local failures are

resolved)

Table 5. Accessing internal ﬂags via pin ERR

…continued

Internal

ﬂag Flag is available on pin ERR[1] Flag is cleared

Product data sheet Rev. 04 — 29 July 2008 9 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

immediately available on pins ERR and RXD (provided that VI/O and VCC are present).

The ﬂag is cleared at power-on, or when the UVNOM ﬂag is set or the transceiver enters

Normal mode.

7.2.5 Wake-up source ﬂag

Wake-up source recognition is provided via the wake-up source ﬂag, which is set when

the wake-up ﬂag is set by a local wake-up request via pin WAKE. The wake-up source ﬂag

can only be set after the pwon ﬂag is cleared. In Normal mode the wake-up source ﬂag

can be made available on pin ERR. The ﬂag is cleared at power-on or when the

transceiver leaves Normal mode.

7.2.6 Bus failure ﬂag

The bus failure ﬂag is set if the transceiver detects a bus line short circuit condition to

VBAT, VCC or GND during four consecutive dominant-recessive cycles on pin TXD, when

trying to drive the bus lines dominant. In Normal mode the bus failure ﬂag can be made

available on pin ERR. The ﬂag is cleared when the transceiver reenters Normal mode.

7.2.7 Local failure ﬂag

In Normal mode or Pwon/Listen-only mode the transceiver can recognize ﬁve different

local failures and will combine them into one local failure ﬂag. The ﬁve local failures are:

TXD dominant clamping, RXD recessive clamping, a TXD-to-RXD short circuit, bus

dominant clamping, and overtemperature. Nature and detection of these local failures is

described in Section 7.3. In Pwon/Listen-only mode the local failure ﬂag can be made

available on pin ERR. The ﬂag is cleared when entering Normal mode or when RXD is

dominant while TXD is recessive, provided that all local failures are resolved.

7.3 Local failures

The TJA1041A can detect ﬁve different local failure conditions. Any of these failures will

set the local failure ﬂag. In most cases the transmitter of the transceiver will be disabled.

The following sections give the details.

7.3.1 TXD dominant clamping detection

A permanent LOW-level on pin TXD (due to a hardware or software application failure)

would drive the CAN bus into a permanent dominant state, blocking all network

communication. The TXD dominant time-out function prevents such a network lockup by

disabling the transmitter of the transceiver if pin TXD remains at a LOW level for longer

than the TXD dominant time-out tdom(TXD). The tdom(TXD) timer deﬁnes the minimum

possible bit rate of 40 kbit/s. The transmitter remains disabled until the local failure ﬂag is

cleared.

7.3.2 RXD recessive clamping detection

An RXD pin clamped to HIGH-level will prevent the controller connected to this pin from

recognizing a bus dominant state. So the controller can start messages at any time, which

is likely to disturb all bus communication. RXD recessive clamping detection prevents this

effect by disabling the transmitter when the bus is in dominant state without RXD reﬂecting

this. The transmitter remains disabled until the local failure ﬂag is cleared.

Product data sheet Rev. 04 — 29 July 2008 10 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

7.3.3 TXD-to-RXD short-circuit detection

A short circuit between pins RXD and TXD would keep the bus in a permanent dominant

state once the bus is driven dominant, because the low-side driver of RXD is typically

stronger than the high-side driver of the controller connected to TXD. The TXD-to-RXD

short circuit detection prevents such a network lockup by disabling the transmitter. The

transmitter remains disabled until the local failure ﬂag is cleared.

7.3.4 Bus dominant clamping detection

A CAN bus short circuit (to VBAT, VCC or GND) or a failure in one of the other network

nodes could result in a differential voltage on the bus high enough to represent a bus

dominant state. Because a node will not start transmission if the bus is dominant, the

normal bus failure detection will not detect this failure, but the bus dominant clamping

detection will. The local failure ﬂag is set if the dominant state on the bus persists for

longer than tdom(bus). By checking this ﬂag, the controller can determine if a clamped bus is

blocking network communication. There is no need to disable the transmitter. Note that

the local failure ﬂag does not retain a bus dominant clamping failure and is released as

soon as the bus returns to recessive state.

7.3.5 Overtemperature detection

To protect the output drivers of the transceiver against overheating, the transmitter will be

disabled if the virtual junction temperature exceeds the shutdown junction temperature

Tj(sd). The transmitter remains disabled until the local failure ﬂag is cleared.

7.4 Recessive bus voltage stabilization

In recessive state the output impedance of transceivers is relatively high. In a partially

powered network (supply voltage is off in some of the nodes) any deactivated transceiver

with a signiﬁcant leakage current is likely to load the recessive bus to ground. This will

cause a common-mode voltage step each time transmission starts, resulting in increased

EME. Using pin SPLIT of the TJA1041A in combination with split termination (see

Figure 5) will reduce this step effect. In Normal mode and Pwon/Listen-only mode

pin SPLIT provides a stabilized 0.5VCC DC voltage. In Standby mode, Go-to-sleep

command mode and Sleep mode pin SPLIT is set ﬂoating.

7.5 I/O level adapter

The TJA1041A is equipped with a built-in I/O-level adapter. By using the supply voltage of

the controller (to be supplied at pin VI/O) the level adapter ratiometrically scales the

I/O-levels of the transceiver. For pins TXD, STB and EN the digital input threshold level is

adjusted, and for pins RXD and ERR the HIGH-level output voltage is adjusted. This

allows the transceiver to be directly interfaced with controllers on supply voltages between

2.8 V and 5.25 V, without the need for glue logic.

7.6 Pin WAKE

Pin WAKE of the TJA1041A allows local wake-up triggering by a LOW-to-HIGH state

change as well as a HIGH-to-LOW state change. This gives maximum ﬂexibility when

designing a local wake-up circuit. To keep current consumption at a minimum, after a twake

delay the internal bias voltage of pin WAKE will follow the logic state of this pin. A HIGH

level on pin WAKE is followed by an internal pull-up to VBAT. A LOW level on pin WAKE is

Product data sheet Rev. 04 — 29 July 2008 11 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

followed by an internal pull-down towards GND. To ensure EMI performance in

applications not using local wake-up it is recommended to connect pin WAKE to pin VBAT

or to pin GND.

8. Limiting values

[1] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor (6 kV level with pin GND

connected to ground).

[2] Equivalent to discharging a 200 pF capacitor via a 0.75 µH series inductor and a 10 Ω series resistor.

[3] Junction temperature in accordance with IEC 60747-1. An alternative deﬁnition is:

Tvj =T

amb +P×Rth(vj-amb), where Rth(vj-amb) is a ﬁxed value. The rating for Tvj limits the allowable

combinations of power dissipation (P) and ambient temperature (Tamb).

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VCC DC voltage on pin VCC no time limit −0.3 +6 V

operating range 4.75 5.25 V

VI/O DC voltage on pin VI/O no time limit −0.3 +6 V

operating range 2.8 5.25 V

VBAT DC voltage on pin VBAT no time limit −0.3 +40 V

operating range 5 27 V

load dump - 40 V

VTXD DC voltage on pin TXD −0.3 VI/O + 0.3 V

VRXD DC voltage on pin RXD −0.3 VI/O + 0.3 V

VSTB DC voltage on pin STB −0.3 VI/O + 0.3 V

VEN DC voltage on pin EN −0.3 VI/O + 0.3 V

VERR DC voltage on pin ERR −0.3 VI/O + 0.3 V

VINH DC voltage on pin INH −0.3 VBAT + 0.3 V

VWAKE DC voltage on pin WAKE −0.3 VBAT + 0.3 V

IWAKE DC current on pin WAKE - −15 mA

VCANH DC voltage on pin CANH 0 < VCC < 5.25 V; no time limit −27 +40 V

VCANL DC voltage on pin CANL 0 < VCC < 5.25 V; no time limit −27 +40 V

VSPLIT DC voltage on pin SPLIT 0 < VCC < 5.25 V; no time limit −27 +40 V

Vtrt transientvoltagesonpins

CANH, CANL, SPLIT

and VBAT

according to ISO 7637;

see Figure 6 −200 +200 V

Vesd electrostatic discharge

voltage Human Body Model (HBM) [1]

pins CANH, CANL and

SPLIT −6+6 kV

pins TXD, RXD, VI/O and

STB −3+3 kV

all other pins −4+4 kV

Machine Model (MM) [2] −200 +200 V

Tvj virtual junction

temperature [3] −40 +150 °C

Tstg storage temperature −55 +150 °C

Product data sheet Rev. 04 — 29 July 2008 12 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

9. Thermal characteristics

10. Characteristics

Table 7. Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction

to ambient in SO14 package in free air 120 K/W

Rth(j-s) thermal resistance from junction

to substrate of bare die in free air 40 K/W

Table 8. Characteristics

= 4.75 V to 5.25 V; V

I/O

= 2.8 V to V

; V

BAT

=5Vto27V; R

=60

Ω

; T

−

C to +150

C; unless otherwise

speciﬁed; all voltages are deﬁned with respect to ground; positive currents ﬂow into the device

[1]

Symbol Parameter Conditions Min Typ Max Unit

Supplies (pins VBAT, VCC and VI/O)

VCC(sleep) VCC undervoltagedetection

level for forced Sleep mode VBAT = 12 V (fail-safe) 2.75 3.3 4.5 V

VI/O(sleep) VI/O undervoltagedetection

level for forced Sleep mode 0.5 1.5 2 V

VBAT(stb) VBAT voltage level for

fail-safe fallback mode VCC = 5 V (fail-safe) 2.75 3.3 4.5 V

VBAT(pwon) VBAT voltage level for

setting pwon ﬂag VCC = 0 V 2.5 3.3 4.1 V

ICC VCC input current normal mode; VTXD = 0 V (dominant) 25 55 80 mA

normal or pwon/listen-only mode;

VTXD =V

I/O (recessive) 2 6 10 mA

standby or sleep mode - 1 10 µA

II/O VI/O input current normal mode; VTXD = 0 V (dominant) 100 350 1000 µA

normal or pwon/listen-only mode;

VTXD =V

I/O (recessive) 15 80 200 µA

standby or sleep mode - 0 5 µA

IBAT VBAT input current normal or pwon/listen-only mode 15 30 40 µA

standby mode; VCC > 4.75 V;

VI/O = 2.8 V;

VINH =V

WAKE =V

BAT =12V

10 20 30 µA

sleep mode; VINH =V

CC =V

I/O =0V;

VWAKE =V

BAT =12V 10 20 30 µA

Transmitter data input (pin TXD)

VIH HIGH-level input voltage 0.7VI/O -V

CC + 0.3 V

VIL LOW-level input voltage −0.3 - 0.3VI/O V

IIH HIGH-level input current normal or pwon/listen-only mode;

VTXD =V

I/O

−50 +5 µA

IIL LOW-level input current normal or pwon/listen-only mode;

VTXD = 0.3VI/O

−70 −250 −500 µA

Ciinput capacitance not tested - 5 10 pF

Product data sheet Rev. 04 — 29 July 2008 13 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

Receiver data output (pin RXD)

IOH HIGH-level output current VRXD =V

I/O −0.4 V; VI/O =V

CC −1−3−6mA

IOL LOW-level output current VRXD = 0.4 V; VTXD =V

I/O;

bus dominant 2 5 12 mA

Standby and enable control inputs (pins STB and EN)

VIH HIGH-level input voltage 0.7VI/O -V

CC + 0.3 V

VIL LOW-level input voltage −0.3 - 0.3VI/O V

IIH HIGH-level input current VSTB =V

EN = 0.7VI/O 14 10µA

IIL LOW-level input current VSTB =V

EN =0V - 0 −1µA

Error and power-on indication output (pin ERR)

IOH HIGH-level output current VERR =V

I/O −0.4 V; VI/O =V

CC −4−20 −50 µA

IOL LOW-level output current VERR = 0.4 V 0.1 0.2 0.35 mA

Local wake-up input (pin WAKE)

IIH HIGH-level input current VWAKE =V

BAT −1.9 V −1−5−10 µA

IIL LOW-level input current VWAKE =V

BAT −3.1 V 1 5 10 µA

Vth threshold voltage VSTB =0V V

BAT −3V

BAT −2.5 VBAT −2V

Inhibit output (pin INH)

∆VHHIGH-level voltage drop IINH =−0.18 mA 0.05 0.2 0.8 V

ILleakage current sleep mode - 0 5 µA

Bus lines (pins CANH and CANL)

VO(dom) dominant output voltage VTXD =0V

pin CANH 3 3.6 4.25 V

pin CANL 0.5 1.4 1.75 V

VO(dom)(m) matching of dominant

output voltage

(VCC −VCANH −VCANL)

−0.1 - +0.15 V

VO(dif)(bus) differential bus output

voltage (VCANH −VCANL)VTXD = 0 V (dominant);

45 Ω<R

L<65Ω1.5 - 3.0 V

VTXD =V

I/O (recessive); no load −50 - +50 mV

VO(reces) recessive output voltage normal or pwon/listen-only mode;

VTXD =V

I/O; no load 2 0.5VCC 3V

standby or sleep mode; no load −0.1 0 +0.1 V

IO(sc) short-circuit output current VTXD = 0 V (dominant)

pin CANH; VCANH =0V −40 −70 −95 mA

pin CANL; VCANL = 40 V 40 70 95 mA

IO(reces) recessive output current −27 V < VCAN <32V −2.5 - +2.5 mA

Table 8. Characteristics

…continued

= 4.75 V to 5.25 V; V

I/O

= 2.8 V to V

; V

BAT

=5Vto27V; R

=60

Ω

; T

−

C to +150

C; unless otherwise

speciﬁed; all voltages are deﬁned with respect to ground; positive currents ﬂow into the device

[1]

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 29 July 2008 14 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

Vdif(th) differential receiver

threshold voltage normal or pwon/listen-only mode

(see Figure 7);

−12 V < VCANH <12V;

−12 V < VCANL <12V

0.5 0.7 0.9 V

standby or sleep mode;

−12 V < VCANH <12V;

−12 V < VCANL <12V

0.4 0.7 1.15 V

Vhys(dif) differential receiver

hysteresis voltage normal or pwon/listen-only mode

(see Figure 7);

−12 V < VCANH <12V;

−12 V < VCANL <12V

50 70 100 mV

ILI input leakage current VCC = 0 V VCANH =V

CANL = 5 V 100 170 250 µA

Ri(cm) common-mode input

resistance 15 25 35 kΩ

Ri(cm)(m) common-mode input

resistance matching VCANH =V

CANL −3 0 +3 %

Ri(dif) differential input resistance 25 50 75 kΩ

Ci(cm) common-mode input

capacitance VTXD =V

CC; not tested - - 20 pF

Ci(dif) differential input

capacitance VTXD =V

CC; not tested - - 10 pF

Rsc(bus) detectable short-circuit

resistance between bus

lines and VBAT, VCC and

GND

normal mode 0 - 50 Ω

Common-mode stabilization output (pin SPLIT)

Vooutput voltage normal or pwon/listen-only mode;

−500 µA<I

SPLIT < 500 µA0.3VCC 0.5VCC 0.7VCC V

ILleakage current standby or sleep mode;

−22 V < VSPLIT <35V -0 5 µA

Timing characteristics; see Figure 8) and 9

td(TXD-BUSon) delay TXD to bus active normal mode 25 70 110 ns

td(TXD-BUSoff) delay TXD to bus inactive normal mode 10 50 95 ns

td(BUSon-RXD) delay bus active to RXD normal or pwon/listen-only mode 15 65 115 ns

td(BUSoff-RXD) delay bus inactive to RXD normal or pwon/listen-only mode 35 100 160 ns

tPD(TXD-RXD) propagation delay TXD to

RXD VSTB = 0 V 40 - 255 ns

tUV(VCC) undervoltage detection

time on VCC

5 10 12.5 ms

tUV(VI/O) undervoltage detection

time on VI/O

5 10 12.5 ms

tdom(TXD) TXD dominant time-out VTXD = 0 V 300 600 1000 µs

tdom(bus) bus dominant time-out Vdif > 0.9 V 300 600 1000 µs

th(min) minimum hold time of

go-to-sleep command 20 35 50 µs

Table 8. Characteristics

…continued

= 4.75 V to 5.25 V; V

I/O

= 2.8 V to V

; V

BAT

=5Vto27V; R

=60

Ω

; T

−

C to +150

C; unless otherwise

speciﬁed; all voltages are deﬁned with respect to ground; positive currents ﬂow into the device

[1]

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 29 July 2008 15 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

[1] All parameters are guaranteed over the virtual junction temperature range by design, but only 100 % tested at Tamb = 125 °C for dies on

wafer level and in addition to this, 100 % tested at Tamb = 125 °C for cased products, unless speciﬁed otherwise. For bare dies, all

parameters are only guaranteed with the reverse side of the die connected to ground.

11. Application information

tBUSdom dominant time for wake-up

via bus standby or sleep mode; VBAT = 12 V 0.75 1.75 5 µs

tBUSrec recessive time for wake-up

via bus standby or sleep mode; VBAT = 12 V 0.75 1.75 5 µs

twake minimum wake-up time

after receiving a falling or

rising edge

standby or sleep mode; VBAT =12V 5 25 50 µs

Thermal shutdown

Tj(sd) shutdown junction

temperature 155 165 180 °C

Table 8. Characteristics

…continued

= 4.75 V to 5.25 V; V

I/O

= 2.8 V to V

; V

BAT

=5Vto27V; R

=60

Ω

; T

−

C to +150

C; unless otherwise

speciﬁed; all voltages are deﬁned with respect to ground; positive currents ﬂow into the device

[1]

Symbol Parameter Conditions Min Typ Max Unit

Fig 4. Typical application with 3 V microcontroller

SPLIT

CAN bus wires

TJA1041A MICRO-

CONTROLLER

WAKE

VI/O

INH

VBAT VCC

5710 3 VCC

Port x, y, z

RXD

TXD

STB

GND

CANLCANH 11 1213

mnb116

TXD

RXD

ERR

5 V

BAT

3 V

Product data sheet Rev. 04 — 29 July 2008 16 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

12. Test information

Fig 5. Stabilization circuitry and application

GND

VCC

VSPLIT = 0.5VCC

in normal mode

and pwon/listen-only

mode;

otherwise floating

TJA1041A

SPLIT

60 Ω

mnb117

VSPLIT

CANH

CANL

(1) The waveforms of the applied transients will be in accordance with ISO 7637 part 1, test pulses 1,

2, 3a, 3b, 5, 6 and 7.

Fig 6. Test circuit for automotive transients

mnb118

10 µF

1 nF

1 nF TRANSIENT

GENERATOR

100 nF47 µF

+5 V

+12 V

TJA1041A

WAKE

TXD

500 kHz 8

310

STB

ERR

RXD

VI/O

GND

VCC VBAT

SPLIT

CANL

CANH

INH

Product data sheet Rev. 04 — 29 July 2008 17 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

Fig 7. Hysteresis of the receiver

Fig 8. Test circuit for timing characteristics

mgs378

VRXD

HIGH

LOW

hysteresis

0.5 0.9 Vi(dif)(bus) (V)

mnb119

10 µF

15 pF

100 nF47 µF

100 pF

60 Ω

+5 V

+12 V

TJA1041A

WAKE

TXD

310

STB

ERR

RXD

VI/O

GND

VCC VBAT

SPLIT

CANL

CANH

INH

Product data sheet Rev. 04 — 29 July 2008 18 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

12.1 Quality information

This product has been qualiﬁed in accordance with the Automotive Electronics Council

(AEC) standard

Q100 - Stress test qualiﬁcation for integrated circuits

, and is suitable for

use in automotive applications.

(1) Vi(dif)(bus) =V

CANH −VCANL.

Fig 9. Timing diagram

mgs377

td(TXD-BUSon)

tPD(TXD-RXD) tPD(TXD-RXD)

0.3VCC 0.7VCC

0.9 V

0.5 V

HIGH

LOW

CANH

TXD

RXD

CANL

Vi(dif)(bus)(1)

HIGH

recessive

(BUS off)

dominant

(BUS on)

LOW

td(TXD-BUSoff)

td(BUSon-RXD) td(BUSoff-RXD)

Product data sheet Rev. 04 — 29 July 2008 19 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

13. Package outline

Fig 10. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 04 — 29 July 2008 20 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

14. Bare die outline

[1] All x/y coordinates represent the position of the center of each pad (in µm) with respect to the left hand

bottom corner of the top aluminium layer.

(1) The reverse side of the bare die must be connected to ground.

Fig 11. Bonding pad locations

Table 9. Bonding pad locations

Symbol Pad Coordinates[1]

x y

TXD 1 664.25 3004.5

GND 2 75.75 3044.25

VCC 3 115.5 2573

RXD 4 115.5 1862.75

VI/O 5 115.5 115.5

EN 6 264.5 114

INH 7 667.75 85

ERR 8 1076.75 115.5

WAKE 9 1765 85

VBAT 10 1765 792.5

SPLIT 11 1765 1442.25

CANL 12 1765 2115

CANH 13 1751 3002.5

STB 14 940.75 3004.5

mdb634

TJA1041AU

678 9

141

Product data sheet Rev. 04 — 29 July 2008 21 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

15.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

15.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

Product data sheet Rev. 04 — 29 July 2008 22 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

15.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 12) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 10 and 11

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 12.

Table 10. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 11. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 04 — 29 July 2008 23 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

16. Revision history

MSL: Moisture Sensitivity Level

Fig 12. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

TJA1041A_4 20080729 Product data sheet - TJA1041A_3

Modiﬁcations: •Table 8: corrected unit for IOH - pin ERR

TJA1041A_3 20071204 Product data sheet - TJA1041A_2

TJA1041A_2 20040220 Product speciﬁcation - TJA1041A_1

TJA1041A_1 20030929 Objective speciﬁcation - -

Product data sheet Rev. 04 — 29 July 2008 24 of 25

NXP Semiconductors TJA1041A

High-speed CAN transceiver

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Bare die — All die are tested on compliance with their related technical

speciﬁcations as stated in this data sheet up to the point of wafer sawing and

are handled in accordance with the NXP Semiconductors storage and

transportation conditions. If there are data sheet limits not guaranteed, these

will be separately indicated in the data sheet. There are no post-packing tests

performed on individual die or wafers.

NXP Semiconductors has no control of third party procedures in the sawing,

handling, packing or assembly of the die. Accordingly, NXP Semiconductors

assumes no liability for device functionality or performance of the die or

systems after third party sawing, handling, packing or assembly of the die. It

is the responsibility of the customer to test and qualify their application in

which the die is used.

All die sales are conditioned upon and subject to the customer entering into a

written die sale agreement with NXP Semiconductors through its legal

department.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors TJA1041A

High-speed CAN transceiver

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 July 2008

Document identifier: TJA1041A_4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 Optimized for in-vehicle high-speed

communication . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.2 Low-power management . . . . . . . . . . . . . . . . . 1

2.3 Protection and diagnosis (detection and

signalling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 4

7.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5

7.1.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.1.2 Pwon/Listen-only mode . . . . . . . . . . . . . . . . . . 6

7.1.3 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.1.4 Go-to-sleep command mode . . . . . . . . . . . . . . 7

7.1.5 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.2 Internal ﬂags. . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.2.1 UVNOM ﬂag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2.2 UVBAT ﬂag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2.3 Pwon ﬂag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2.4 Wake-up ﬂag. . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2.5 Wake-up source ﬂag. . . . . . . . . . . . . . . . . . . . . 9

7.2.6 Bus failure ﬂag . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.2.7 Local failure ﬂag . . . . . . . . . . . . . . . . . . . . . . . . 9

7.3 Local failures. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.3.1 TXD dominant clamping detection . . . . . . . . . . 9

7.3.2 RXD recessive clamping detection. . . . . . . . . . 9

7.3.3 TXD-to-RXD short-circuit detection . . . . . . . . 10

7.3.4 Bus dominant clamping detection. . . . . . . . . . 10

7.3.5 Overtemperature detection. . . . . . . . . . . . . . . 10

7.4 Recessive bus voltage stabilization . . . . . . . . 10

7.5 I/O level adapter . . . . . . . . . . . . . . . . . . . . . . . 10

7.6 Pin WAKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11

9 Thermal characteristics. . . . . . . . . . . . . . . . . . 12

10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 12

11 Application information. . . . . . . . . . . . . . . . . . 15

12 Test information. . . . . . . . . . . . . . . . . . . . . . . . 16

12.1 Quality information . . . . . . . . . . . . . . . . . . . . . 18

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19

14 Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 20

15 Soldering of SMD packages. . . . . . . . . . . . . . 21

15.1 Introduction to soldering. . . . . . . . . . . . . . . . . 21

15.2 Wave and reﬂow soldering. . . . . . . . . . . . . . . 21

15.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 21

15.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 22

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 23

17 Legal information . . . . . . . . . . . . . . . . . . . . . . 24

17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24

17.2 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 24

18 Contact information . . . . . . . . . . . . . . . . . . . . 24

19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25