2SJ552(L), 2SJ552(S) Silicon P Channel MOS FET REJ03G0899-0400 (Previous: ADE-208-651B) Rev.4.00 Sep 07, 2005 Description High speed power switching Features * Low on-resistance RDS (on) = 0.042 typ. * Low drive current. * 4 V gate drive devices. * High speed switching. Outline RENESAS Package code: PRSS0004AE-A (Package name: LDPAK (L) ) RENESAS Package code: PRSS0004AE-B (Package name: LDPAK (S)-(1) ) D 4 4 1. Gate 2. Drain 3. Source 4. Drain G 1 1 2 2 3 3 S Rev.4.00 Sep 07, 2005 page 1 of 8 2SJ552(L), 2SJ552(S) Absolute Maximum Ratings (Ta = 25C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Symbol VDSS Value -60 Unit V VGSS ID 20 -20 V A -80 -20 A A ID (pulse) IDR Note 1 Note 3 Avalanche current Avalanche energy IAP Note 3 EAR -20 34 A mJ Channel dissipation Channel temperature Pch Tch Note 2 75 150 W C -55 to +150 C Storage temperature Notes: 1. PW 10 s, duty cycle 1% 2. Value at Tc = 25C 3. Value at Tch = 25C, Rg 50 Tstg Electrical Characteristics (Ta = 25C) Item Symbol Min Typ Max Unit V (BR) DSS V (BR) GSS -60 20 -- -- -- -- V V ID = -10 mA, VGS = 0 IG = 100 A, VDS = 0 IDSS IGSS -- -- -- -- -10 10 A A VDS = -60 V, VGS = 0 VGS = 16 V, VDS = 0 Gate to source cutoff voltage Static drain to source on state resistance VGS (off) RDS (on) -1.0 -- -- 0.042 -2.0 0.055 V ID = -1 mA, VDS = -10 V Note 4 ID = -10 A, VGS = -10 V Forward transfer admittance RDS (on) |yfs| -- 10 0.065 16 0.095 -- S ID = -10 A, VGS = -4 V Note 4 ID = -10 A, VDS = -10 V Input capacitance Output capacitance Ciss Coss -- -- 1750 800 -- -- pF pF Reverse transfer capacitance Turn-on delay time Crss td (on) -- -- 180 16 -- -- pF ns VDS = -10 V VGS = 0 f = 1 MHz Rise time Turn-off delay time tr td (off) -- -- 100 230 -- -- ns ns Fall time Body to drain diode forward voltage tf VDF -- -- 140 -1.0 -- -- ns V trr -- 100 -- ns Drain to source breakdown voltage Gate to source breakdown voltage Zero gate voltage drain current Gate to source leak current Body to drain diode reverse recovery time Note: 4. Pulse test Rev.4.00 Sep 07, 2005 page 2 of 8 Test Conditions Note 4 VGS = -10 V ID = -10 A RL = 3 IF = -20 A, VGS = 0 IF = -20 A, VGS = 0 diF/dt = 50 A/s 2SJ552(L), 2SJ552(S) Main Characteristics Maximum Safe Operation Area Power vs. Temperature Derating -1000 ID (A) -300 60 Drain Current Channel Dissipation Pch (W) 80 40 20 10 s -100 0 = 1 1 ms s 0m Op s( era 1s tio ho n( t) Tc Operation in =2 5 this area is C) limited by RDS (on) PW -30 DC -10 -3 -1 -0.3 0 0 50 100 150 Case Temperature Ta = 25C -0.1 -0.1 -0.3 -1 200 Tc (C) -40 -30 -100 VDS (V) -50 -8 V -4.5 V -6 V -5 V Pulse Test -4 V VDS = -10 V Pulse Test -40 -30 Drain Current -30 Drain Current -10 Typical Transfer Characteristics ID (A) ID (A) -10 V -3 Drain to Source Voltage Typical Output Characteristics -50 10 -3.5 V -20 -3 V -10 -20 -10 25C Tc = 75C VGS = -2.5 V -25C 0 0 -2 -4 -6 -8 -10 Drain to Source Saturation Voltage vs. Gate to Source Voltage -2.0 Pulse Test -1.6 -1.2 ID = -20 A -0.8 -10 A -0.4 -5 A -2 A 0 0 -4 -8 -12 Gate to Source Voltage Rev.4.00 Sep 07, 2005 page 3 of 8 -16 -20 VGS (V) 0 -1 -2 -3 -4 Gate to Source Voltage VDS (V) -5 VGS (V) Static Drain to Source on State Resistance vs. Drain Current Static Drain to Source on State Resistance RDS (on) () Drain to Source Saturation Voltage VDS (on) (V) Drain to Source Voltage 0 1 Pulse Test 0.5 0.2 VGS = -4 V 0.1 0.05 -10 V 0.02 0.01 -1 -2 -5 -10 Drain Current -20 -50 -100 ID (A) 2SJ552(L), 2SJ552(S) Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance RDS (on) () Static Drain to Source on State Resistance vs. Temperature 0.20 Pulse Test 0.16 -10 A ID = -20 A 0.12 VGS = -4 V 0.08 -5 A -20 A 0.04 -10 V 0 -40 0 -5 A, -10 A 40 80 Case Temperature 120 160 100 30 Tc = -25C 10 25C 3 75C 1 0.3 VDS = -10 V Pulse Test 0.1 -0.1 Tc (C) -10 -30 -100 10000 Pulse Test 500 Capacitance C (pF) Reverse Recovery Time trr (ns) -3 Typical Capacitance vs. Drain to Source Voltage 1000 200 100 50 -1 -3 -10 Reverse Drain Current -30 3000 1000 Coss 300 100 Crss 10 -100 IDR (A) -8 VGS VDS -60 -12 VDD = -10 V -25 V -50 V -80 -16 ID = -20 A -100 0 16 32 Gate Charge Rev.4.00 Sep 07, 2005 page 4 of 8 48 64 Qg (nc) -10 -20 -30 -40 -50 -20 80 VGS (V) 1000 Switching Time t (ns) -40 -4 Gate to Source Voltage -20 0 Switching Characteristics 0 VDD = -10 V -25 V -50 V VGS = 0 f = 1 MHz Drain to Source Voltage VDS (V) Dynamic Input Characteristics 0 Ciss 30 di / dt = 50 A / s VGS = 0, Ta = 25C 20 10 -0.1 -0.3 VDS (V) -1 Drain Current ID (A) Body-Drain Diode Reverse Recovery Time Drain to Source Voltage -0.3 VGS = -10 V, VDD = -30 V PW = 10 s, duty 1 % 500 td(off) 200 tf 100 50 tr 20 td(on) 10 -0.1 -0.3 -1 -3 Drain Current -10 -30 ID (A) -100 2SJ552(L), 2SJ552(S) Reverse Drain Current vs. Source to Drain Voltage Repetitive Avalanche Energy EAR (mJ) Maximum Avalanche Energy vs. Channel Temperature Derating Reverse Drain Current IDR (A) -50 -40 -30 -10 V -20 -5 V VGS = 0, 5 V -10 Pulse Test 0 0 -0.4 -0.8 -1.2 -1.6 Source to Drain Voltage -2.0 50 IAP = -20 A VDD = -25 V duty < 0.1 % Rg 50 40 30 20 10 0 25 50 75 100 125 150 Channel Temperature Tch (C) VSD (V) Normalized Transient Thermal Impedance s (t) Normalized Transient Thermal Impedance vs. Pulse Width 3 Tc = 25C D=1 1 0.5 0.3 0.2 0.1 0.1 0.05 ch - c (t) = s (t) * ch - c ch - c = 1.67C/W, Tc = 25C 0.02 PDM 0.03 0.0 1 1 o sh tp uls 0.01 10 D= e PW T PW T 100 10 m 1m 100 m 1 10 Pulse Width PW (S) Avalanche Test Circuit VDS Monitor Avalanche Waveform L EAR = 1 * L * IAP2 * 2 VDSS VDSS - VDD IAP Monitor Rg V(BR)DSS IAP D.U.T VDD VDS ID Vin -15 V 50 0 Rev.4.00 Sep 07, 2005 page 5 of 8 VDD 2SJ552(L), 2SJ552(S) Switching Time Test Circuit Waveform Vin Vout Monitor Vin Monitor 10% D.U.T. 90% RL 90% 90% Vin -10 V 50 VDD = -30 V Vout td(on) Rev.4.00 Sep 07, 2005 page 6 of 8 10% tr 10% td(off) tf 2SJ552(L), 2SJ552(S) Package Dimensions JEITA Package Code RENESAS Code Package Name MASS[Typ.] PRSS0004AE-A LDPAK(L) / LDPAK(L)V 1.40g 8.6 0.3 1.3 0.15 1.3 0.2 1.37 0.2 0.76 0.1 2.54 0.5 2.54 0.5 RENESAS Code Package Name PRSS0004AE-B LDPAK(S)-(1) / LDPAK(S)-(1)V 0.4 0.1 MASS[Typ.] Unit: mm 1.30g (1.5) 10.0 Rev.4.00 Sep 07, 2005 page 7 of 8 2.54 0.5 0.4 0.1 0.3 3.0 +- 0.5 2.54 0.5 0.2 0.86 +- 0.1 7.8 7.0 2.49 0.2 0.2 0.1 +- 0.1 1.37 0.2 1.3 0.2 7.8 6.6 1.3 0.15 + 0.3 - 0.5 8.6 0.3 (1.5) (1.4) 4.44 0.2 10.2 0.3 1.7 SC-83 2.49 0.2 11.0 0.5 11.3 0.5 0.3 10.0 +- 0.5 (1.4) 4.44 0.2 10.2 0.3 0.2 0.86 +- 0.1 JEITA Package Code Unit: mm 2.2 2SJ552(L), 2SJ552(S) Ordering Information Part Name 2SJ552L-E 2SJ552STL-E Quantity 500 pcs 1000 pcs Shipping Container Box (Sack) Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.4.00 Sep 07, 2005 page 8 of 8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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