SSC2101S Power Factor Correction Continuous Conduction Mode Controller Features and Benefits Description Interleaved Discontinuous Conduction Mode (DCM) operation: low peak current, low ripple current, and low noise; for medium- to high-power applications Constant Voltage Mode control: no auxiliary windings required on inductors because of the built-in arithmetic circuit; achieves a simple PFC system * Maximum on-time: 15 s (typ) Built-in Soft Start function: reduces stress on power devices at startup Built-in High Speed Response (HSR): suppression of output voltage changes during dynamic load transients Error Amplifier reference voltage: 3.5 V (typ) The SSC2101S is a controller IC intended to implement a Discontinuous Conduction Mode (DCM) interleaved Power Factor Correction (PFC) circuit. Using the two-phase interleaved control incorporated in this IC, it is possible to achieve a low cost, high performance PFC system with low input / output ripple currents, low noise, and few external components. Continued on the next page... Package: SOP8 Functional Block Diagram - Peak Current Limitation COMP 1 VCC Gain Control - VFB 3 3.5 V + 8 IS + gm - + R Q S Q 7 OUT1 6 GND - 3.72 V + OVP - + - 0.7 V or 0.5 V + Phase Management VIN 2 VCC UVLO VCC 4 25501.04 VREG5V OVP TSD R Q S Q 5 OUT2 Features and Benefits (continued) Protection Functions Soft Overvoltage Protection (SOVP): output voltage reduction Output Overvoltage Protection (OVP): gate drive on/off on a pulse-by-pulse basis, with auto-restart Overcurrent Protection (OCP): dual-level OCP, with auto-restart Output Open Loop Detection (OLD): switching operation stop and transition to standby mode Open Terminal Protection (OTP): switching operation stop or output voltage reduction, during open condition on VFB, VIN, or IS terminals Thermal Shutdown (TSD): auto-restart with hysteresis Selection Guide Part Number SSC2101S Absolute Maximum Ratings* TA = 25C unless otherwise specified Characteristics Symbol Terminals Rating Unit VCC 4-6 -0.3 to 30 A VCOMP 1-6 -0.3 to 5.5 A VFB 3-6 -0.3 to 5.5 V VFB Terminal Current IFB 3-6 -1 to 1 mA VIN Terminal Voltage VIN 2-6 -0.3 to 5.5 V VIN Terminal Current IIN 2-6 -1 to 1 mA IS Terminal Voltage VIS 8-6 -16.0 to 5.5 V VCC Terminal Voltage COMP Terminal Voltage VFB Terminal Voltage IS Terminal Current Notes IIS 8-6 -1.75 to 1 mA OUT2 Terminal Voltage VOUT2 5-6 -0.3 to 30 V OUT1 Terminal Voltage VOUT1 7-6 -0.3 to 30 V Operating Frame Temperature TFOP - -40 to 85 C Storage Temperature Tstg - -40 to 125 C Junction Temperature Tj - -40 to 125 C *Current polarity is defined relative to the IC: sink as positive, source as negative. Terminal List Table Pin-out Diagram COMP 1 8 IS VIN 2 7 OUT1 VFB 3 6 GND VCC 4 5 OUT2 Name 1 Number COMP Function Error Amplifier output and phase compensation terminal 2 VIN AC mains rectified voltage monitoring input terminal 3 VFB Feedback control terminal, input for: Constant Voltage Mode control signal, Overvoltage Protection signal, and Open Loop Detection signal 4 VCC IC power supply input terminal 5 OUT2 Gate drive 2 output terminal 6 GND IC ground terminal 7 OUT1 Gate drive 1 output terminal 8 IS Peak current detection signal input terminal Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 25501.04 ELECTRICAL CHARACTERISTICS Valid at TA = 25C, unless otherwise specified Characteristics Symbol Test Conditions Terminals Min. Typ. Max. Unit Power Supply Start-up Operation VCC Operation Start Voltage VCC(ON) 4-6 10.8 11.6 12.4 V VCC Operation Stop Voltage VCC(OFF) 4-6 9.8 10.6 11.4 V VCC Undervoltage Lockout Hysteresis VCC(HYS) 4-6 0.8 1.0 1.2 V VCC Circuit Current in Pre-operation ICC(OFF) 4-6 - 40 100 A VCC Circuit Current in Operation ICC(ON) 4-6 - 11.0 15.0 mA VCC Circuit Current During OVP ICC(OVP) 4-6 - 8.0 10.0 mA ICC(Standby) 4-6 - 100 200 A Maximum On-Time tONMAX 7-6 14 15 16 s OUT1 to OUT2 On-Time Matching tRATIO 5-6 7-6 -5 0 5 % OUT1 to OUT2 Phase Difference PHASE 5-6 7-6 170 180 190 deg. VCC Circuit Current During Standby Oscillator Operation Protection Operation VFB Output Open Loop Stop Voltage VFB(OLDL) 3-6 0.46 0.50 0.54 V VFB Output Open Loop Start Voltage VFB(OLDH) 3-6 0.64 0.70 0.76 V VFB Output Overvoltage Protection Voltage VFB(OVP) 3-6 3.64 3.72 3.80 V VFB Output Soft Overvoltage Protection Voltage VFB(SOVP) 3-6 3.60 3.68 3.76 V IS Lower Overcurrent Protection Voltage VIS(OCPL) 8-6 -0.48 -0.42 -0.36 V IS Upper Overcurrent Protection Voltage VIS(OCPH) 8-6 -0.62 -0.55 -0.48 V COMP Sink Current During Protection Mode ICOMP(SK) 1-6 80 100 120 A Upper Thermal Shutdown Protection Threshold Temperature TJTSDH Not tested, guaranteed by design - 150 - - C Lower Thermal Shutdown Protection Threshold Temperature TJTSDL Not tested, guaranteed by design - 140 - - C TJTSDHYS Not tested, guaranteed by design - - 10 - C VFB(REF) 3-6 3.4 3.5 3.6 V gmEA - 80 100 120 S COMP Error Amplifier Maximum Source Current ICOMP(SO) 1-6 -36 -30 -24 A COMP Error Amplifier Maximum Output Voltage VCOMP(MAX) 1-6 4.00 4.12 4.25 V VFB High Speed Response Enable Voltage VFB(HSR)enable Not tested, guaranteed by design 3-6 3.3 3.4 3.5 V Thermal Shutdown Protection Hysteresis Error Amplifier Operation VFB Error Amplifier Reference Voltage VFB Error Amplifier Transconductance Gain Continued on the next page... Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 25501.04 ELECTRICAL CHARACTERISTICS (continued) Valid at TA = 25C, unless otherwise specified Characteristics Symbol Test Conditions Terminals Min. Typ. Max. Unit VFB High Speed Response Active Voltage VFB(HSR)active 3-6 3.1 3.2 3.3 V COMP High Speed Response Source Current ICOMP(SOHSR) 1-6 -120 -100 -80 A IFB(bias) 3-6 - - 1.5 A VCOMP(OLD) 1-6 0.7 0.9 1.1 V OUTx Gate Voltage (Low) VOUT(L) 5-6 7-6 - - 0.3 V OUTx Gate Voltage (High) VOUT(H) 5-6 7-6 - 10.2 - V OUTx Rise Time tr 5-6 7-6 - 70 - ns OUTx Fall Time tf 5-6 7-6 - 35 - ns VFB Input Bias Current COMP Voltage During Output Open Loop Detection Drive Circuit OUTx Peak Source Current IOUT(SO) Not tested, guaranteed by design 5-6 7-6 - -0.5 - A OUTx Peak Sink Current IOUT(SK) Not tested, guaranteed by design 5-6 7-6 - 0.5 - A Terminals Min. Typ. Max. Unit - - 65 85 C/W *Current polarity is defined relative to the IC: sink as positive, source as negative. Thermal Characteristics Valid at TA = 25C Characteristics Symbol Package Thermal Resistance (Junction to Internal Leadframe) RJF Test Conditions Internal leadframe temperature (TF) is measured at the root of pin 6, the GND terminal. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 25501.04 Functional Description Interleaved Discontinuous Conduction Mode (DCM) The well-known single-phase Discontinuous Conduction Mode (DCM) technique achieves low switching noise because the drain current increase starts at zero when a power MOSFET turns on, and the rate of drain current increase is not steep, as shown by the waveforms in Figure 1. However, the usable power level of single-phase DCM is limited by the very high input / output ripple currents that are generated. The SSC2100 series provides two-phase interleaved DCM (see Figure 2). This advanced technique incorporates two boost converters working together to cancel input ripple currents and to reduce output ripple currents. This result is based on a phase difference of 180 between the two converters. Interleaved DCM also achieves a PFC system with lower switching noise and smaller input filter footprint in comparison to single-phase DCM. This is because reducing input / output ripple currents increases the filtering effectiveness of the EMI filter and also reduces switching noise. ID L1 VOUT MOSFET Drain Current IL IL Q1 ID 0 Inductor Current 0 Figure 1. External circuit and current waveforms for single-phase DCM L1 IL(Q1) ID(Q1) VOUT L2 ID MOSFET Drain Current ID(Q2) I D(Q1 0 Q1 IL(Q2) ) ) I D(Q2 Q2 IL IL CM P Inductor Current 0 ) I L(Q2 ) I L(Q1 ILCMP = Composite Inductor Current Figure 2. External circuit and current waveforms for two-phase interleaved DCM Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 25501.04 Startup Operation Soft Start Function VCC is the external power supply input to the SSC2100 IC. The external circuit for the VCC terminal is shown in Figure 3. Soft start is adjusted by the external circuits on the VFB and COMP terminals, as shown in Figure 5. At startup, when the input voltage increases to approximately 20% of the rated output voltage, VOUT , and the VCC terminal voltage increases to VCC(ON) = 11.6 V (typ), soft start operation begins. When AC mains and VCC external voltage are applied, after the VFB terminal voltage increases to VFB(OLDH) = 0.7 V (typ) or more and the VCC terminal voltage increases to VCC(ON) = 11.6 V (typ) or more, the control circuit starts switching operation. Note: One of the startup conditions is that the input voltage must reach 20% or more of the rated value for VOUT . This value of VOUT is equivalent to approximately VFB(OLDH) = 0.7 V (typ). As shown in Figure 6, during the soft start period, the COMP terminal is charged by ICOMP(SO) = -30 A. In this way, the output power increases gradually, reducing stress on the power devices. 8176 When the VCC terminal voltage subsequently decreases to VCC(OFF) = 10.6 V (typ) or less, the control circuit stops switching operation. It does so by enabling the UVLO (undervoltage lockout) circuit, and then reverting to the standby mode that is the state of the IC before startup. When the VFB terminal voltage subsequently decreases to VFB(OLDL) = 0.5 V (typ) or less, the control circuit stops switching operation and reverts to pre-startup standby mode, even if VCC terminal voltage has increased to VCC(ON) or more. Because the regulation range of the VCC internal circuit is very wide, between VCC(OFF) = 11.4 V (max) and the VCC absolute maximum rating of 30 V (max), a wide input voltage range from the external power supply can be applied. The behaviors of ICC during startup and when switching is stopped are shown in Figure 4. % 4 55% %1/2 # 4 % % % 4 +5 8+0 176 8($ )0& 8%% 176 Figure 5. External circuits of VFB and COMP terminals IDS(Q1,Q2) SSC2100 IS 8 1 COMP power supply 2 VIN OUT1 7 3 VFB GND 6 4 VCC C6 VFB VFB(REF) OUT2 5 Cf Time Soft start period Constant voltage operation 3.5 V 3.2 V VOUT=100% 90% of VOUT 0.7 V 0 Figure 3. External circuit of VCC terminal Time ICOMP ICC ICC(ON) 11 mA(typ ) 0 Stop Startup ICOMP(SO) 30A Time VCC ICC(OFF) 40 A(typ) VCC(ON) 11.6 V(typ) External power supply for VCC 10.6 V(typ) VCC(OFF) 11.6V(typ) VCC VCC(ON) 0 Figure 4. Relationship of VCC and ICC at startup and stopping Time Figure 6. Soft Start operation Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 25501.04 using the voltage-mode control method. Thus, a PFC system used with this IC has no requirement for an auxiliary winding to detect zero crossings of the inductor current. This allows simple circuits with few external components. Voltage Control Operation A generic PFC circuit for implementing single-phase DCM is shown in Figure 7. The circuit is composed of a boost inductor (L1), a switching device (Q1), a rectifier diode (D2), and an output capacitor (C2). A control circuit would monitor the C2 voltage and generate an error amplifier output signal to operate Q1. When the control circuit detects an off-time at the L1 Zero Current Detection (ZCD) winding, it turns on Q1 for a period of time. When Q1 is later turned off, the energy stored in L1 is transferred through D2 to C2. After all of the energy stored in L1 is transferred to C2, the control circuit would again turn on Q1, repeating the process. In the boost PFC converter, tON is a function of load power and tOFF is a function of both the input voltage, EIN , and the rated output voltage, VOUT . The relationship between tON and tOFF is given by the following: EIN (1) tOFF > x tON VOUT - EIN The VIN terminal voltage is monitored internally and used to calculate the internal tOFF . The typical relationship between tON and the VIN terminal voltage, VIN , is shown in Figure 8. The maximum tON occurs at VIN = 0 V. The values shown assume VCOMP = 4 V , where VCOMP is the COMP terminal voltage. The SSC2100 series two-phase interleaved DCM uses the VIN terminal to monitor the AC mains rectified input voltage, the VFB terminal to monitor output voltage, and the COMP terminal to monitor phase compensation. This IC internally generates the on-time, tON , and off-time, tOFF , and it controls output voltage '+0 & . As shown in Figure 9, the rectified input voltage is divided by R1 and R2, and input to the VIN terminal. The output voltage is divided by R3 and R4, and input to the VFB terminal. Because of the way in which the VIN terminal voltage and the VFB terminal voltage are used for internal calculations, the two dividers should be well matched. Thus, the R1, R2, and C7 values of the input portion should be equal to the R3, R4, and C8 values of the output portion. 8176 <%& % % 3 R1 is recommended to be a high-value resistor, in the range from several hundred k to several M, 1% tolerance, and of an anti-electromigration type, such as metal oxide film. C8, if necessary to reduce high frequency noise, is recommended to have a capacitance of in the range of 0.1 to 10 nF. Figure 7. PFC circuit with generic single-phase DCM 16 On-Time, t ON (s) 15 14 13 12 11 10 9 8 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VIN terminal voltage, VIN (V) Figure 8. Typical relationship between VIN and tON Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 25501.04 nal voltage increases to VFB(HSR)enable = 3.4 V (typ) or more, the control circuit enables the HSR operation. If the VFB terminal voltage subsequently decreases to VFB(HSR)active = 3.2 V (typ) or less, whether due to dynamic load change or other conditions, the control circuit activates the HSR operation. High Speed Response Function (HSR) The boost PFC converter is supplied by an AC sinusoidal waveform at the local commercial mains input voltage and frequency. However, the IC voltage control circuit, described above, characteristically responds at a relatively slow rate. As a result, the dynamic load response of the IC would be slow, and could cause the output voltage to drop too quickly. When HSR is in active operation, the COMP terminal charges by ICOMP(SOHSR) = -100 A (typ) and the output power increases until the COMP terminal voltage increases to 3.2 V (typ). VFB(HSR)active = 3.2 V (typ) is equivalent to approximately 91.4% of the rated output voltage, VOUT . The innovative built-in High Speed Response (HSR) function reduces variation of the output voltage under dynamic load change conditions. As shown in Figure 10, when the VFB termi4% ' +0 8#% L1 & L2 & 81 76 4 % 4 4 % 3 4 3 4 55% +5 %1/2 4 % 4 % 8+0 176 8($ )0& 8%% 176 Figure 9. External circuits for VIN and VFB terminals OUT1,OUT2 Low HSR OFF HSR enable VFB COMP Sink 3.72 V 3.68 V HSR active 3.5 V 3.4 V 3.2 V 3.2 V SS : Soft start period CV : Constant voltage operation period LC : Dynamic load change period HSR: High speed response operation period OV : Overvoltage operation period HSR 0 ICOMP ICOMP(SK) 0 ICOMP(SO) Time SS CV LC CV OV CV 100A 30A Time ICOMP(SOHSR) 100A Figure 10. VFB terminal voltage waveforms Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 25501.04 Gate Drive The OUT1 and OUT2 terminals each directly drive an external power MOSFET. Currents and voltages are set as follows: Peak Current Gate Voltage Source Sink Low High -0.5 A (typ) 0.5 A (typ) 0.3 V (max) 10.2 V (typ) Resistors R7, R8, R9, and R10 in Figure 11 should be selected for performance in the actual application, because these values relate to the individual board layout patterns and power MOSFET capacities. The gate resistors, R7 and R8, are recommended to be in the range of several ohms to several tens of ohms, and should be selected to reduce gate voltage ringing and EMI noise. R9 and R10 help to prevent malfunctions caused by steep dV/dt during power MOSFET turn-off. The recommended values are in the 10 to 100 k range. These components should be placed close to the gate and source terminals of the corresponding power MOSFET. Error Amplifier Phase Compensation The phase compensation circuit is connected between the COMP and GND terminals, as shown in Figure 12. The COMP terminal is the output of the internal Error Amplifier. The Error Amplifier circuit, which implements the enhanced response functions, consists of a transconductance amplifier and switched current sources. The Error Amplifier response is set below 20 Hz to maintain power factor correction at standard commercial power frequencies of 50 or 60 Hz. The phase compensation components, C4, C5, and R11 (see Figure 12), have typical recommended values shown below, but should be selected for performance in the application: to reduce ripple, or to enhance transient load response at the rated output voltage. * C4: 0.047 to 0.47 F * C5: 0.47 to 10 F * R11: 10 to 100 k Thermal Shutdown Protection (TSD) When the temperature of the IC increases to TJTSDH = 150C (min) or more, the control circuit stops switching operation. Conversely, when temperature decreases to TJTSDL = 140C or less, the control circuit restarts switching operation. The hysteresis of the detection temperature, TJTSDHYS, is 10C (typ). 8176 55% %1/2 +5 8+0 176 8($ )0& 8%% 176 L1 & L2 & 4 8176 % 55% +5 %1/2 4 3 % 4 4 3 4 Figure 11. External circuits for OUTx terminals 4 % % 4 % 8+0 176 8($ )0& 8%% 176 Figure 12. Phase compensation circuit (external COMP terminal circuit) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 25501.04 Overcurrent Protection (OCP) The inductor current of both inductors is monitored by the detection resistor, R5, and is input to the IS terminal, as shown in Figure 13. The overcurrent protection function has two stages, IS Lower OCP, and IS Upper OCP, described below. IS Lower Overcurrent Protection, VIS(OCPL) When the inductor current is increasing and if the IS terminal voltage decreases to VIS(OCPL) = -0.42 V (typ), the control circuit limits the output power by turning off either one or both power MOSFETs, according to the output states of both OUT1 and OUT2, as follows: * If either one of OUT1 or OUT2 is high when the fault occurs, that output is now set low (so both outputs are off). Figure 14 is RC1 EIN L1 D2 L2 D3 * If both OUT1 and OUT2 are high when the fault occurs, the output that went high earlier than the other output (considering the current pulses only) is now set low (the other output remains high). Figure 15 is an example where both OUT1 and OUT2 are high (Q1 and Q2 are on), and the IS terminal detects VIS(OCPL) or lower. Under this condition, because OUT1 was set high before OUT2 was, OUT1 is now set low (and OUT2 remains high). R5 (see Figure 13) should be selected for performance in the actual application, such that IS terminal voltage reaches VIS(OCPL) or lower under the conditions of minimum input voltage and peak load. VOUT MOSFET(Q1) Drain current % Q1 Q1:OFF C2 Q2 MOSFET(Q2) Drain current R10 Inductor current IL an example. Where the IS terminal voltage falls to VIS(OCPL) or lower while OUT1 is high (Q1 is ON) and OUT2 is low, under this condition, OUT1 is set to low. R9 OUT1 terminal R5 R7 R8 R6 SSC2100 %1/2 +5 8+0 176 8($ )0& 8%% 176 OUT2 terminal IS terminal When both OUT1and OUT2 are set to high, OUT1 which is set to high ahead is set to low C3 VIS(OCPL) 0.42V(TYP) Figure 15. VIS(OCPL) operation waveform after both OUT1 and OUT2 are set to high Figure 13. External circuits for IS and OUTx terminals MOSFET(Q1) Drain current Q1= OFF MOSFET(Q2) Drain current OUT1 terminal MOSFET(Q1) Drain current Abnormal state, such as inductor is shorted or is saturated MOSFET(Q2) Drain current OUT1 is set to low after detecting VIS(OCPL) OUT1 terminal OUT2 terminal OUT2 terminal IS terminal IS terminal VIS(OCPL) 0.42V(TYP) Figure 14. VIS(OCPL) operation waveform after OUT1 is set to high and OUT2 is set to low Both OUT1 and OUT2 are set to low after detecting V IS(OCPH) VIS(OCPH) 0.55V(TYP) Figure 16. Phase compensation circuit (external COMP terminal circuit) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 25501.04 R6 is a damping resistor, which buffers IS terminal current against surge currents, such as inrush currents. It is recommended to have a value of 100 . C3, if necessary to reduce high frequency noise, is recommended to have a capacitance of in the range of 0.1 to 10 nF. IS Upper Overcurrent Protection, VIS(OCPH) If the IS terminal voltage decreases to VIS(OCPH) = -0.55 V (typ) or lower, the control circuit limits the output power on a pulse-by-pulse basis by setting both OUT1 and OUT2 low, which turns off both power MOSFETs. This is shown in Figure 16. This protection function operates under abnormal conditions such as when an inductor is shorted or is saturated. Overvoltage Protection (OVP) The overvoltage protection function has two stages, Soft OVP, and OVP, illustrated in Figure 17 and described below. VFB Output Soft Overvoltage Protection, VFB(SOVP) When VFB terminal voltage increases to VFB(SOVP) = 3.68 V (typ), Soft Overvoltage Protection is activated. This discharges the COMP terminal by ICOMP(SK) = 100 A (typ) and the output voltage is decreased. VFB(SOVP) = 3.68 V (typ) is equivalent to about 105% of the rated output voltage, VOUT . The output voltage threshold that initiates Soft Overvoltage Protection, is calculated approximately as follows: VOUT(norm) (2) VOUT(SOVP) x VFB(SOVP) VFB(REF) where VOUT(norm) is VOUT under normal operating conditions, and VFB(REF) is the Error Amplifier reference voltage, 3.5V (typ). VFB terminal voltage 3.72 V(typ) VFB Output Overvoltage Protection, VFB(OVP) When the VFB terminal voltage increases to VFB(OVP) = 3.72 V (typ), both OUT1 and OUT2 are set low on a pulse-by-pulse basis, which stops the output supply by turning off the power MOSFETS. When VFB terminal voltage decreases to VFB(SOVP) , the control circuit stops discharging from the COMP terminal and restores switching operation. The output voltage threshold that initiates Overvoltage Protection, is calculated approximately as follows: VOUT(norm) (3) VOUT(OVP) x VFB(OVP) VFB(REF) where VOUT(norm) is VOUT under normal operating conditions, and VFB(REF) is the Error Amplifier reference voltage, 3.5V (typ). R3 is recommended to be a high-value resistor, in the range from several hundred k to several M, 1% tolerance, and of an anti-electromigration type, such as metal oxide film. C8 is recommended if necessary to reduce high frequency noise, and should have a rating of 0.1 to 10 nF. Open Loop Detection (OLD) In the event that the output voltage detection resistor, R3 (see Figure 18), opens and VFB terminal voltage decreases to VFB(OLDL) = 0.5 V (typ) or less, the control circuit stops the switching operation and enters standby mode. VFB(OLDL) = 0.5 V (typ) is equivalent to about 14.3% of the rated output voltage, VOUT . When the VFB terminal voltage subsequently increases to VFB(OLDH) = 0.7 V (typ) or more, the control circuit restores switching operation. VFB(OLDH) = 0.7 V (typ) is equivalent to about 20% of the rated output voltage, VOUT . OUT1,OUT2 is set to low 106% of V OUT 3.68 V(typ) 8176 VFB(OVP) 105% of V OUT VFB(SOVP) 3.50 V(typ) % VFB(REF) 4 VOUT =100% 0 CV OV CV 55% %1/2 +5 Time # 4 COMP terminal current 100A(typ ) ICOMP(SK) % % 4 % 8+0 176 8($ )0& 8%% 176 Time CV : Constant voltage operation period OV : Overvoltage operation period Figure 17. Overvoltage operation waveform and external circuit Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 25501.04 IS Open Protection The IS terminal is internally connected with a pull-up current source. In the event that the IS terminal is open, the IS terminal voltage is pulled-up to the internal supply voltage, the IC overcurrent protection is activated, and both OUT1 and OUT2 are set low, decreasing the output voltage. Open Terminal Protection (OTP) The VFB, IS, and VIN terminals each have dedicated internal Open Terminal Protection functions. VFB Open Protection The VFB terminal is internally connected with a pull-up current source. In the event that the VFB terminal is open, VFB terminal voltage is pulled-up to the internal supply voltage, the IC overvoltage protection is activated, and both OUT1 and OUT2 are set low, decreasing the output voltage. 4% '+0 VIN Open Protection The VIN terminal is internally connected with a pull-up current source. In the event that the VIN terminal is open, the VIN terminal voltage is pulled-up to the internal supply voltage, and the control circuit limits IC operation or stops it. L1 & L2 & 8176 % 4 4 4 3 % 4 3 4 55% +5 %1/2 4 % 4 % 8+0 176 8($ )0& 8%% 176 Figure 18. External VFB terminal circuit D1 85 to 264 VAC RC1 L1 D2 L2 D3 EMI Filter VOUT C1 R7 R1 Q1 R8 Q2 7 4 VCC SSC2100 5 3 OUT2 VFB 2 OUT1 VIN COMP External power supply R3 C2 1 R4 IS 8 R2 R5 R6 GND 6 C4 GND C3 Figure 18. Typical application diagram Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 25501.04 Package Outline Drawing 10 0 5.2 0.3 8 0.15 +0.1 -0.05 A B 4.4 0.2 Branding: 6.2 0.3 A. Type number (abbreviation): SC21xx C 0.4 0.2 B. Lot number 1st letter: Last digit of year 1 0.695 TYP 0.10 1.27 0.05 2nd letter: Month 2 1 to 9 for January to September O for October N for November D for December 0.4 0.1 0.12 M 3rd letter: Week 1 for dates 1 through 10 2 for dates 11 through 20 3 for dates 21 through 31 1.5 0.1 0.05 0.05 Dimensions in mm Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com C. Sanken tracking number 13 25501.04 Handling and Use Cautions and Warnings Because reliability can be affected adversely by improper storage environments and handling methods during characteristic tests, please observe the following cautions. Cautions for Storage * Ensure that storage conditions comply with standard temperature (5C to 35C) and standard relative humidity (around 40% to 75%) and avoid storage locations that experience extreme changes in temperature or humidity. * Avoid locations where dust or harmful gases are present, and avoid direct sunlight. * Reinspect for rust on leads and solderability of devices which have been stored for a long time. Cautions for Characteristic Tests and Handling * When characteristic tests are carried out during inspection testing and other standard test periods, protect the devices from power surges from the test equipment, and from shorts between the devices and the heatsink. Recommended Operating Temperature * Internal leadframe temperature in operation: TF = 115C (max). Note: Measure at pin 5, close the case molding. Soldering * When soldering the devices, please be sure to minimize the working time, and stay within the following conditions: 260 (+0 / -10) C for 10 s (during reflow ) 350 5 C for 3 s (using a soldering iron ) Considerations to protect the Products from Electrostatic Discharge * When handling the devices, the operator must be grounded. Grounded wrist straps should be worn, and have at least 1 M of resistance from operators to ground to prevent shock hazard. * Workbenches where the devices are handled should be grounded and be provided with conductive table and floor mats. * When using measuring equipment such as a curve tracer, the equipment also should be grounded. * When soldering the devices, the head of the soldering iron or the solder bath must be grounded in order to prevent leakage voltage generated by them from being applied to the devices. * The devices should always be stored and transported in Sanken shipping containers or conductive containers, or be wrapped up in aluminum foil. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 25501.04 The contents in this document are subject to change, for improvement and other purposes, without notice. Make sure that this is the latest version of the document before use. The operation and circuit examples in this document are provided for reference purposes only. Sanken and Allegro MicroSystems assume no liability for violation of industrial property, intellectual property, or other rights of Sanken or Allegro or third parties, that stem from these examples. The user must take responsibility for considering and determining which devices the products described in this document are used with. Although Sanken will continue to improve the quality and reliability of its products, semiconductor products, by their nature, have certain fault and failure rates. The user must take responsibility for designing and checking to secure the product and system so that a product failure may not lead to human injury, fire, damage, or other losses. The products described in this document are intended for use in normal electronic devices (such as home appliances, office equipment, communication terminals, or measurement equipment). If you are considering using Sanken's products in a device that requires high reliability (such as transport machines and their control units, traffic light control systems, disaster prevention and security equipment, or any kind of safety equipment), make sure that you consult a Sanken sales representative. Do not use these products in devices that require extremely high reliability (such as aerospace instruments, nuclear power control units, or life support systems), without Sanken's written consent. The products described in this document are not designed to be radiation-proof. The contents in this document must not be transcribed or copied without Sanken's written consent. This is notification that you, as purchaser of the products/technology, are not allowed to perform any of the following: 1. Resell or retransfer these products/technology to any party intending to disturb international peace and security. 2. Use these products/technology yourself for activities disturbing international peace and security. 3. Allow any other party to use these products/technology for activities disturbing international peace and security. Also, as purchaser of these products/technology, you agree to follow the procedures for the export or transfer of these products/ technology, under the Foreign Exchange and Foreign Trade Law of Japan, when you export or transfer the products/technology abroad. Copyright (c) 2008-2010 Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 25501.04 Worldwide Contacts Asia-Pacific China Sanken Electric Hong Kong Co., Ltd. Korea Sanken Electric Korea Co., Ltd. Samsung Life Yeouido Building 16F 23-10, Yeouido-Dong, Yeongdeungpo-gu Seoul 150-734, Korea Tel: 82-2-714-3700, Fax: 82-2-3272-2145 Suite 1026, Ocean Centre Canton Road, Tsimshatsui Kowloon, Hong Kong Tel: 852-2735-5262, Fax: 852-2735-5494 Singapore Sanken Electric Singapore Pte. Ltd. Sanken Electric (Shanghai) Co., Ltd. Room 3202, Maxdo Centre Xingyi Road 8, Changning District Shanghai, China Tel: 86-21-5208-1177, Fax: 86-21-5208-1757 152 Beach Road, #10-06 The Gateway East Singapore 189721 Tel: 65-6291-4755, Fax: 65-6297-1744 Sanken Electric (Shanghai) Co., Ltd. Shenzhen Office Room 1013, Xinhua Insurance Building Mintian Road, Futian District Shenzhen City, Guangdong, China Tel: 86-755-3391-9356/9358, Fax: 86-755-3391-9368 Europe Sanken Power Systems (UK) Limited Pencoed Technology Park Pencoed, Bridgend CF35 5HY, United Kingdom Tel: 44-1656-869-100, Fax: 44-1656-869-162 Taiwan Sanken Electric Co., Ltd. Room 1801, 18th Floor 88 Jung Shiau East Road, Sec. 2 Taipei 100, Taiwan R.O.C. Tel: 886-2-2356-8161, Fax: 886-2-2356-8261 Japan Sanken Electric Co., Ltd. Overseas Sales Headquarters Metropolitan Plaza Building 1-11-1 Nishi-Ikebukuro, Toshima-ku Tokyo 171-0021, Japan Tel: 81-3-3986-6164, Fax: 81-3-3986-8637 North America United States Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01606, U.S.A. Tel: 1-508-853-5000, Fax: 1-508-853-7895 Allegro MicroSystems, Inc. 14 Hughes Street, Suite B105 Irvine, California 92618, U.S.A. Tel: 1-949-460-2003, Fax: 1-949-460-7837 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 25501.04