Power Factor Correction
Continuous Conduction Mode Controller
SSC2101S
Continued on the next page…
25501.04
Description
The SSC2101S is a controller IC intended to implement
a Discontinuous Conduction Mode (DCM) interleaved
Power Factor Correction (PFC) circuit. Using the two-phase
interleaved control incorporated in this IC, it is possible to
achieve a low cost, high performance PFC system with low
input / output ripple currents, low noise, and few external
components.
Features and Benefits
Interleaved Discontinuous Conduction Mode (DCM)
operation: low peak current, low ripple current, and low
noise; for medium- to high-power applications
Constant Voltage Mode control: no auxiliary windings
required on inductors because of the built-in arithmetic
circuit; achieves a simple PFC system
• Maximum on-time: 15 s (typ)
Built-in Soft Start function: reduces stress on power
devices at startup
Built-in High Speed Response (HSR): suppression of
output voltage changes during dynamic load transients
Error Amplifier reference voltage: 3.5 V (typ)
Functional Block Diagram
Package: SOP8
SOP8
+
–
+
–
+
–
+
–
+
–
+
–
COMP 1
3
2
4
VFB
VIN
VCC
UVLO
TSD
OVP
VREG5V
VCC
Gain
Control
Peak Current
Limitation
8
7
VCC
6
5
IS
OUT1
GND
OUT2
Phase
Management
OVP
3.5 V
3.72 V
0.7 V or
0.5 V
gm
RQ
Q
S
RQ
Q
S
2
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115 Northeast Cutoff
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25501.04
Terminal List Table
Name Number Function
1 COMP Error Amplifier output and phase compensation terminal
2 VIN AC mains rectified voltage monitoring input terminal
3 VFB Feedback control terminal, input for: Constant Voltage Mode control signal,
Overvoltage Protection signal, and Open Loop Detection signal
4 VCC IC power supply input terminal
5 OUT2 Gate drive 2 output terminal
6 GND IC ground terminal
7 OUT1 Gate drive 1 output terminal
8 IS Peak current detection signal input terminal
1
2
3
4
8
7
6
5
IS
OUT1
GND
OUT2
COMP
VIN
VFB
VCC
Pin-out Diagram
Protection Functions
Soft Overvoltage Protection (SOVP): output voltage reduction
Output Overvoltage Protection (OVP): gate drive on/off on a
pulse-by-pulse basis, with auto-restart
Overcurrent Protection (OCP): dual-level OCP, with
auto-restart
Output Open Loop Detection (OLD): switching operation stop
and transition to standby mode
Open Terminal Protection (OTP): switching operation stop or
output voltage reduction, during open condition on VFB, VIN,
or IS terminals
Thermal Shutdown (TSD): auto-restart with hysteresis
Selection Guide
Part Number
SSC2101S
Features and Benefits (continued)
Absolute Maximum Ratings* TA = 25°C unless otherwise specified
Characteristics Symbol Notes Terminals Rating Unit
VCC Terminal Voltage VCC 4 – 6 0.3 to 30 A
COMP Terminal Voltage VCOMP 1 – 6 0.3 to 5.5 A
VFB Terminal Voltage VFB 3 – 6 0.3 to 5.5 V
VFB Terminal Current IFB 3 – 6 1 to 1 mA
VIN Terminal Voltage VIN 2 – 6 0.3 to 5.5 V
VIN Terminal Current IIN 2 – 6 1 to 1 mA
IS Terminal Voltage VIS 8 – 6 16.0 to 5.5 V
IS Terminal Current IIS 8 – 6 1.75 to 1 mA
OUT2 Terminal Voltage VOUT2 5 – 6 0.3 to 30 V
OUT1 Terminal Voltage VOUT1 7 – 6 0.3 to 30 V
Operating Frame Temperature TFOP –40 to 85 °C
Storage Temperature Tstg –40 to 125 °C
Junction Temperature Tj–40 to 125 °C
*Current polarity is defined relative to the IC: sink as positive, source as negative.
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25501.04
ELECTRICAL CHARACTERISTICS Valid at TA = 25°C, unless otherwise specified
Characteristics Symbol Test Conditions Terminals Min. Typ. Max. Unit
Power Supply Start-up Operation
VCC Operation Start Voltage VCC(ON) 4 – 6 10.8 11.6 12.4 V
VCC Operation Stop Voltage VCC(OFF) 4 – 6 9.8 10.6 11.4 V
VCC Undervoltage Lockout Hysteresis VCC(HYS) 4 – 6 0.8 1.0 1.2 V
VCC Circuit Current in Pre-operation ICC(OFF) 4 – 6 – 40 100 A
VCC Circuit Current in Operation ICC(ON) 4 – 6 – 11.0 15.0 mA
VCC Circuit Current During OVP ICC(OVP) 4 – 6 – 8.0 10.0 mA
VCC Circuit Current During Standby ICC(Standby) 4 – 6 – 100 200 A
Oscillator Operation
Maximum On-Time tONMAX 7 – 6 14 15 16 s
OUT1 to OUT2 On-Time Matching tRATIO
5 – 6
7 – 6 50 5 %
OUT1 to OUT2 Phase Difference PHASE
5 – 6
7 – 6 170 180 190 deg.
Protection Operation
VFB Output Open Loop Stop Voltage VFB(OLDL) 3 – 6 0.46 0.50 0.54 V
VFB Output Open Loop Start Voltage VFB(OLDH) 3 – 6 0.64 0.70 0.76 V
VFB Output Overvoltage Protection
Voltage VFB(OVP) 3 – 6 3.64 3.72 3.80 V
VFB Output Soft Overvoltage
Protection Voltage VFB(SOVP) 3 – 6 3.60 3.68 3.76 V
IS Lower Overcurrent Protection
Voltage VIS(OCPL) 8 – 6 0.48 0.42 0.36 V
IS Upper Overcurrent Protection
Voltage VIS(OCPH) 8 – 6 0.62 0.55 0.48 V
COMP Sink Current During
Protection Mode ICOMP(SK) 1 – 6 80 100 120 A
Upper Thermal Shutdown Protection
Threshold Temperature TJTSDH Not tested, guaranteed by design – 150 – – °C
Lower Thermal Shutdown Protection
Threshold Temperature TJTSDL Not tested, guaranteed by design – 140 – – °C
Thermal Shutdown Protection
Hysteresis TJTSDHYS Not tested, guaranteed by design – – 10 – °C
Error Amplifier Operation
VFB Error Amplifier Reference
Voltage VFB(REF) 3 – 6 3.4 3.5 3.6 V
VFB Error Amplifier Transconductance
Gain gmEA – 80 100 120 S
COMP Error Amplifier Maximum
Source Current ICOMP(SO) 1 – 6 –36 –30 –24 A
COMP Error Amplifier Maximum
Output Voltage VCOMP(MAX) 1 – 6 4.00 4.12 4.25 V
VFB High Speed Response
Enable Voltage V
FB(HSR)enable Not tested, guaranteed by design 3 – 6 3.3 3.4 3.5 V
Continued on the next page…
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VFB High Speed Response
Active Voltage VFB(HSR)active 3 – 6 3.1 3.2 3.3 V
COMP High Speed Response
Source Current ICOMP(SOHSR) 1 – 6 –120 –100 –80 A
VFB Input Bias Current IFB(bias) 3 – 6 – – 1.5 A
COMP Voltage During Output Open
Loop Detection VCOMP(OLD) 1 – 6 0.7 0.9 1.1 V
Drive Circuit
OUTx Gate Voltage (Low) VOUT(L)
5 – 6
7 – 6 – – 0.3 V
OUTx Gate Voltage (High) VOUT(H)
5 – 6
7 – 6 – 10.2 – V
OUTx Rise Time tr
5 – 6
7 – 6 –70–ns
OUTx Fall Time tf
5 – 6
7 – 6 –35–ns
OUTx Peak Source Current IOUT(SO) Not tested, guaranteed by design 5 – 6
7 – 6 – –0.5 – A
OUTx Peak Sink Current IOUT(SK) Not tested, guaranteed by design 5 – 6
7 – 6 – 0.5 – A
*Current polarity is defined relative to the IC: sink as positive, source as negative.
ELECTRICAL CHARACTERISTICS (continued) Valid at TA = 25°C, unless otherwise specified
Characteristics Symbol Test Conditions Terminals Min. Typ. Max. Unit
Thermal Characteristics Valid at TA = 25°C
Characteristics Symbol Test Conditions Terminals Min. Typ. Max. Unit
Package Thermal Resistance (Junction
to Internal Leadframe) RJF
Internal leadframe temperature (TF) is
measured at the root of pin 6, the GND
terminal.
– – 65 85 ºC/W
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25501.04
Q1
V
OUT
I
D
I
L
I
D(Q2)
I
D(Q1)
I
L(Q2)
I
L(Q1)
Q2
Q1
VOUT
L1
L2
L1
MOSFET
Drain Current
Inductor
Current
I
D
I
L
MOSFET
Drain Current
Inductor
Current
I
LCMP
= Composite Inductor Current
I
D
0
0
0
0
ID(Q2)
ID(Q1)
IL(Q2)
IL(Q1)
I
LCMP
I
L
Interleaved Discontinuous Conduction Mode (DCM)
The well-known single-phase Discontinuous Conduction Mode
(DCM) technique achieves low switching noise because the drain
current increase starts at zero when a power MOSFET turns on,
and the rate of drain current increase is not steep, as shown by
the waveforms in Figure 1. However, the usable power level of
single-phase DCM is limited by the very high input / output ripple
currents that are generated.
The SSC2100 series provides two-phase interleaved DCM (see
Figure 2). This advanced technique incorporates two boost
converters working together to cancel input ripple currents and
to reduce output ripple currents. This result is based on a phase
difference of 180° between the two converters.
Interleaved DCM also achieves a PFC system with lower switch-
ing noise and smaller input filter footprint in comparison to
single-phase DCM. This is because reducing input / output ripple
currents increases the filtering effectiveness of the EMI filter and
also reduces switching noise.
Functional Description
Figure 1. External circuit and current waveforms for single-phase DCM
Figure 2. External circuit and current waveforms for two-phase interleaved DCM
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Startup Operation
VCC is the external power supply input to the SSC2100 IC. The
external circuit for the VCC terminal is shown in Figure 3.
When AC mains and VCC external voltage are applied, after the
VFB terminal voltage increases to VFB(OLDH) = 0.7 V (typ) or
more and the VCC terminal voltage increases to VCC(ON) = 11.6 V
(typ) or more, the control circuit starts switching operation.
Note: One of the startup conditions is that the input voltage must
reach 20% or more of the rated value for VOUT . This value of
VOUT is equivalent to approximately VFB(OLDH) = 0.7 V (typ).
When the VCC terminal voltage subsequently decreases to
VCC(OFF) = 10.6 V (typ) or less, the control circuit stops switch-
ing operation. It does so by enabling the UVLO (undervoltage
lockout) circuit, and then reverting to the standby mode that is the
state of the IC before startup.
When the VFB terminal voltage subsequently decreases to
V
FB(OLDL) = 0.5 V (typ) or less, the control circuit stops switching
operation and reverts to pre-startup standby mode, even if VCC
terminal voltage has increased to VCC(ON) or more.
Because the regulation range of the VCC internal circuit is very
wide, between VCC(OFF) = 11.4 V (max) and the VCC absolute
maximum rating of 30 V (max), a wide input voltage range
from the external power supply can be applied. The behaviors of
ICC during startup and when switching is stopped are shown in
Figure 4.
Soft Start Function
Soft start is adjusted by the external circuits on the VFB and
COMP terminals, as shown in Figure 5. At startup, when the
input voltage increases to approximately 20% of the rated out-
put voltage, VOUT , and the VCC terminal voltage increases to
VCC(ON) = 11.6 V (typ), soft start operation begins.
As shown in Figure 6, during the soft start period, the COMP
terminal is charged by ICOMP(SO) = 30 A. In this way, the output
power increases gradually, reducing stress on the power devices.
Figure 4. Relationship of VCC and ICC at startup and stopping Figure 6. Soft Start operation
Figure 3. External circuit of VCC terminal
Figure 5. External circuits of VFB and COMP terminals
1 COMP
2 VIN
3 VFB
4 VCC
IS 8
OUT1 7
GND 6
OUT2 5
SSC2100
power supply
C6 C
f
ICC
V
CC
ICC(ON)
11 mA(typ)
ICC(OFF)
40 A(typ)
10.6 V(typ)
VCC(OFF)
11.6V(typ)
VCC(ON)
Startup
Stop
4
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Soft start period
Time
Time
Time
3.2 V
V
FB(REF)
3.5 V
V
CC
I
COMP
V
CC(ON)
11.6 V(typ)
I
COMP(SO)
㧙30ǴA
0
0
0
Constant voltage operation
VFB
V
OUT
=100%
90% of V
OUT
I
DS
(Q1,Q2)
External power supply
for VCC
0.7 V
Time
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Voltage Control Operation
A generic PFC circuit for implementing single-phase DCM is
shown in Figure 7. The circuit is composed of a boost induc-
tor (L1), a switching device (Q1), a rectifier diode (D2), and an
output capacitor (C2). A control circuit would monitor the C2
voltage and generate an error amplifier output signal to operate
Q1. When the control circuit detects an off-time at the L1 Zero
Current Detection (ZCD) winding, it turns on Q1 for a period
of time. When Q1 is later turned off, the energy stored in L1 is
transferred through D2 to C2. After all of the energy stored in L1
is transferred to C2, the control circuit would again turn on Q1,
repeating the process.
The SSC2100 series two-phase interleaved DCM uses the VIN
terminal to monitor the AC mains rectified input voltage, the
VFB terminal to monitor output voltage, and the COMP terminal
to monitor phase compensation. This IC internally generates the
on-time, tON , and off-time, tOFF , and it controls output voltage
using the voltage-mode control method. Thus, a PFC system used
with this IC has no requirement for an auxiliary winding to detect
zero crossings of the inductor current. This allows simple circuits
with few external components.
In the boost PFC converter, tON is a function of load power and
tOFF is a function of both the input voltage, EIN , and the rated
output voltage, VOUT
. The relationship between tON and tOFF is
given by the following:
tOFF
×
tON
>
E
IN
VOUT – E
IN
(1)
The VIN terminal voltage is monitored internally and used to cal-
culate the internal tOFF . The typical relationship between tON and
the VIN terminal voltage, VIN , is shown in Figure 8. The maxi-
mum tON occurs at VIN = 0 V. The values shown assume VCOMP =
4 V , where VCOMP is the COMP terminal voltage.
As shown in Figure 9, the rectified input voltage is divided by
R1 and R2, and input to the VIN terminal. The output voltage is
divided by R3 and R4, and input to the VFB terminal. Because of
the way in which the VIN terminal voltage and the VFB termi-
nal voltage are used for internal calculations, the two dividers
should be well matched. Thus, the R1, R2, and C7 values of the
input portion should be equal to the R3, R4, and C8 values of the
output portion.
R1 is recommended to be a high-value resistor, in the range from
several hundred k to several M, ±1% tolerance, and of an
anti-electromigration type, such as metal oxide film.
C8, if necessary to reduce high frequency noise, is recommended
to have a capacitance of in the range of 0.1 to 10 nF.
Figure 8. Typical relationship between VIN and tON
Figure 7. PFC circuit with generic single-phase DCM
8
9
10
11
12
13
14
15
16
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VIN terminal voltage, V
IN
(V)
On-Time, t
ON
(μs)
.
3
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High Speed Response Function (HSR)
The boost PFC converter is supplied by an AC sinusoidal wave-
form at the local commercial mains input voltage and frequency.
However, the IC voltage control circuit, described above, char-
acteristically responds at a relatively slow rate. As a result, the
dynamic load response of the IC would be slow, and could cause
the output voltage to drop too quickly.
The innovative built-in High Speed Response (HSR) function
reduces variation of the output voltage under dynamic load
change conditions. As shown in Figure 10, when the VFB termi-
nal voltage increases to VFB(HSR)enable = 3.4 V (typ) or more, the
control circuit enables the HSR operation. If the VFB terminal
voltage subsequently decreases to VFB(HSR)active = 3.2 V (typ) or
less, whether due to dynamic load change or other conditions, the
control circuit activates the HSR operation.
When HSR is in active operation, the COMP terminal charges
by ICOMP(SOHSR) = 100 A (typ) and the output power increases
until the COMP terminal voltage increases to 3.2 V (typ).
VFB(HSR)active = 3.2 V (typ) is equivalent to approximately 91.4%
of the rated output voltage, VOUT
.
Figure 9. External circuits for VIN and VFB terminals
Figure 10. VFB terminal voltage waveforms
4
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3
4
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L2
L1
SS CV LC CV OV CV
Time
3.2 V
3.4 V
3.5 V
VFB HSR enable
HSR active
HSR OFF
HSR
3.72 V
3.68 V
3.2 V
OUT1,OUT2 Low
COMP Sink
Time
ICOMP
0
0
ICOMP(SK)
100Ǵ
A
ICOMP(SO) 㧙30Ǵ
A
ICOMP(SOHSR)㧙100Ǵ
A
SS : Soft start period
CV : Constant voltage operation period
LC : Dynamic load change period
HSR: High speed response operation period
OV : Overvoltage operation period
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Gate Drive
The OUT1 and OUT2 terminals each directly drive an external
power MOSFET. Currents and voltages are set as follows:
Peak Current Gate Voltage
Source Sink Low High
–0.5 A (typ) 0.5 A (typ) 0.3 V (max) 10.2 V (typ)
Resistors R7, R8, R9, and R10 in Figure 11 should be selected
for performance in the actual application, because these values
relate to the individual board layout patterns and power MOSFET
capacities. The gate resistors, R7 and R8, are recommended to
be in the range of several ohms to several tens of ohms, and
should be selected to reduce gate voltage ringing and EMI noise.
R9 and R10 help to prevent malfunctions caused by steep dV/dt
during power MOSFET turn-off. The recommended values are
in the 10 to 100 k range. These components should be placed
close to the gate and source terminals of the corresponding power
MOSFET.
Error Amplifier Phase Compensation
The phase compensation circuit is connected between the COMP
and GND terminals, as shown in Figure 12. The COMP terminal
is the output of the internal Error Amplifier. The Error Ampli-
fier circuit, which implements the enhanced response functions,
consists of a transconductance amplifier and switched current
sources. The Error Amplifier response is set below 20 Hz to
maintain power factor correction at standard commercial power
frequencies of 50 or 60 Hz.
The phase compensation components, C4, C5, and R11 (see
Figure 12), have typical recommended values shown below, but
should be selected for performance in the application: to reduce
ripple, or to enhance transient load response at the rated output
voltage.
• C4: 0.047 to 0.47 F
• C5: 0.47 to 10 F
• R11: 10 to 100 k
Thermal Shutdown Protection (TSD)
When the temperature of the IC increases to TJTSDH =
150°C (min) or more, the control circuit stops switching opera-
tion. Conversely, when temperature decreases to TJTSDL = 140°C
or less, the control circuit restarts switching operation. The hys-
teresis of the detection temperature, TJTSDHYS, is 10°C (typ).
Figure 12. Phase compensation circuit (external COMP terminal circuit)
Figure 11. External circuits for OUTx terminals
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L2
L1
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Overcurrent Protection (OCP)
The inductor current of both inductors is monitored by the detec-
tion resistor, R5, and is input to the IS terminal, as shown in
Figure 13.
The overcurrent protection function has two stages, IS Lower
OCP, and IS Upper OCP, described below.
IS Lower Overcurrent Protection, VIS(OCPL) When the
inductor current is increasing and if the IS terminal voltage
decreases to VIS(OCPL) = 0.42 V (typ), the control circuit lim-
its the output power by turning off either one or both power
MOSFETs, according to the output states of both OUT1 and
OUT2, as follows:
• If either one of OUT1 or OUT2 is high when the fault occurs,
that output is now set low (so both outputs are off). Figure 14 is
an example. Where the IS terminal voltage falls to VIS(OCPL) or
lower while OUT1 is high (Q1 is ON) and OUT2 is low, under
this condition, OUT1 is set to low.
• If both OUT1 and OUT2 are high when the fault occurs, the
output that went high earlier than the other output (considering
the current pulses only) is now set low (the other output remains
high). Figure 15 is an example where both OUT1 and OUT2 are
high (Q1 and Q2 are on), and the IS terminal detects VIS(OCPL) or
lower. Under this condition, because OUT1 was set high before
OUT2 was, OUT1 is now set low (and OUT2 remains high).
R5 (see Figure 13) should be selected for performance in the
actual application, such that IS terminal voltage reaches VIS(OCPL)
or lower under the conditions of minimum input voltage and peak
load.
Figure 16. Phase compensation circuit (external COMP terminal circuit)
Figure 15. VIS(OCPL) operation waveform after both OUT1 and OUT2 are
set to high
Figure 14. VIS(OCPL) operation waveform after OUT1 is set to high
and OUT2 is set to low
Figure 13. External circuits for IS and OUTx terminals
D2
D3
Q1
Q2
R5
RC1
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R6
SSC2100
Inductor current I
L
R7
R8
R9R10
E
IN
V
OUT
L2
L1
MOSFET(Q1)
Drain current
OUT1
terminal
MOSFET(Q2)
Drain current
OUT2
terminal
IS
terminal
OUT1 is set to low
after detecting V
IS(OCPL)
V
IS(OCPL)
㧙0.42V(TYP)
Q1= OFF
MOSFET(Q1)
Drain current
OUT1
terminal
MOSFET(Q2)
Drain current
OUT2
terminal
V
IS(OCPL)
㧙0.42V(TYP)
IS
terminal
When both OUT1and OUT2 are set to high,
OUT1 which is set to high ahead is set to low
Q1:OFF
MOSFET(Q1)
Drain current
OUT1
terminal
MOSFET(Q2)
Drain current
OUT2
terminal
V
IS(OCPH)
㧙0.55V(TYP)
Both OUT1 and OUT2
are set to low after
detecting V
IS(OCPH)
IS
terminal
Abnormal state, such as
inductor is shorted
or is saturated
11
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R6 is a damping resistor, which buffers IS terminal current
against surge currents, such as inrush currents. It is recommended
to have a value of 100 .
C3, if necessary to reduce high frequency noise, is recommended
to have a capacitance of in the range of 0.1 to 10 nF.
IS Upper Overcurrent Protection, VIS(OCPH) If the IS termi-
nal voltage decreases to VIS(OCPH) = 0.55 V (typ) or lower, the
control circuit limits the output power on a pulse-by-pulse basis
by setting both OUT1 and OUT2 low, which turns off both power
MOSFETs. This is shown in Figure 16. This protection function
operates under abnormal conditions such as when an inductor is
shorted or is saturated.
Overvoltage Protection (OVP)
The overvoltage protection function has two stages, Soft OVP,
and OVP, illustrated in Figure 17 and described below.
VFB Output Soft Overvoltage Protection, VFB(SOVP) When
VFB terminal voltage increases to VFB(SOVP) = 3.68 V (typ), Soft
Overvoltage Protection is activated. This discharges the COMP
terminal by ICOMP(SK) = 100 A (typ) and the output voltage is
decreased. VFB(SOVP) = 3.68 V (typ) is equivalent to about 105%
of the rated output voltage, VOUT
.
The output voltage threshold that initiates Soft Overvoltage Pro-
tection, is calculated approximately as follows:
VOUT(SOVP)
×
VFB(SOVP)
VOUT(norm)
VFB(REF)
(2)
where VOUT(norm) is VOUT under normal operating conditions, and
VFB(REF) is the Error Amplifier reference voltage, 3.5V (typ).
VFB Output Overvoltage Protection, VFB(OVP) When the
VFB terminal voltage increases to VFB(OVP) = 3.72 V (typ), both
OUT1 and OUT2 are set low on a pulse-by-pulse basis, which
stops the output supply by turning off the power MOSFETS.
When VFB terminal voltage decreases to VFB(SOVP)
, the control
circuit stops discharging from the COMP terminal and restores
switching operation.
The output voltage threshold that initiates Overvoltage Protec-
tion, is calculated approximately as follows:
VOUT(OVP)
×
VFB(OVP)
VOUT(norm)
VFB(REF)
(3)
where VOUT(norm) is VOUT under normal operating conditions, and
VFB(REF) is the Error Amplifier reference voltage, 3.5V (typ).
R3 is recommended to be a high-value resistor, in the range from
several hundred k to several M, ±1% tolerance, and of an
anti-electromigration type, such as metal oxide film.
C8 is recommended if necessary to reduce high frequency noise,
and should have a rating of 0.1 to 10 nF.
Open Loop Detection (OLD)
In the event that the output voltage detection resistor, R3 (see
Figure 18), opens and VFB terminal voltage decreases to
VFB(OLDL) = 0.5 V (typ) or less, the control circuit stops the
switching operation and enters standby mode. VFB(OLDL) =
0.5 V (typ) is equivalent to about 14.3% of the rated output volt-
age, VOUT .
When the VFB terminal voltage subsequently increases to
VFB(OLDH) = 0.7 V (typ) or more, the control circuit restores
switching operation. VFB(OLDH) = 0.7 V (typ) is equivalent to
about 20% of the rated output voltage, VOUT .
Figure 17. Overvoltage operation waveform and external circuit
CV OV
Time
3.50 V(typ)
VFB terminal
voltage
3.72 V(typ)
3.68 V(typ)
OUT1,OUT2 is set to low
CV : Constant voltage operation period
Time
COMP terminal
current
0
100Ǵ
A(typ )
CV
V
FB(OVP)
V
FB(SOVP)
106% of V
OUT
105% of V
OUT
V
OUT
=100%
OV : Overvoltage operation period
V
FB(REF)
I
COMP(SK)
4
%
%1/2
8+0
8($
8%%
+5
176
)0&
176
55%
4
4
% %%
Ǵ#
8
176
12
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115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
25501.04
Open Terminal Protection (OTP)
The VFB, IS, and VIN terminals each have dedicated internal
Open Terminal Protection functions.
VFB Open Protection The VFB terminal is internally con-
nected with a pull-up current source. In the event that the VFB
terminal is open, VFB terminal voltage is pulled-up to the inter-
nal supply voltage, the IC overvoltage protection is activated, and
both OUT1 and OUT2 are set low, decreasing the output voltage.
IS Open Protection The IS terminal is internally connected
with a pull-up current source. In the event that the IS terminal is
open, the IS terminal voltage is pulled-up to the internal sup-
ply voltage, the IC overcurrent protection is activated, and both
OUT1 and OUT2 are set low, decreasing the output voltage.
VIN Open Protection The VIN terminal is internally connected
with a pull-up current source. In the event that the VIN terminal
is open, the VIN terminal voltage is pulled-up to the internal sup-
ply voltage, and the control circuit limits IC operation or stops it.
Figure 18. External VFB terminal circuit
Figure 18. Typical application diagram
4
4
&
&
3
3
4
4%
4
4
%
%
%1/2
8+0
8($
8%%
+5
176
)0&
176
55%
4
4
% %
'
+0
8
176
L2
L1
EMI
Filter
85 to
264 VAC
GND
IS
OUT2
OUT1
VIN COMP
VFB
VCC
VOUT
R1
R2
R3
R4
L1
L2
D1
D2
D3
Q1
Q2
C2
C4
R5
R6
RC1
R7
R8
C3
SSC2100
C1
7
5
21
3
4
68
External
power
supply
GND
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1.508.853.5000; www.allegromicro.com
25501.04
Package Outline Drawing
A. Type number (abbreviation): SC21xx
Branding:
B. Lot number
1st letter: Last digit of year
2nd letter: Month
1 to 9 for January to September
O for October
N for November
D for December
3rd letter: Week
1 for dates 1 through 10
2 for dates 11 through 20
3 for dates 21 through 31
C. Sanken tracking number
Dimensions in mm
10º
0º
5.2 ±0.3
0.4 ±0.1
0.15 +0.1
–0.05
1.5 ±0.1
0.05 ±0.05
0.4 ±0.2
0.695 TYP
4.4 ±0.2 6.2 ±0.3
1.27 ±0.05
0.10
0.12 M
21
8
A
B
C
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Allegro MicroSystems, Inc.
115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
25501.04
Handling and Use Cautions and Warnings
Because reliability can be affected adversely by improper storage environments and handling methods during characteristic tests, please observe the
following cautions.
Cautions for Storage
• Ensure that storage conditions comply with standard temperature (5°C to 35°C) and standard relative humidity (around 40% to 75%) and avoid storage
locations that experience extreme changes in temperature or humidity.
• Avoid locations where dust or harmful gases are present, and avoid direct sunlight.
• Reinspect for rust on leads and solderability of devices which have been stored for a long time.
Cautions for Characteristic Tests and Handling
• When characteristic tests are carried out during inspection testing and other standard test periods, protect the devices from power surges from the test
equipment, and from shorts between the devices and the heatsink.
Recommended Operating Temperature
• Internal leadframe temperature in operation: TF = 115°C (max). Note: Measure at pin 5, close the case molding.
Soldering
• When soldering the devices, please be sure to minimize the working time, and stay within the following conditions:
260 (+0 / –10) °C for 10 s (during reflow )
350 ±5 °C for 3 s (using a soldering iron )
Considerations to protect the Products from Electrostatic Discharge
• When handling the devices, the operator must be grounded. Grounded wrist straps should be worn, and have at least 1 M of resistance from
operators to ground to prevent shock hazard.
• Workbenches where the devices are handled should be grounded and be provided with conductive table and floor mats.
• When using measuring equipment such as a curve tracer, the equipment also should be grounded.
• When soldering the devices, the head of the soldering iron or the solder bath must be grounded in order to prevent leakage voltage generated by them
from being applied to the devices.
• The devices should always be stored and transported in Sanken shipping containers or conductive containers, or be wrapped up in aluminum foil.
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Allegro MicroSystems, Inc.
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1.508.853.5000; www.allegromicro.com
25501.04
The contents in this document are subject to change, for improvement and other purposes, without notice.
Make sure that this is the latest version of the document before use.
The operation and circuit examples in this document are provided for reference purposes only. Sanken and Allegro MicroSystems assume no liabil-
ity for violation of industrial property, intellectual property, or other rights of Sanken or Allegro or third parties, that stem from these examples.
The user must take responsibility for considering and determining which devices the products described in this document are used with.
Although Sanken will continue to improve the quality and reliability of its products, semiconductor products, by their nature, have certain fault and
failure rates. The user must take responsibility for designing and checking to secure the product and system so that a product failure may not lead to
human injury, fire, damage, or other losses.
The products described in this document are intended for use in normal electronic devices (such as home appliances, office equipment, communi-
cation terminals, or measurement equipment).
If you are considering using Sanken’s products in a device that requires high reliability (such as transport machines and their control units, traffic
light control systems, disaster prevention and security equipment, or any kind of safety equipment), make sure that you consult a Sanken sales repre-
sentative.
Do not use these products in devices that require extremely high reliability (such as aerospace instruments, nuclear power control units, or life sup-
port systems), without Sanken’s written consent.
The products described in this document are not designed to be radiation-proof.
The contents in this document must not be transcribed or copied without Sanken’s written consent.
This is notification that you, as purchaser of the products/technology, are not allowed to perform any of the following:
1. Resell or retransfer these products/technology to any party intending to disturb international peace and security.
2. Use these products/technology yourself for activities disturbing international peace and security.
3. Allow any other party to use these products/technology for activities disturbing international peace and security.
Also, as purchaser of these products/technology, you agree to follow the procedures for the export or transfer of these products/
technology, under the Foreign Exchange and Foreign Trade Law of Japan, when you export or transfer the products/technology
abroad.
Copyright © 2008-2010 Allegro MicroSystems, Inc.
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Allegro MicroSystems, Inc.
115 Northeast Cutoff
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25501.04
Asia-Pacific
China
Sanken Electric Hong Kong Co., Ltd.
Suite 1026, Ocean Centre
Canton Road, Tsimshatsui
Kowloon, Hong Kong
Tel: 852-2735-5262, Fax: 852-2735-5494
Sanken Electric (Shanghai) Co., Ltd.
Room 3202, Maxdo Centre
Xingyi Road 8, Changning District
Shanghai, China
Tel: 86-21-5208-1177, Fax: 86-21-5208-1757
Sanken Electric (Shanghai) Co., Ltd.
Shenzhen Office
Room 1013, Xinhua Insurance Building
Mintian Road, Futian District
Shenzhen City, Guangdong, China
Tel: 86-755-3391-9356/9358, Fax: 86-755-3391-9368
Taiwan Sanken Electric Co., Ltd.
Room 1801, 18th Floor
88 Jung Shiau East Road, Sec. 2
Taipei 100, Taiwan R.O.C.
Tel: 886-2-2356-8161, Fax: 886-2-2356-8261
Japan
Sanken Electric Co., Ltd.
Overseas Sales Headquarters
Metropolitan Plaza Building
1-11-1 Nishi-Ikebukuro, Toshima-ku
Tokyo 171-0021, Japan
Tel: 81-3-3986-6164, Fax: 81-3-3986-8637
Korea
Sanken Electric Korea Co., Ltd.
Samsung Life Yeouido Building 16F
23-10, Yeouido-Dong, Yeongdeungpo-gu
Seoul 150-734, Korea
Tel: 82-2-714-3700, Fax: 82-2-3272-2145
Singapore
Sanken Electric Singapore Pte. Ltd.
152 Beach Road, #10-06 The Gateway East
Singapore 189721
Tel: 65-6291-4755, Fax: 65-6297-1744
Europe
Sanken Power Systems (UK) Limited
Pencoed Technology Park
Pencoed, Bridgend CF35 5HY, United Kingdom
Tel: 44-1656-869-100, Fax: 44-1656-869-162
North America
United States
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01606, U.S.A.
Tel: 1-508-853-5000, Fax: 1-508-853-7895
Allegro MicroSystems, Inc.
14 Hughes Street, Suite B105
Irvine, California 92618, U.S.A.
Tel: 1-949-460-2003, Fax: 1-949-460-7837
Worldwide Contacts
