Semiconductor Components Industries, LLC, 2003
May, 2003 - Rev. 0 1Publication Order Number:
NCP5201DEMO/D
NCP5201DEMO/D
Demonstration Board
Manual for the NCP5201
Purpose of this Document
This document presents the results of testing on the
NCP5201 demonstration board, including electrical
waveforms, power and efficiency charts and thermal data.
Key Features of the NCP5201
•Incorporates VDDQ, VTT Regulators
•Internal Switching Standby Regulator for VDDQ
•All External Power MOSFETs are N-Channel
•Adjustable VDDQ
•VTT Tracks VDDQ/2
•Fixed Switching frequency of 250kHz for VDDQ in
Normal Mode
•Doubled Switching Frequency (500kHz) for Standby
Mode
•Softstart Protection for VDDQ
•Undervoltage Monitor
•Short-Circuit Protection for both VDDQ and VTT
•Thermal Shutdown
•Housed in 5X6 QFN-18
Figure 1. NCP5201 Demonstration Board
DEMONSTRATION BOARD
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Figure 2. Schematic of NCP5201 Demonstration Board
R8
0
L1
1.7u H
VDDQ =2. 5V/15A
R1
2K
R2
910
R1 0
20K
R1 1
2.2
C1 3
150n F
C1 5
6.8n FC1 6
10n F
Q1
NTD60N 03
Q2
NTD60N 03
Q3
NTD60N 03
R5
10k*
R6
62K
R7
4.7
C4
4.7u FC6
3300u F
6.3V
C1
1u FC2
1000u F
10V
C3
470u F
10V
T1 VT T
T2 GND
VT T
T4 VDDQ
T3 GND
C9
470u F
10V
R9
4.7
L2
1.0u H
C1 7
1800u F
10V
R1 2
2K
JP 2
FBDDQ
CO MP
T9
GND
C8
330u F
25V
T7
VS TBY
R4
10K
C1 1
0.1u FC1 0
22n F
R3
100K
C1 4
1u F
VDDQ
VS TBY
C1 8
0.1u F*
2
31
JP 4
GNDSENS ESEL
VT T_GND
VOUT _GND
T5
PW RG DPW R GD
VT T_GND
VOUT _GND
S3_E N
11
12V
16
VS TBY
4
PW R G D
10
OC DDQ 7
TGDDQ 15
SDDQ 13
BGDDQ 14
CO MP 17
FBDDQ 1
AGND
12
VDDQ 8
VT T5
FB VT T 2
PGND 3
VT T6
SS
18
U1
NC P 5201- QFN 1 8
J1
T1 0
BF _CU T
C1 9
0.1u FC2 0
0.1u F C2 1
0.1u F C2 2
0.1u F C2 3
0.1u F C2 4
0.1u F C2 5
0.1u F C2 6
0.1u F C2 7
0.1u F C2 8
0.1u F C2 9
0.1u F C3 0
0.1u F C3 1
0.1u F C3 2
0.1u F C3 3
0.1u F C3 4
0.1u F C3 5
0.1u F C3 6
0.1u F C3 7
0.1u F C3 8
0.1u F C3 9
0.1u F C4 0
0.1u F C4 1
0.1u F C4 2
0.1u F C4 3
0.1u F
C4 4
0.1u FC4 5
0.1u F C4 6
0.1u F C4 7
0.1u F C4 8
0.1u F C4 9
0.1u F C5 0
0.1u F C5 1
0.1u F C5 2
0.1u F C5 3
0.1u F C5 4
0.1u F C5 5
0.1u F C5 6
0.1u F C5 7
0.1u F C5 8
0.1u F C5 9
0.1u F C6 0
0.1u F C6 1
0.1u F C6 2
0.1u F C6 3
0.1u F C6 4
0.1u F C6 5
0.1u F C6 6
0.1u F C6 7
0.1u F C6 8
0.1u F
C6 9
0.1u FC7 0
0.1u F C7 1
0.1u F C7 2
0.1u F C7 3
0.1u F C7 4
0.1u F C7 5
0.1u F C7 6
0.1u F C7 7
0.1u F C7 8
0.1u F C7 9
0.1u F C8 0
0.1u F C8 1
0.1u F C8 2
0.1u F C8 3
0.1u F C8 4
0.1u F C8 5
0.1u F C8 6
0.1u F C8 7
0.1u F C8 8
0.1u F C8 9
0.1u F C9 0
0.1u F C9 1
0.1u F C9 2
0.1u F C9 3
0.1u F
C9 4
0.1u FC9 5
0.1u F C9 6
0.1u F C9 7
0.1u F C9 8
0.1u F C9 9
0.1u F C 100
0.1u F C101
0.1u F C 102
0.1u F C 103
0.1u F C104
0.1u F C 105
0.1u F C106
0.1u F C107
0.1u F C 108
0.1u F C109
0.1u F C110
0.1u F C 111
0.1u F C112
0.1u F C113
0.1u F C114
0.1u F C115
0.1u F C116
0.1u F C117
0.1u F C118
0.1u F
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
JP 4
+5 V
+5 V
PS _ON
C119
0.1u F
+5 V
+12V
+12V
S3_E N
S3_E N
+5 V
+5 V
VS TBY
C120
1u F
C1 2
1u F
Q4
MGSF1N02ELT1
*
R1 3
4.7
R1 4
4.7
*
T8
NC H_ L
NOT E:
1. InstallR13 ifblocking FET isdriven by TGDDQ.
2. Install Q4, R5 if block ing FET is drvien by 12V CC with quick pull- dow ninS3.
3. Install R14 if block ing FET is driven by ex ter nal signal NCH _L.
4. (*) denotes optiona litem s.
C 121
1u F *
C123
4.7u FC122
4.7u F
DQ[0..63]
DM [0..7]
M AA [0..12]
MA B[ 1..5 ]
DQS [0..7]
VT T
RES TER MINATION
RES TERMINAT ION. sch
VDDQ
M AA [0..12]
D M [0..7]
DQS [0..7]
MA B[ 1 ..5 ]
DQ [0..63]
DI MM
DIMM.s ch
************************
************************
*****
******
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
**
**
*
*
*
*
**
*
*
*
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Table 1. BOM
Item Qty Designators Part Description Mfg. & P/N
1 3 C1, C14, C120 Ceramic, 1.0uF/16V 0805 Panasonic ECJ2FB1C105K
2 1 C2 Aluminum Electrolytic, 1000uF/10V Panasonic EEUFJ1A102
3 3 C3, C9 Aluminum Electrolytic, 470uF/6.3V Panasonic EEUFJ1A471
4 4 C4, C122, C123 Ceramic, 4.7uF/6.3V 1206 Panasonic ECJ3YB0J475K
5 1 C6 Aluminum Electrolytic, 3300uF/6.3V Panasonic EEUFJ0J332U
6 1 C8 Aluminum Electrolytic, 330uF/25V Rubycon 25JXA330MCA10x12.5/
Panasonic EEUFJ1E331
7 1 C10 Ceramic, 22nF/25V 0603 Panasonic ECJ1VB1E223K
8 3 C11, C119 Ceramic, 100nF/16V 0603 Panasonic ECJ1VB1C104K
9 1 C12 Ceramic, 1.0uF/16V 1206 Panasonic ECJ3FB1C105K
10 1 C13 Ceramic, 150nF/16V 0603 Panasonic ECJ1VB1C154K
11 1 C15 Ceramic, 6.8nF/50V 0603 Panasonic ECJ1VB1H682K
12 1 C16 Ceramic, 10nF/50V 0603 Panasonic ECJ1VB1H103K
13 1 C17 Aluminum Electrolytic, 1800uF/10V Nichicon UHM1A182MPT
14 2 JP1, JP3 3-Pin Jumper
15 1 JP2 2-Pin Jumper
16 1 JP4 ATX Connector Female
17 2 JP5, JP6 DDR DIMM Socket Foxconn AT09211-D7
18 1 L1 Inductor, 1.7uH/20A Core: MICROMETALS T44-52;
Wire: 1.27mm, 7 Turns
Pulse: PA0689 L1
Pulse Engineering Inc.
19 1 L2 Inductor, 1.0uH/20A Core: MICROMETALS T44-52;
Wire: 1.27mm, 5 Turns
Pulse: PA0690 L2
Pulse Engineering Inc.
20 3 Q1, Q2, Q3 N-Channel DPAK MOSFET, 30V/60A ON Semiconductor NTD60N03
21 2 R1, R12 Resistor, 2 kΩ 1% 0603 Panasonic ERJ3EKF2001V
22 1 R2 Resistor, 910 Ω 1% 0603 Panasonic ERJ3EKF9100V
23 1 R3 Resistor, 100 kΩ 5% 0603 Panasonic ERJ3GEYJ104V
24 1 R4 Resistor, 10 kΩ 5% 0603 Panasonic ERJ3GEYJ103V
25 1 R6 Resistor, 62 kΩ 1% 0603 Panasonic ERJ3EKF6202V
26 3 R7, R9, R13 Resistor, 4.7 Ω 5% 0603 Panasonic ERJ3GEYJ4R7V
27 1 R8 Resistor, 0 Ω 5% 0603 Panasonic ERJ3GEY0R00V
28 1 R10 Resistor , 20 kΩ 1% 0603 Panasonic ERJ3EKF2002V
29 1 R11 Resistor, 2.2 Ω 5% 0603 Panasonic ERJ3GEYJ2R2V
30 1 S1 DIP Switch
31 1 U1 Dual Output DDR Power Controller ON Semiconductor NCP5201
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ELECTRICAL TEST RESULTS
Demo Board Jumpers and Switches
S1 is an eight-pole DIP switch located near the ATX
power connector. The switch nearest the ATX power
connector is labeled PS_ON. When this switch is closed,
pin 14 of the ATX power connector is pulled low and the
ATX power supply is enabled.
The next switch position on the DIP switch is marked
S3_EN. This switch grounds pin 11 (the S3 enable) of the
NCP5201 when it is closed.
JP1 is a three-pin header with a jumper that can be
selected to either provide a 100k pull up resistor to the S3
enable pin of the NCP5201 or connect the S3 enable pin to
a test point labeled BF_CUT through a 100k resistor. For
manual control of the S3 enable signal, JP1 should be
connected t o the VSTBY position. This allows the S3 enable
signal to be controlled by the S3_EN DIP switch.
If the S3 enable signal is controlled from an external
source, JP1 should be connected to the BF_CUT position
and the DIP switch labeled S3enable should be left open.
Another configuration option on the NCP5201 demo
board is the gate drive of the blocking FET. The purpose of
the blocking FET is to allow a current path from VCC(5V)
to the high side FET during S0, and to block a potential
reverse current path from VDDQ back to the VCC(5V) rail
during S3.
The demo board has component place holders on the PCB
to allow the gate of the blocking FET to be controlled by
TGDDQ or by the S3enable signal.
If resistor R13 is populated and R5 and Q4 are
unpopulated, then the blocking FET is controlled by the
TGDDQ signal. This configuration requires the fewest
components, but it increases the drive power required from
the NCP5201 since it increases the total gate charge on the
TGDDQ node.
If R5 and Q4 are populated and R13 removed, then the
S3enable signal drives the blocking FET. This configuration
provides the lowest losses and highest efficiency.
JP2 is a two-pin header that programs the VDDQ voltage.
If JP2 is open, the output voltage is set to 1.8V. If JP2 is
closed, the VDDQ is set to 2.5V.
JP4 is a three-pin header with a jumper that routes the
analog ground of the NCP5201 to either the VTT ground
output pin or to the VDDQ ground output pin.
It is recommended to route a non-current carrying copper
shape under the NCP5201 to provide protection from stray
electric fields. This analog ground copper shape (or trace)
should be connected to the motherboard ground at only one
point to prevent external ground current from flowing
through the analog ground shape. Pin 12 is the analog
ground pin of the NCP5201 and should be routed to this
analog ground shape.
The internal voltage reference of the NCP5201 is
referenced to pin 12. Therefore, by selecting the location of
the connection between the NCP5201 analog ground and the
motherboard ground plane, voltage drops in the ground
plane can be compensated for.
Mode Switching
S5 to S0 Normal Transition from OFF to ON
In this test the ATX power supply is enabled, simulating
a mode change from S5 to S0. The 12V rail from the ATX
power supply is observed as well as the VDDQ and VTT
output voltages from the NCP5201 demo board.
VTT
VDDQ
5 Fin
12 Fin
Figure 3. S5 to S0 Normal Transition from OFF to ON
No Load
VDDQ
VTT
5 Vin
12 Vin
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S0 to S3 Normal Transition from ON to STANDBY
The transition from S0 mode to the S3 mode is initiated by
asserting the S3_EN pin, while in the S0 mode. Asserting the
S3_EN pin will immediately cause the PWRGD output pin
to go to a logic low level, and immediately put the VTT
regulator into a high impedance mode. Figure 4 shows the
result of S3_EN going high during S0 mode. VTT shows an
RC decay (with a 100 ohm load to ground), PWRGD is
deasserted, and VDDQ does not change.
VTT
VDDQ
S3_EN
PWRGD
Figure 4. S3_EN Asserted During S0 Mode
Asserting the S3_EN pin will not immediately cause a
change in the operating mode of the VDDQ regulator, but it
will enable the VDDQ regulator to switch to the S3 mode
when either the pulse width goes to 100% (usually due to a
decay in the 5.0 V conversion rail) or the 12 Volt input
decays below the under voltage monitor threshold. Figure 5
shows the result of the 5.0 Vin rail decreasing, triggering a
change in the VDDQ regulator mode from S0 to S3.
5 Vin VDDQ
VComp
Figure 5. S0 to S3 Transition with the Decay of the
5.0 V Input as the Trigger
Figure 5 shows a fluctuation in the VDDQ output voltage
during the transition from S0 to the S3 mode. The output
voltage fluctuation is caused by the voltage feedback loop of
the VDDQ regulator changing the pulse width as the 5.0 V
VCC input voltage decays, and then changing again when
the conversion power source is switched from the 5.0 V
VCC rail to the 5.0 V standby rail. The following figure
shows the S0 to S3 transition, with the scales set to zoom in
on the event when the VDDQ regulator switches from the
5.0 V input to the 5.0 V standby power source.
VDDQ
VComp
5 Vin
Figure 6. S0 to S3 Transition with the Decay of the
5.0 V Input as the Trigger (Zoomed)
Figure 7 shows the S0 to S3 transition with the decay of
the 12 Volt input as the trigger. Since the pulse width does
not have to change when the power converter switches from
the 5.0 V Vcc rail to the 5.0 V standby rail, there is no
fluctuation in the VDDQ output voltage.
CH1 VDDQ with 2.6 V Off-
set
CH3 5 Vin
CH4 12 Vin
Figure 7. S0-S3 with Decreasing 12 V as the Trigger
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S3 to S0 Normal Transition from STANDBY to ON
Figure 8 shows the transition from S3 to S0 with the
S3_EN as the trigger. On a normal transition from S3 to S0
it is assumed that the 12 Volt and 5.0 V Vcc rails are in
regulation before S3_EN is deasserted. When S3_EN is
deasserted the VDDQ regulator will immediately switch to
the S0 mode and convert VDDQ power from the 5.0 V Vcc
rail instead of the 5.0 V Standby rail. When S3_EN is
deasserted the VTT regulator will be enabled, and the
PWRGD signal will be asserted when VDDQ and VTT are
in regulation.
CH1 VDDQ with 2.6 V Offset
CH2 VTT
CH3 PWRGD
CH4 S3_EN
Figure 8. S3-S0 with S3_EN as the Trigger
Undervoltage Detection
VCC (12V) Undervoltage Detection
In the SO mode the NCP5201 will turn off (disabling the
gate drive to the top and bottom MOSFETs) if the VCC
(12V) (pin 16) voltage goes below 9.2 volts. The NCP5201
will start when VCC (12V) goes above 10.5 volts. If the
S3_EN is asserted when the VCC (12V) voltage goes below
9.2 volts, then the NCP5201 will switch into the S3 mode.
VSTBY Undervoltage Detection
In the S3 mode the NCP5201 will turn off when the
VSTBY (pin 4) voltage goes below 4.3 volts.
Switching Waveforms
CH1 High-Side Fet Gate Voltage
CH2 Low-Side Fet Gate Voltage
Figure 9. High-Side/Low-Side FET Gate Voltage in
S0 Mode
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Figure 10. VDDQ Switch-Node During S0 with no Load and with Full Load
VDDQ Load = 0 A VDDQ Load = 15 A
VDDQ Load = 700 mA
VDDQ Load = 100 mA
Figure 11. VDDQ Switch-Node During S3
Voltage Regulation
VDDQ Static Voltage Regulation During S3
Figure 12 shows the effect of a static load current on the
VDDQ regulator during the S3 standby mode. During S3,
the peak inductor current is limited to 2.0 Amps
(ILIMstbpk). If the inductor current exceeds this value, the
high-side FET internal to the NCP5201 will turn off,
effectively reducing the duty cycle and the VDDQ voltage.
2.5
2.45
2.4
2.35
2.3
Figure 12. Static VDDQ Voltage vs.
VDDQ Load Current in S3
01
VOLTS
AMPS
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VDDQ Static Voltage Regulation During S3
1.3
1.25
1.2
1.15
Figure 13. VTT Voltage vs. Current
-2.5 0.5
VOLTS
AMPS
-1.5 -0.5 1.5 2.5
Power Requirements
Input Voltages
The NCP5201 demonstration board has a standard ATX
style power receptacle to provide simple means to provide
the required voltages. The board requires 5 Volts for the
VSTBY pin of the NCP5201 which is normally supplied by
the 5.0 Vstandby regulator from the ATX power supply.
When the demonstration board is in the S0 mode, 12 Volts
and 5 Volts are required in addition to the 5 Volt standby
voltage. All of these power supply voltages are normally
supplied by the ATX power supply.
Input Current
Input current requirements vary according to the
operating mode, the load current, the gate charge of FETs,
and the way the gate voltage of the blocking FET is
controlled. The following tables show current requirements
in the S0 mode.
Input Current Requirements with the Blocking FET
driven by 12V:
5 Volt
Standby 5 Volt Vcc 12 Volt
VDDQ
Current
3.0 mA 1.16 A 26 mA 2.0 A
3.0 mA 5.90 A 27 mA 10 A
Power Requirements with the Blocking FET driven by
TGDDQ:
5 Volt
Standby 5 Volt Vcc 12 Volt VDDQ
Current
3.0 mA 1.16 A 41 mA 2.0 A
3.0 mA 6.16 A 43 mA 10 A
The following chart shows the conversion efficiency of
the VDDQ regulator in S0 mode.
VDDQ CONVERTER EFFICIENCY
0
20
40
60
80
100
0 5 10 15
LOAD CURRENT (AMPS)
12 V
High-Side Gate Drive
Figure 14. VDDQ Conversion Efficiency in S0
Figure 14 shows the power conversion efficiency of the
VDDQ regulator from no load to full load. The efficiency
calculation includes the bias current required to operate the
NCP5201 as well as the input power from the 5.0 Volt
conversion rail.
In Standby or S3 mode the 12 Volt and 5.0 Volt Vcc rails
do not supply any power, all VDDQ current is converted
from the 5.0 V Standby rail. The following chart shows the
conversion efficiency for the VDDQ regulator in the S3
mode.
S3 CONVERSION EFFICIENCY
0
20
40
60
80
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4
VDDQ CURRENT
Figure 15. 5.0 V Standby to VDDQ Conversion
Efficiency in the S3 Mode
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VDDQ Over-Current Protection
The NCP5201 senses the voltage drop across the high side
FET to detect an over current event. The over current
threshold level is a function of the voltage on the OCDDQ
pin of the NCP5201 and the on resistance of the high-side
FET. A constant current source in the NCP5201, in
conjunction with the OCDDQ resistor sets a voltage trip
voltage level that is compared with the voltage on the switch
node. If the voltage on the switch node, during the on time
of the high-side FET, i s less then the voltage on the OCDDQ
pin, then the NCP5201 assumes an excessive voltage drop
across the high-side FET has occurred due to high FET
current. If an over current event is detected the NCP5201
turn off the high-side and low-side FETs, and will remain
latched off until the 5 Volt standby power is cycled.
The over current protection feature of the NCP5201 is not
intended to provide a precise current limit, but rather to
prevent catastrophic damage to the motherboard in the event
of a short circuit in the memory system.
The NCP5201 demonstration board has a VDDQ over
current threshold of about 40 Amps.
Figure 16 shows the effect of a 45A load being placed on
the VDDQ output terminals. Channel 1 is the VDDQ switch
node; channel 2 shows the VDDQ output voltage being
switched into a 45 A load. The over current event lasts about
2.2 msec until the NCP5201 latches off.
Figure 17 shows the VDDQ switch node, during startup
with a short on the VDDQ output. The NCP5201 detects an
over current event about 1.6 ms after the initial turn on.
CH1 VDDQ switch-node
CH2 Voltage on 45 Amp load
∆: 2.18 ms
∆: 2.16 ms
Figure 16. VDDQ Over Current Protection Tripping
with a 45 Amp Load
@: 40 µs
∆: 1.57 ms
Figure 17. VDDQ Switch Node during Startup into a
Short Circuit
Thermal Data
UNLOADED VDDQ Load 15 A
VTT Load 400 mA
Temperature / CTemperature Rise / CTemperature / CTemperature Rise / C
NCP5201 26.0 3.7 51.5 29.2
Blocking FET 27.5 5.2 60.8 38.5
TOP FET 28.4 6.1 60.6 38.3
BOTTOM FET 29.1 6.8 54.2 31.9
Input Inductor 27.9 5.6 45.7 23.4
Output Inductor 33.4 11.1 59.7 37.4
Input Capacitor 27.3 5.0 59.3 37.0
Output Capacitor 26.0 3.7 35.5 13.2
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Glue Logic
The NCP5201 was designed to meet an Intel requirement
for use on Intel motherboards that included the glue logic
chip (e.g. the Port Angeles super I/O chip) required to drive
the S3_EN pin directly. Motherboards that do not use the
glue logic chip may use different glue logic circuits to
generate the S3_EN signal.
The following circuit shows a proven method of deriving
the S3_EN signal. Both NCP5201 and the M/B are working
normally with the S3_EN signal from the circuit.
The SLP_S4# signal comes from the Intel chipset, and the
PWROK signal comes from the ATX power supply.
Figure 18. Method for Deriving the D3enable Signal
SLP_S4#
47 k
S3_EN
PWROK Q1 MGSF1N02ELT1/
2N7002
SOT23
The S leep_S4* a nd Sleep_S3* s ignals c ome f rom t he I ntel c hipset, a nd t he P owerOK s ignal c omes f rom t he ATX p ower s upply.
S3enable is asserted when Sleep_S3* remains
high and Sleep_S4 goes low.
Figure 19. S0-S3
S3enable is not deasserted until PowerOK from
the ATX power is asserted.
Figure 20. S3-S0
CH1 S3enable
CH2 Sleep_S4*
CH3 Sleep_S3*
CH4 ATX Power Good CH1 S3enable
CH2 Sleep_S4*
CH3 Sleep_S3*
CH4 ATX Power Good
CH1 S3enable
CH2 Sleep_S4*
CH3 Sleep_S3*
CH4 ATX Power Good
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During a transition to S4 or S5, Sleep_S3*
goes low, and S3enable is not asserted.
S3enable is deasserted when PowerOK from the ATX
power supply is asserted. S3enable being enabled for
Figure 21. S0-S4 and S0-S5 Figure 22. S4-S0 and S5-S0
a short time before the ATX power supply is in
regulation will not cause a problem.
CH1 S3enable
CH2 Sleep_S4*
CH3 Sleep_S3*
CH4 ATX Power Good
CH1 S3enable
CH2 Sleep_S4*
CH3 Sleep_S3*
CH4 ATX Power Good
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changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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