W681511IS - Nuvoton Technology Corp. America

Publication Release Date: April 2005

- 1 - Revision A10

W681511

SINGLE-CHANNEL VOICEBAND CODEC

Advanced Data Sheet

W681511

- 2 -

1. GENERAL DESCRIPTION

The W681511 is a general-purpose single channel PCM CODEC with pin-selectable μ-Law or A-Law

companding. The device is compliant with the ITU G.712 specification. It operates off of a single +5V

power supply and is available in 20-pin PDIP, SOG, SSOP, and TSSOP package options. Functions

performed include digitization and reconstruction of voice signals, and band limiting and smoothing

filters required for PCM systems. The filters are compliant with ITU G.712 specification. W681511

performance is specified over the industrial temperature range of –40°C to +85°C.

The W681511 includes an on-chip precision voltage reference and an additional power amplifier,

capable of driving 300Ω loads differentially up to a level of 6.3V peak-to-peak. The analog section is

fully differential, reducing noise and improving the power supply rejection ratio. The data transfer

protocol supports both long-frame and short-frame synchronous communications for PCM

applications, and IDL and GCI communications for ISDN applications. W681511 accepts seven

master clock rates between 256 kHz and 4.096 MHz, and an on-chip pre-scaler automatically

determines the division ratio for the required internal clock.

For fast evaluation and prototyping purposes, the W681511DK development kit is available.

2. FEATURES

• Single +5V power supply

• Typical power dissipation of 25 mW,

power-down mode of 0.5 μW

• Fully-differential analog circuit design

• On-chip precision reference of 1.575 V for

a 0 dBm TLP at 600 Ω

• Push-pull power amplifiers with external

gain adjustment with 300 Ω load capability

• Seven master clock rates of 256 kHz to

4.096 MHz

• Pin-selectable μ-Law and A-Law

companding (compliant with ITU G.711)

• CODEC A/D and D/A filtering compliant

with ITU G.712

• Industrial temperature range (–40°C to

+85°C)

• Package: 20-pin SOG

ApplIcations

• Digital Telephone Systems

• Central Office Equipment (Gateways,

Switches, Routers)

• PBX Systems (Gateways, Switches)

• PABX/SOHO Systems

• Local Loop card

• SOHO Routers

• VoIP Terminals

• Enterprise Phones

• ISDN Terminals

• Analog line cards

• Digital Voice Recorders

W681511

Publication Release Date: April 2005

- 3 - Revision A10

3. BLOCK DIAGRAM

256 kHz,

512 kHz,

1536 kHz,

1544 kHz,

2048 kHz,

2560 kHz

& 4096 kHz

MCLK 256 kHz

8 kHz

512 kHz

Pre - scaler

Power Conditioning

Voltag e reference V

PUI

G.712 CODEC

G.711

/A-Law

PAO+

PAO-

PAI

AI+

AI-

/A-Law

Tra

mit

Int

erf

ace

cei

Int

erf

ace

FST

BCLKT

PCMT

FSR

BCLKR

PCMR

REF

256 kHz,

512 kHz,

1536 kHz,

1544 kHz,

2048 kHz,

2560 kHz

& 4096 kHz

MCLK 256 kHz

8 kHz

Pre - Scaler

Power Conditioning

Voltag e reference V

G.712 CODEC

G.711

/A-Law RO+

/A-Law

G.712 CODEC

G.711

/A-Law

Transmit

PCM

Interface

Receive

PCM

Interface

BCLKT BCLKT

BCLKR

W681511

- 4 -

4. TABLE OF CONTENTS

1. GENERAL DESCRIPTION.................................................................................................................. 2

2. FEATURES ......................................................................................................................................... 2

3. BLOCK DIAGRAM .............................................................................................................................. 3

4. TABLE OF CONTENTS...................................................................................................................... 4

5. PIN CONFIGURATION....................................................................................................................... 6

6. PIN DESCRIPTION............................................................................................................................. 7

7. FUNCTIONAL DESCRIPTION............................................................................................................ 8

7.1. Transmit Path............................................................................................................................. 8

7.2. Receive Path.............................................................................................................................. 9

7.3. Power Management................................................................................................................. 10

7.3.1. Analog and Digital Supply..............................................................................................10

7.3.2. Analog Ground Reference Voltage Output.................................................................... 10

7.4. PCM Interface.......................................................................................................................... 10

7.4.1. Long Frame Sync........................................................................................................... 10

7.4.2. Short Frame Sync .......................................................................................................... 11

7.4.3. GCI Interface.................................................................................................................. 11

7.4.4. IDL Interface................................................................................................................... 12

7.4.5. System Timing................................................................................................................ 12

8. TIMING DIAGRAMS.......................................................................................................................... 13

9. ABSOLUTE MAXIMUM RATINGS....................................................................................................20

9.1. Absolute Maximum Ratings..................................................................................................... 20

9.2. Operating Conditions............................................................................................................... 20

10. ELECTRICAL CHARACTERISTICS............................................................................................... 21

10.1. General Parameters .............................................................................................................. 21

10.2. Analog Signal Level and Gain Parameters............................................................................ 22

10.3. Analog Distortion and Noise Parameters .............................................................................. 23

10.4. Analog Input and Output Amplifier Parameters..................................................................... 24

10.5. Digital I/O............................................................................................................................... 26

10.5.1. µ-Law Encode Decode Characteristics........................................................................ 26

10.5.2. A-Law Encode Decode Characteristics ....................................................................... 27

10.5.3. PCM Codes for Zero and Full Scale ............................................................................ 28

10.5.4. PCM Codes for 0dBm0 Output .................................................................................... 28

11. TYPICAL APPLICATION CIRCUIT.................................................................................................29

12. PACKAGE SPECIFICATION .......................................................................................................... 31

12.1. 20L SOG – 300mil ................................................................................................................. 31

W681511

Publication Release Date: April 2005

- 5 - Revision A10

13. ORDERING INFORMATION........................................................................................................... 32

14. VERSION HISTORY....................................................................................................................... 33

W681511

- 6 -

5. PIN CONFIGURATION

SINGLE

CHANNEL

CODEC

SOG

RO+

PAI

PAO-

PAO+

FSR

PCMR

BCLKR

PUI

AI+

A I-

FST

PCMT

BCLKT

MCLK

SINGLE

CHANNEL

CODEC

FSR

BCLKR

/A-Law

BCLKT

MCLK

W681511

Publication Release Date: April 2005

- 7 - Revision A10

6. PIN DESCRIPTION

Name Pin

No. Functionality

RO+ 1

Non-inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to

1.575 volt peak referenced to the analog ground level.

NC 2 Not connected.

PAI 3 This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage.

PAO- 4 Inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak referenced

to the VAG voltage level.

PAO+ 5 Non-inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak

referenced to the VAG voltage level.

VDD 6 Power supply. This pin should be decoupled to VSS with a 0.1μF ceramic capacitor.

FSR 7 8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or

channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit

and receive are synchronous operations.

PCMR 8 PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.

BCLKR 9 PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is

selected when this pin is tied to VSS. The IDL mode is selected when this pin is tied to VDD.

This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.

PUI 10 Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VSS,

the part is powered down.

MCLK 11 System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544

kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better performance, it is recommended to have

the MCLK signal synchronous and aligned to the FST signal. This is a requirement in the

case of 256 and 512 kHz frequency.

BCLKT 12 PCM transmit bit clock input pin.

PCMT 13 PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.

FST 14 8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.

VSS 15 This is the supply ground. This pin should be connected to 0V.

μ/A-Law 16 Compander mode select pin. μ-Law companding is selected when this pin is tied to VDD. A-Law

companding is selected when this pin is tied to VSS.

AO 17 Analog output of the first gain stage in the transmit path.

AI- 18 Inverting input of the first gain stage in the transmit path.

AI+ 19 Non-inverting input of the first gain stage in the transmit path.

VAG 20 Mid-Supply analog ground pin, which supplies a 2.5 Volt reference voltage for all-analog signal

processing. This pin should be decoupled to VSS with a 0.01μF to 0.1 μF capacitor. This pin

becomes high impedance when the chip is powered down.

W681511

- 8 -

7. FUNCTIONAL DESCRIPTION

W681511 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC

complies with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a

complete μ-Law and A-Law compander. The μ-Law and A-Law companders are designed to comply

with the specifications of the ITU-T G.711 recommendation.

The block diagram in section 3 shows the main components of the W681511. The chip consists of a

PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats.

The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample

rate with the external frame sync frequency. The power conditioning block provides the internal

power supply for the digital and the analog section, while the voltage reference block provides a

precision analog ground voltage for the analog signal processing. The main CODEC block diagram

is shown in section 3.

PAO

Cont

Ant

Aliasi

Fil

Ant

Aliasi

Fil

200

High

Pas

Fil

oot

ilter

oot

Figure 7.1 The W681511 Signal Path

7.1. Transmit Path

The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain

setting (see application examples in section 11). The device has an input operational amplifier whose

output is the input to the encoder section. If the input amplifier is not required for operation it can be

powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or

the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The

input amplifier can be powered down by connecting the AI+ pin to VDD or VSS. The AO pin is selected

as an input when AI+ is tied to VDD and the AI- pin is selected as an input when AI+ is tied to VSS (see

Table 7.1).

Filter

PAI

+ -

Ant

Fil

Aliasing

Fil

Ant

Fil

High Pass

Fil

ter

oot

hin

Filter

Smoothing

Filter

Receive Path

Transmit Path

A +

ter

Converter

3400Hz

200Hz

W681511

Publication Release Date: April 2005

- 9 - Revision A10

AI+ Input Amplifier Input

VDD Powered Down AO

1.2 to VDD-1.2 Powered Up AI+, AI-

VSS Powered Down AI-

Table 7.1 Input Amplifier Modes of operation

When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the

analog ground voltage VAG.

The output of the input amplifier is fed through a low-pass filter to prevent aliasing at the switched

capacitor 3.4 kHz low pass filter. The 3.4 kHz switched capacitor low pass filter prevents aliasing of

input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is

filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the

recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is

digitized. The signal is converted into a compressed 8-bit digital representation with either μ-Law or A-

Law format. The μ-Law or A-Law format is pin-selectable through the μ/A-Law pin. The compression

format can be selected according to Table 7.2.

μ/A-Law Pin Format

VSS A-Law

VDD μ-Law

Table 7.2. Pin-selectable Compression Format

The digital 8-bit μ-Law or A-Law samples are fed to the PCM interface for serial transmission at the

sample rate supplied by the external frame sync FST.

7.2. Receive Path

The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and

converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed

through the pin-selectable μ-Law or A-Law expander and converted to analog samples. The mode of

expansion is selected by the μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a

low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification.

A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is

buffered to provide the receive output signal RO+. The RO+ output can be externally connected to the

PAI pin to provide a differential output with high driving capability at the PAO+ and PAO- pins. By

using external resistors (see section 11 for examples), various gain settings of this output amplifier

can be achieved. If the transmit power amplifier is not in use, it can be powered down by connecting

PAI to VDD.

W681511

- 10 -

7.3. POWER MANAGEMENT

7.3.1. Analog and Digital Supply

The power supply for the analog and digital parts of the W681511 must be 5V +/- 10%. This supply

voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 μF

ceramic capacitor.

7.3.2. Analog Ground Reference Voltage Outpt

The analog ground reference voltage is available for external reference at the VAG pin. This voltage

needs to be decoupled to VSS through a 0.01 μF ceramic capacitor.

7.4. PCM INTERFACE

The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received

through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of

operation of the interface are shown in Table 7.3.

BCLKR FSR Interface Mode

64 kHz to 4.096 MHz 8 kHz Long or Short Frame Sync

VSS VSS ISDN GCI with active channel B1

VSS VDD ISDN GCI with active channel B2

VDD VSS ISDN IDL with active channel B1

VDD VDD ISDN IDL with active channel B2

Table 7.3 PCM Interface mode selections

7.4.1. Long Frame Sync

The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the

BCLKR or BCLKT pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8

kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC

sample rate on the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when

the FST pin is held high for two consecutive falling edges of the bit-clock at the BCLKT pin. The length

of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge

occurs every 125 μsec. During data transmission in the Long Frame Sync mode, the transmit data pin

W681511

Publication Release Date: April 2005

- 11 - Revision A10

PCMT will become low impedance when the Frame Sync signal FST is high or when the 8 bit data

word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame

Sync signal FST becomes low while the data is transmitted or when half of the LSB is transmitted. The

internal decision logic will determine whether the next frame sync is a long or a short frame sync,

based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high

impedance for two frame sync cycles after every power down state. More detailed timing information

can be found in the interface timing section.

7.4.2. Short Frame Sync

The W681511 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is high

for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the

bit-clock, the W681511 starts clocking out the data on the PCMT pin, which will also change from high

to low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway

the LSB. The Short Frame Sync operation of the W681511 is based on an 8-bit data word. When

receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge

that coincides with the Frame Sync signal. The internal decision logic will determine whether the next

frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus

collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down

state. More detailed timing information can be found in the interface timing section.

7.4.3. General Circuit Interface (GCI)

The GCI interface mode is selected when the BCLKR pin is connected to VSS for two or more frame

sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface

consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects

channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data

clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK.

The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted

consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is

transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section.

W681511

- 12 -

7.4.4. Interchip Digital Link (IDL)

The IDL interface mode is selected when the BCLKR pin is connected to VDD for two or more frame

sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface

consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR

pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the

first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK

cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after

the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK

after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the

IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when

not used for data transmission and also in the time slot of the unused channel. For more timing

information, see the timing section.

7.4.5. System Timing

The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz

master clock rates. The system clock is supplied through the master clock input MCLK and can be

derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz and 8

kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency

versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is low for

the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the

W681511 will enter the low power standby mode. Another way to power down is to set the PUI pin to

low. When the system needs to be powered up again, the PUI pin needs to be set to high and the

Frame Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will

become low impedance.

W681511

Publication Release Date: April 2005

- 13 - Revision A10

8. TIMING DIAGRAMS

FST

BCLKT

D7 D6 D5 D4 D3 D2 D1PCMT

MSB LSB

THID TBCK

TBCKH TBCKL

TFS

TFTFH

TFTRS

TFTRH

THID

TBDTD

TFDTD

01 23 45 7 8 0 1

MSB LSB

FSR

BCLKR

TBCK

D6 D5 D4 D3 D2 D1 D0PCMR D7

TDRH

TDRS

TBCKH TBCKL

TFS

TFRFH

TFRRS

TFRRH

01 23 45 67 8 0 1

MCLK

TFTRHM TFTRSM TMCKH TMCKL

TMCK

TRISE TFALL

TFSL

Figure 8.1 Long Frame Sync PCM Timing

W681511

- 14 -

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TFS FST, FSR Frequency --- 8 --- kHz

TFSL FST / FSR Minimum Low Width 1TBCK sec

1/TBCK BCLKT, BCLKR Frequency 64 --- 4096 kHz

TBCKH BCLKT, BCLKR High Pulse Width 50 --- --- ns

TBCKL BCLKT, BCLKR Low Pulse Width 50 --- --- ns

TFTRH BCLKT 0 Falling Edge to FST Rising

Edge Hold Time 20 --- --- ns

TFTRS FST Rising Edge to BCLKT 1 Falling

edge Setup Time 80 --- --- ns

TFTFH BCLKT 2 Falling Edge to FST Falling

Edge Hold Time 50 --- --- ns

TFDTD FST Rising Edge to Valid PCMT Delay

Time --- --- 60 ns

TBDTD BCLKT Rising Edge to Valid PCMT

Delay Time --- --- 60 ns

THID Delay Time from the Later of FST

Falling Edge, or

BCLKT 8 Falling Edge to PCMT Output

High Impedance

10 --- 60 ns

TFRRH BCLKR 0 Falling Edge to FSR Rising

Edge Hold Time 20 --- --- ns

TFRRS FSR Rising Edge to BCLKR 1 Falling

edge Setup Time 80 --- --- ns

TFRFH BCLKR 2 Falling Edge to FSR Falling

Edge Hold Time 50 --- --- ns

TDRS Valid PCMR to BCLKR Falling Edge

Setup Time 0 --- --- ns

TDRH PCMR Hold Time from BCLKR Falling

Edge 50 --- --- ns

Table 8.1 Long Frame Sync PCM Timing Parameters

1 TFSL must be at least ≥ TBCK

W681511

Publication Release Date: April 2005

- 15 - Revision A10

D7 D6 D5 D4 D3 D2 D1

MSB LSB

TBCK

TBCKH TBCKL

TFS

TFTRS

TFTRH

THID

TBDTD

01 2 3 45 6 7 8 01

FST

BCLKT

PCMT

TBDTD

TFTFH

-1

TFTFS

MSB LSB

TBCK

D6 D5 D4 D3 D2 D1 D0D7

TDRH

TDRS

TBCKH TBCKL

TFS

TFRRS

TFRRH

01 23 45 6 7 8 01

FSR

BCLKR

PCMR

TFRFH

-1

TFRFS

MCLK

TFTRHM TFTRSM TMCKH TMCKL

TMCK

TRISE TFALL

Figure 8.2 Short Frame Sync PCM Timing

W681511

- 16 -

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TFS FST, FSR Frequency --- 8 --- kHz

1/TBCK BCLKT, BCLKR Frequency 64 --- 4096 kHz

TBCKH BCLKT, BCLKR High Pulse Width 50 --- --- ns

TBCKL BCLKT, BCLKR Low Pulse Width 50 --- --- ns

TFTRH BCLKT –1 Falling Edge to FST Rising Edge Hold

Time 20 --- --- ns

TFTRS FST Rising Edge to BCLKT 0 Falling edge Setup

Time 80 --- --- ns

TFTFH BCLKT 0 Falling Edge to FST Falling Edge Hold Time 50 --- --- ns

TFTFS FST Falling Edge to BCLKT 1 Falling Edge Setup

Time 50 --- --- ns

TBDTD BCLKT Rising Edge to Valid PCMT Delay Time 10 --- 60 ns

THID Delay Time from BCLKT 8 Falling Edge to PCMT

Output High Impedance 10 --- 60 ns

TFRRH BCLKR –1 Falling Edge to FSR Rising Edge Hold

Time 20 --- --- ns

TFRRS FSR Rising Edge to BCLKR 0 Falling edge Setup

Time 80 --- --- ns

TFRFH BCLKR 0 Falling Edge to FSR Falling Edge Hold Time 50 --- --- ns

TFRFS FSR Falling Edge to BCLKR 1 Falling Edge Setup

Time 50 --- --- ns

TDRS Valid PCMR to BCLKR Falling Edge Setup Time 0 --- --- ns

TDRH PCMR Hold Time from BCLKR Falling Edge 50 --- --- ns

Table 8.2 Short Frame Sync PCM Timing Parameters

W681511

Publication Release Date: April 2005

- 17 - Revision A10

Figure 8.3 IDL PCM Timing

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TFS FST Frequency --- 8 --- kHz

1/TBCK BCLKT Frequency 256 --- 4096 kHz

TBCKH BCLKT High Pulse Width 50 --- --- ns

TBCKL BCLKT Low Pulse Width 50 --- --- ns

TFSRH BCLKT –1 Falling Edge to FST Rising Edge

Hold Time 20 --- --- ns

TFSRS FST Rising Edge to BCLKT 0 Falling edge

Setup Time 60 --- --- ns

TFSFH BCLKT 0 Falling Edge to FST Falling Edge

Hold Time 20 --- --- ns

TBDTD BCLKT Rising Edge to Valid PCMT Delay

Time 10 --- 60 ns

THID Delay Time from the BCLKT 8 Falling Edge

(B1 channel) or BCLKT 18 Falling Edge (B2

Channel) to PCMT Output High Impedance

10 --- 50 ns

TDRS Valid PCMR to BCLKT Falling Edge Setup

Time 20 --- --- ns

TDRH PCMR Hold Time from BCLKT Falling Edge 75 --- --- ns

Table 8.3 IDL PCM Timing Parameters

FST

BCLKT

PCMT

PCMR

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

TFS

TFSRH

TFSFH

TFSRS

TBDTD TBDTD TBDTD TBDTD

THID THID

TDRS TDRS

TDRH TDRH

BCH = 0

B1 Channel

BCH = 1

B2 Channel

MSB

LSB

TBCK

TBCKH TBCKL

-1

W681511

- 18 -

FST

BCLKT

PCMT

PCMR

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

TFS

TFDTD TBDTD TBDTD TBDTD

THID THID

TDRS TDRS

TDRH TDRH

BCH = 0

B1 Channel

BCH = 1

B2 Channel

MSB

LSB

TFSRH

TFSFH

TFSRS

TBCK

TBCKH TBCKL

234567891011121314151617181920212223242526272829303132333410

Figure 8.4 GCI PCM Timing

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TFST FST Frequency --- 8 --- kHz

1/TBCK BCLKT Frequency 512 --- 6176 kHz

TBCKH BCLKT High Pulse Width 50 --- --- ns

TBCKL BCLKT Low Pulse Width 50 --- --- ns

TFSRH BCLKT 0 Falling Edge to FST Rising Edge Hold Time 20 --- --- ns

TFSRS FST Rising Edge to BCLKT 1 Falling edge Setup Time 60 --- --- ns

TFSFH BCLKT 1 Falling Edge to FST Falling Edge Hold Time 20 --- --- ns

TFDTD FST Rising Edge to Valid PCMT Delay Time --- --- 60 ns

TBDTD BCLKT Rising Edge to Valid PCMT Delay Time --- --- 60 ns

THID Delay Time from the BCLKT 16 Falling Edge (B1

channel) or BCLKT 32 Falling Edge (B2 Channel) to

PCMT Output High Impedance

10 --- 50 ns

TDRS Valid PCMR to BCLKT Rising Edge Setup Time 20 --- --- ns

TDRH PCMR Hold Time from BCLKT Rising Edge --- --- 60 ns

Table 8.4 GCI PCM Timing Parameters

W681511

Publication Release Date: April 2005

- 19 - Revision A10

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TMCK Master Clock Frequency --- 256

512

1536

1544

2048

2560

4096

--- kHz

TMCKH /

TMCK MCLK Duty Cycle for 256 kHz

Operation 45% 55%

TMCKH Minimum Pulse Width High for

MCLK(512 kHz or Higher) 50 --- --- ns

TMCKL Minimum Pulse Width Low for MCLK

(512 kHz or Higher) 50 --- --- ns

TFTRHM MCLK falling Edge to FST Rising Edge

Hold Time 50 --- --- ns

TFTRSM FST Rising Edge to MCLK Falling edge

Setup Time 50 --- --- ns

TRISE Rise Time for All Digital Signals --- --- 50 ns

TFALL Fall Time for All Digital Signals --- --- 50 ns

Table 8.5 General PCM Timing Parameters

W681511

- 20 -

9. ABSOLUTE MAXIMUM RATINGS

9.1. ABSOLUTE MAXIMUM RATINGS

Condition Value

Junction temperature 1500C

Storage temperature range -650C to +1500C

Voltage Applied to any pin (VSS - 0.3V) to (VDD + 0.3V)

Voltage applied to any pin (Input current limited to +/-20 mA) (VSS – 1.0V) to (VDD + 1.0V)

Lead temperature (soldering – 10 seconds) 3000C

VDD - VSS -0.5V to +6V

1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute

maximum ratings may affect device reliability. Functional operation is not implied at these conditions.

9.2. OPERATING CONDITIONS

Condition Value

Industrial operating temperature -400C to +850C

Supply voltage (VDD) +4.5V to +5.5V

Ground voltage (VSS) 0V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely

affect the life and reliability of the device.

W681511

Publication Release Date: April 2005

- 21 - Revision A10

10. ELECTRICAL CHARACTERISTICS

10.1. GENERAL PARAMETERS

Symbol Parameters Conditions Min (2) Typ (1) Max (2) Units

VIL Input Low Voltage 0.6 V

VIH Input High Voltage 2.4 V

VOL PCMT Output Low Voltage IOL = 3 mA 0.4 V

VOH PCMT Output High Voltage IOL = -3 mA VDD –

0.4 V

IDD VDD Current (Operating) - ADC + DAC No Load 5 8 mA

ISB VDD Current (Standby) FST & FSR =Vss ;

PUI=VDD

10 100

μA

Ipd VDD Current (Power Down) PUI= Vss 0.1 10

μA

IIL Input Leakage Current VSS<VIN<VDD +/-10

μA

IOL PCMT Output Leakage Current VSS<PCMT<VDD

High Z State +/-10

μA

CIN Digital Input Capacitance 10 pF

COUT PCMT Output Capacitance PCMT High Z 15 pF

1. Typical values: TA = 25°C , VDD = 5.0 V

2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all

specifications are 100 percent tested.

W681511

- 22 -

10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS

VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG;

TRANSMIT

(A/D) RECEIVE

(D/A) UNITPARAMETER SYM. CONDITION TYP.

MIN. MAX. MIN. MAX.

Absolute

Level LABS 0 dBm0 = 0dBm @ 600Ω1.096 --- --- --- --- VPK

Max. Transmit

Level TXMAX 3.17 dBm0 for μ-Law

3.14 dBm0 for A-Law

1.579

1.573 ---

--- ---

--- VPK

VPK

Absolute Gain

(0 dBm0 @

1020 Hz;

TA=+25°C)

GABS 0 dBm0 @ 1020 Hz;

TA=+25°C 0 -0.25 +0.25 -0.25 +0.25 dB

Absolute Gain

variation with

Temperature

GABST TA=0°C to TA=+70°C

TA=-40°C to TA=+85°C

0 -0.03

-0.05 +0.03

+0.05 -0.03

-0.05 +0.03

+0.05 dB

Frequency

Response,

Relative to

0dBm0 @

1020 Hz

GRTV 15 Hz

50 Hz

60 Hz

200 Hz

300 to 3000 Hz

3300 Hz

3400 Hz

3600 Hz

4000 Hz

4600 Hz to 100 kHz

---

-1.0

-0.20

-0.35

-0.8

---

-40

-30

-26

-0.4

+0.15

-14

-32

-0.5

-0.20

-0.35

-0.8

---

+0.15

-14

-30

Gain Variation

vs. Level Tone

(1020 Hz

relative to –10

dBm0)

GLT +3 to –40 dBm0

-40 to –50 dBm0

-50 to –55 dBm0

---

-0.3

-0.6

-1.6

+0.3

+0.6

+1.6

-0.2

-0.4

-1.6

+0.2

+0.4

+1.6

W681511

Publication Release Date: April 2005

- 23 - Revision A10

10.3. ANALOG DISTORTION AND NOISE PARAMETERS

VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG;

TRANSMIT (A/D) RECEIVE (D/A) PARAMETER SYM. CONDITION

MIN. TYP. MAX. MIN. TYP. MAX.

UNIT

Total Distortion vs.

Level Tone (1020 Hz,

μ-Law, C-Message

Weighted)

DLTμ+3 dBm0

0 dBm0 to -30 dBm0

-40 dBm0

-45 dBm0

---

dBC

Total Distortion vs.

Level Tone (1020 Hz,

A-Law, Psophometric

Weighted)

DLTA +3 dBm0

0 dBm0 to -30 dBm0

-40 dBm0

-45 dBm0

---

dBp

Spurious Out-Of-Band

at RO+ (300 Hz to

3400 Hz @ 0dBm0)

DSPO 4600 Hz to 7600 Hz

7600 Hz to 8400 Hz

8400 Hz to 100000 Hz

---

-30

-40

-30

Spurious In-Band (700

Hz to 1100 Hz @

0dBm0)

DSPI 300 to 3000 Hz ---

--- -47

---

--- -47

Intermodulation

Distortion (300 Hz to

3400 Hz –4 to –21

dBm0

DIM Two tones

--- --- -41 --- --- -41 dB

Crosstalk (1020 Hz @

0dBm0) DXT --- --- -75 --- --- -75 dBm0

Absolute Group Delay τABS 1200Hz --- --- 360 --- --- 240

μsec

Group Delay

Distortion (relative to

group delay @ 1200

Hz)

τD500 Hz

600 Hz

1000 Hz

2600 Hz

2800 Hz

---

750

380

130

750

---

750

370

120

750

μsec

Idle Channel Noise NIDL μ-Law; C-message

A-Law; Psophometric

---

--- ---

--- 5

-69 ---

--- ---

--- 13

-79 dBrnc

dBm0p

W681511

- 24 -

10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS

VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG;

PARAMETER SYM. CONDITION MIN. TYP. MAX. UNIT.

AI Input Offset Voltage VOFF,AI AI+, AI- --- --- ±25 mV

AI Input Current IIN,AI AI+, AI- --- ±0.1 ±1.0 μA

AI Input Resistance RIN,AI AI+, AI- to VAG 10 --- --- MΩ

AI Input Capacitance CIN,AI AI+, AI- --- --- 10 pF

AI Common Mode Input Voltage

Range VCM,AI AI+, AI- 1.2 --- VDD-1.2 V

AI Common Mode Rejection

Ratio CMRRTI AI+, AI- --- 60 --- dB

AI Amp Gain Bandwidth Product GBWTI AO, RLD≥10kΩ --- 2150 --- kHz

AI Amp DC Open Loop Gain GTI AO, RLD≥10kΩ --- 95 --- dB

AI Amp Equivalent Input Noise NTI C-Message Weighted --- -24 --- dBrnC

AO Output Voltage Range VTG RLD=10kΩ to VAG

RLD=2kΩ to VAG

0.5

1.0 ---

--- VDD-0.5

VDD-1.0 V

Load Resistance RLDTGRO AO, RO to VAG 2 --- --- kΩ

Load Capacitance CLDTGRO AO, RO --- --- 100 pF

AO & RO Output Current IOUT1 0.5 ≤AO,RO+≤ VDD-0.5 ±1.0 --- --- mA

RO+ Output Resistance RRO+ RO+, 0 to 3400 Hz --- 1 --- Ω

RO+ Output Offset Voltage VOFF,RO+ RO+ to VAG --- --- ±25 mV

Analog Ground Voltage VAG Relative to VSS 2.429 2.5 2.573 V

VAG Output Resistance RVAG Within ±25mV change --- 2.5 12.5 Ω

Power Supply Rejection Ratio (0

to 100 kHz to VDD, C-message) PSRR Transmit

Receive 30

30 80

75 ---

--- dBC

PAI Input Offset Voltage VOFF,PAI PAI --- ---

±20 mV

PAI Input Current IIN,PAI PAI ---

±0.05 ±1.0 μA

PAI Input Resistance RIN,PAI PAI to VAG 10 --- --- MΩ

PAI Amp Gain Bandwidth

Product GBWPI PAO- no load --- 1000 --- kHz

Output Offset Voltage VOFF,PO PAO+ to PAO- --- --- ±50 mV

Load Resistance RLDPO PAO+, PAO-

differentially 300 --- --- Ω

Load Capacitance CLDPO PAO+, PAO-

differentially --- --- 1000 pF

W681511

Publication Release Date: April 2005

- 25 - Revision A10

PARAMETER SYM. CONDITION MIN. TYP. MAX. UNIT.

PO Output Current IOUTPO 0.5 ≤AO,RO+≤ VDD-0.5 ±10.0 --- --- mA

PO Output Resistance RPO PAO+ to PAO- --- 1 --- Ω

PO Differential Gain GPO RLD=300Ω, +3dBm0, 1

kHz, PAO+ to PAO- -0.2 0 +0.2 dB

PO Differential Signal to

Distortion C-Message weighted DPO ZLD=300Ω

ZLD=100nF + 100Ω

ZLD=100nF + 20Ω

---

dBC

PO Power Supply Rejection

Ratio (0 to 25 kHz to VDD,

Differential out)

PSRRP

0 to 4 kHz

4 to 25 kHz 40

--- 55

40 ---

--- dB

W681511

- 26 -

10.5. DIGITAL I/O

10.5.1. μ-Law Encode Decode Characteristics

Digital Code

D7 D6 D5 D4 D3 D2 D1 D0

Normalized

Encode

Decision

Levels Sign Chord Chord Chord Step Step Step Step

Normalized

Decode

Levels

1 0 0 0 0 0 0 0 8031

1 0 0 0 1 1 1 1 4191

1 0 0 1 1 1 1 1 2079

1 0 1 0 1 1 1 1 1023

1 0 1 1 1 1 1 1 495

1 1 0 0 1 1 1 1 231

1 1 0 1 1 1 1 1 99

1 1 1 0 1 1 1 1 33

1 1 1 1 1 1 1 0 2

1 1 1 1 1 1 1 1 0

8159

7903

4319

4063

2143

2015

1055

991

511

479

239

223

103

Notes:

Sign bit = 0 for negative values, sign bit = 1 for positive values

W681511

Publication Release Date: April 2005

- 27 - Revision A10

10.5.2. A-Law Encode Decode Characteristics

Digital Code

D7 D6 D5 D4 D3 D2 D1 D0

Normalized

Encode

Decision

Levels Sign Chord Chord Chord Step Step Step Step

Normalized

Decode

Levels

1 0 1 0 1 0 1 0 4032

1 0 1 0 0 1 0 1 2112

1 0 1 1 0 1 0 1 1056

1 0 0 0 0 1 0 1 528

1 0 0 1 0 1 0 1 264

1 1 1 0 0 1 0 1 132

1 1 1 0 0 1 0 1 66

1 1 0 1 0 1 0 1 1

4096

3968

2048

1088

1024

544

512

272

256

136

128

Notes:

1. Sign bit = 0 for negative values, sign bit = 1 for positive values

2. Digital code includes inversion of all even number bits

W681511

- 28 -

10.5.3. PCM Codes for Zero and Full Scale

μ-Law A-Law

Level Sign bit

(D7)

Chord bits

(D6,D5,D4)

Step bits

(D3,D2,D1,D0)

Sign bit

(D7)

Chord bits

(D6,D5,D4)

Step bits

(D3,D2,D1,D0)

+ Full Scale 1 000 0000 1 010 1010

+ Zero 1 111 1111 1 101 0101

- Zero 0 111 1111 0 101 0101

- Full Scale 0 000 0000 0 010 1010

10.5.4. PCM Codes for 0dBm0 Output

μ-Law A-Law

Sample Sign bit

(D7)

Chord bits

(D6,D5,D4)

Step bits

(D3,D2,D1,D0)

Sign bit

(D7)

Chord bits

(D6,D5,D4)

Step bits

(D3,D2,D1,D0)

1 0 001 1110 0 011 0100

2 0 000 1011 0 010 0001

3 0 000 1011 0 010 0001

4 0 001 1110 0 011 0100

5 1 001 1110 1 011 0100

6 1 000 1011 1 010 0001

7 1 000 1011 1 010 0001

8 1 001 1110 1 011 0100

W681511

Publication Release Date: April 2005

- 29 - Revision A10

11. TYPICAL APPLICATION CIRCUIT

VAG 20

AI+ 19

AI-18

AO 17

/A 16

VSS 15

FST 14

PCMT 13

BCLKT 12

MCLK 11

1 VREF

2 RO-

3 PAI

4 PAO-

5 PAO+

6 VDD

7 FSR

8 PCMR

9 BCLKR

10 PUI

SOG

27k

AUDIOOUT

0.1

μ F

Power

Control

2.048 MHz

PCM OUT

PCM IN

8 kHz

27k

0.01

27k

1.0

μ F

1.0

F V

AUDIOIN-

AUDIOIN+

VAG 20

AI+ 19

AI-18

AO 17

/A 16

VSS 15

FST 14

PCMT 13

BCLKT 12

MCLK 11

1 RO+

2 NC

3 PAI

4 PAO-

5 PAO+

6 VDD

7 FSR

8 PCMR

9 BCLKR

10 PUI

0.1

μ F

Power

Control

2.048 MHz

PCM OUT

PCM IN

8 kHz

27k

1.0

μ F

1.0

F V

AUDIOIN-

AUDIOIN+

Figure 11.1 Typical circuit for Differential Analog I/O’s

VAG 20

AI+ 19

AI-18

AO 17

/A 16

VSS 15

FST 14

PCMT 13

BCLKT 12

MCLK 11

1 VREF

2 RO-

3 PAI

4 PAO-

5 PAO+

6 VDD

7 FSR

8 PCMR

9 BCLKR

10 PUI

SOG

27k Ω

27k

0.1

2.048 MHz

PCM OUT

PCM IN

8 kHz

27k

0.01

27k

1.0 μ

F V

AUDIOIN

AUDIO OUT

≥ 2k Ω

100 μ

AUDIO OUT

≥ 150 Ω

Power

Control

VAG 20

AI+ 19

AI-18

AO 17

/A 16

VSS 15

FST 14

PCMT 13

BCLKT 12

MCLK 11

1 RO+

2 NC

3 PAI

4 PAO-

5 PAO+

6 VDD

7 FSR

8 PCMR

9 BCLKR

10 PUI

27k Ω

27k

0.1

2.048 MHz

PCM OUT

PCM IN

8 kHz

27k

1.0 μ

F V

AUDIOIN

AUDIO OUT

≥ 2k Ω

100 μ

AUDIO OUT

≥ 150 Ω

Power

Control

Figure 11.2 Typical circuit for Single Ended Analog I/O’s

W681511

- 30 -

VAG 20

AI+ 19

AI-18

AO 17

/A 16

VSS 15

FST 14

PCMT 13

BCLKT 12

MCLK 11

1 VREF

2 RO-

3 PAI

4 PAO-

5 PAO+

6 VDD

7 FSR

8 PCMR

9 BCLKR

10 PUI

27k

0.1

2.048 MHz

PCM OUT

PCM IN

8 kHz

0.01

100k

1.0

27k

1.5k

Electret

Microphone

WM -

54B Panasonic

Speake

Power

Control

200

VAG 20

AI+ 19

AI-18

AO 17

/A 16

VSS 15

FST 14

PCMT 13

BCLKT 12

MCLK 11

1 RO+

2 NC

3 PAI

4 PAO-

5 PAO+

6 VDD

7 FSR

8 PCMR

9 BCLKR

10 PUISOG

27k

0.1

2.048 MHz

PCM OUT

PCM IN

8 kHz

0.01

100k

1.0

27k

1.5k

Electret

Microphone

WM -

54B Panasonic

27k

Speaker

Power

Control

200

Figure 11.3 Handset Interface

VAG 20

AI+ 19

AI-18

AO 17

/A 16

VSS 15

FST 14

PCMT 13

BC LKT 12

MCLK 11

1 VREF

2 RO-

3 PAI

4 PAO-

5 PAO+

6 VDD

7 FSR

8 PCMR

9 BCLKR

10 PUI SOG

27k

0.1

μ F

4.096 MHz

PCM OUT

PCM IN

8 kHz

VDD

27k

0.01

27k

1.0

600

TIP

RING

600

–

B2 -+5V

Power

Control

VAG 20

AI+ 19

AI-18

AO 17

/A 16

VSS 15

FST 14

PCMT 13

BC LKT 12

MCLK 11

1 RO+

2 NC

3 PAI

4 PAO-

5 PAO+

6 VDD

7 FSR

8 PCMR

9 BCLKR

10 PUI

27k

0.1

μ F

4.096 MHz

PCM OUT

PCM IN

8 kHz

VDD

600

TIP

600

–

B2 -+5V

Power

Control

Figure 11.4 Transformer Interface Circuit in GCI mode

W681511

Publication Release Date: April 2005

- 31 - Revision A10

12. PACKAGE SPECIFICATION

12.2. 20L SOG (SOP)-300MIL

SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS

SEATING PLANE

0.2

GAUGE

DIMENSION (MM) DIMENSION (INCH)

SYMBOL MIN. MAX. MIN. MAX.

A 2.35 2.65 0.093 0.104

A1 0.10 0.30 0.004 0.012

b 0.33 0.51 0.013 0.020

c 0.23 0.32 0.009 0.013

E 7.40 7.60 0.291 0.299

D 12.60 13.00 0.496 0.512

e 1.27 BSC 0.050 BSC

HE10.00 10.65 0.394 0.419

Y - 0.10 - 0.004

L 0.40 1.27 0.016 0.050

0 0º 8º 0º 8º

W681511

- 32 -

13. ORDERING INFORMATION

Winbond Part Number Description

Product Family

W681511 Product

W681511_

Package Type:

S = 20-Lead Plastic Small Outline Package (SOG/SOP)

When ordering W681511 series devices, please refer to the following part numbers.

Part Number

W681511IS

W681511

Publication Release Date: April 2005

- 33 - Revision A10

14. VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A9 Decembe

r 4, 2002

A10 April 2005 33 Add Important Notice

Important Notice

Winbond products are not designed, intended, authorized or w arranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications w herein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

ow n risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

The information contained in this datasheet may be subject to change without

notice. It is the responsibility of the customer to check the Winbond USA website

(www.winbond-usa.com) periodically for the latest version of this document, and

any Errata Sheets that may be generated between datasheet revisions.