© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice 1
CAT24C44
256-Bit Serial Nonvolatile CMOS Static RAM
Doc. No. 1083, Rev. R
FEATURES
Single 5V Supply
Infinite EEPROM to RAM Recall
CMOS and TTL Compatible I/O
Low CMOS Power Consumption:
–Active: 3 mA Max.
–Standby: 30 µA Max.
Power Up/Down Protection
10 Year Data Retention
JEDEC Standard Pinouts:
–8-pin DIP
–8-pin SOIC
100,000 Program/Erase Cycles (EEPROM)
Auto Recall on Power-up
Commercial, Industrial and Automotive
Temperature Ranges
"Green" Package Options Available
DESCRIPTION
The CAT24C44 Serial NVRAM is a 256-bit nonvolatile
memory organized as 16 words x 16 bits. The high
speed Static RAM array is bit for bit backed up by a
nonvolatile EEPROM array which allows for easy trans-
fer of data from RAM array to EEPROM (STORE) and
from EEPROM to RAM (RECALL). STORE operations
are completed in 10ms max. and RECALL operations
typically within 1.5µs. The CAT24C44 features unlim-
ited RAM write operations either through external RAM
writes or internal recalls from EEPROM. Internal false
PIN CONFIGURATION
store protection circuitry prohibits STORE operations
when VCC is less than 3.5V (typical) ensuring EEPROM
data integrity.
The CAT24C44 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles (EEPROM) and
has a data retention of 10 years. The device is available
in JEDEC approved 8-pin plastic DIP and SOIC pack-
ages.
PIN FUNCTIONS
Pin Name Function
SK Serial Clock
DI Serial Input
DO Serial Data Output
CE Chip Enable
RECALL Recall
STORE Store
VCC +5V
VSS Ground
SOIC Package (S, V, GV)
DI
DO
1
2
3
4
CE
SK RECALL
VSS
VCC
STORE
8
7
6
5
1
2
3
4
8
7
6
5
CE
SK
DI
DO
VCC
RECALL
VSS
STORE
DIP Package (P, L, GL)
2
CAT24C44
Doc. No. 1083, Rev. R © 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
POWER-UP TIMING(4)
Symbol Parameter Min. Max. Units
VCCSR VCC Slew Rate 0.5 0.005 V/m
tpur Power-Up to Read Operations 200 µs
tpuw Power-Up to Write or Store Operation 5 ms
MODE SELECTION(1)(2)
Software Write Enable Previous Recall
Mode STORESTORE
STORESTORE
STORE RECALLRECALL
RECALLRECALL
RECALL Instruction Latch Latch
Hardware Recall(3) 1 0 NOP X X
Software Recall 1 1 RCL X X
Hardware Store(3) 0 1 NOP SET TRUE
Software Store 1 1 STO SET TRUE
X = Dont Care
BLOCK DIAGRAM
ROW
DECODE
INSTRUCTION
REGISTER COLUMN
DECODE
EEPROM ARRAY
STORE
RECAL
L
STATIC RAM
ARRAY
256-BIT
STORE
RECALL
CE
DI
SK
INSTRUCTION
DECODE 4-BIT
COUNTER
CONTROL
LOGIC
VCC
VSS
DO
Note:
(1) The store operation has priority over all the other operations.
(2) The store operation is inhibited when VCC is below 3.5V.
(3) NOP designates that the device is not currently executing an instruction.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
CAT24C44
3Doc. No. 1083, Rev. R
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55°C to +125°C
Storage Temperature....................... 65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) .............2.0 to +VCC +2.0V
VCC with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
*COMMENT
Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Note:
(1) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(2) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to VCC +1V.
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Parameter Max. Unit Conditions
CI/O(1) Input/Output Capacitance 10 pF VI/O = 0V
CIN(1) Input Capacitance 6 pF VIN = 0V
D.C. OPERATING CHARACTERISTICS
VCC = 5V ±10%, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Unit Conditions
ICCO Current Consumption (Operating) 3 mA Inputs = 5.5V, TA = 0°C
All Outputs Unloaded
ISB Current Consumption (Standby) 30 µA CE = VIL
ILI Input Current 2 µA0 VIN 5.5V
ILO Output Leakage Current 10 µA0 VOUT 5.5V
VIH High Level Input Voltage 2 VCC V
VIL Low Level Input Voltage 0 0.8 V
VOH High Level Output Voltage 2.4 V IOH = 2mA
VOL Low Level Output Voltage 0.4 V IOL = 4.2mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Typ. Max. Units
NEND(1) Endurance 100,000 Cycles/Byte
TDR(1) Data Retention 10 Years
VZAP(1) ESD Susceptibility 2000 Volts
ILTH(1)(4) Latch-up 100 mA
4
CAT24C44
Doc. No. 1083, Rev. R © 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
A.C. CHARACTERISTICS
VCC = 5V ±10%, unless otherwise specified.
Symbol Parameter Min. Max. Units Conditions
FSK SK Frequency DC 1 MHz
tSKH SK Positive Pulse Width 400 ns
tSKL SK Negative Pulse Width 400 ns CL = 100pF + 1TTL gate
tDS Data Setup Time 400 ns VOH = 2.2V, VOL = 0.65V
tDH Data Hold Time 80 ns VIH = 2.2V, VIL = 0.65V
tPD SK Data Valid Time 375 ns Input rise and fall times = 10ns
tZCE Disable Time 1 µs
tCES CE Enable Setup Time 800 ns
tCEH CE Enable Hold Time 400 ns
tCDS CE De-Select Time 800 ns
A.C. CHARACTERISTICS, Store Cycle
VCC = 5V ±10%, unless otherwise specified.
Limits
Symbol Parameter Min. Max. Units Conditions
tST Store Time 10 ms CL = 100pF + 1TTL gate
tSTP Store Pulse Width 200 ns VOH = 2.2V, VOL = 0.65V
tSTZ Store Disable Time 100 ns VIH = 2.2V, VIL = 0.65V
A.C. CHARACTERISTICS, Recall Cycle
VCC = 5V ±10%, unless otherwise specified.
Symbol Parameter Min. Max. Units Conditions
tRCC Recall Cycle Time 2.5 µs
tRCP Recall Pulse Width 500 ns CL = 100pF + 1TTL gate
tRCZ Recall Disable Time 500 ns VOH = 2.2V, VOL = 0.65V
tORC Recall Enable Time 10 ns VIH = 2.2V, VIL = 0.65V
tARC Recall Data Access Time 1.5 µs
INSTRUCTION SET
Format
Instruction Start Bit Address OP Code Operation
WRDS 1 XXXX 0 0 0 Reset Write Enable Latch (Disables, Writes and Stores)
STO 1 XXXX 0 0 1 Store RAM Data in EEPROM
WRITE 1 AAAA 0 1 1 Write Data into RAM Address AAAA
WREN 1 XXXX 1 0 0 Set Write Enable Latch (Enables, Writes and Stores)
RCL 1 XXXX 1 0 1 Recall EEPROM Data into RAM
READ 1 AAAA 1 1 X Read Data From RAM Address AAAA
X = Dont care
A = Address bit
CAT24C44
5Doc. No. 1083, Rev. R
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
DEVICE OPERATION
The CAT24C44 is intended for use with standard micro-
processors. The CAT24C44 is organized as 16 registers
by 16 bits. Seven 8-bit instructions control the devices
operating modes, the RAM reading and writing, and the
EEPROM storing and recalling. It is also possible to
control the EEPROM store and recall functions in hard-
ware with the STORE and RECALL pins. The CAT24C44
operates on a single 5V supply and will generate, on
chip, the high voltage required during a RAM to EEPROM
storing operation.
Instructions, addresses and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin remains in a high impedance state except when
outputting data from the device. The CE (Chip Enable)
pin must remain high during the entire data transfer.
The format for all instructions sent to the CAT24C44 is
a logical 1 start bit, 4 address bits (data read or write
operations) or 4 Dont Care bits (device mode opera-
tions), and a 3-bit op code (see Instruction Set). For data
write operations, the 8-bit instruction is followed by 16
bits of data. For data read instructions, DO will come out
of the high impedance state and enable 16 bits of data
to be clocked from the device. The 8th bit of the read
instruction is a Dont Care bit. This is to eliminate any
bus contention that would occur in applications where
the DI and DO pins are tied together to form a common
DI/DO line. A word of caution while clocking data to and
from the device: If the CE pin is prematurely deselected
while shifting in an instruction, that instruction will not be
executed, and the shift register internal to the CAT24C44
will be cleared. If there are more than or less than 16
clocks during a memory data transfer, an improper data
transfer will result. The SK clock is completely static
allowing the user to stop the clock and restart it to
resume shifting of data.
Read
Upon receiving a start bit, 4 address bits, and the 3-bit
read command (clocked into the DI pin), the DO pin of
the CAT24C44 will come out of the high impedance state
and the 16 bits of data, located at the address specified
in the instructions, will be clocked out of the device.
When clocking data from the device, the first bit clocked
out (DO) is timed from the falling edge of the 8th clock,
all succeeding bits (D1D15) are timed from the rising
edge of the clock.
Write
After receiving a start bit, 4 address bits, and the 3-bit
WRITE command, the 16-bit word is clocked into the
device for storage into the RAM memory location speci-
fied. The CE pin must remain high during the entire write
operation.
Figure 1. RAM Read Cycle Timing
Note:
(1) Bit 8 of READ instruction is Dont Care.
Figure 2. RAM Write Cycle Timing
SK
CE
DI D0
123456789101112 222324
1D1D2D3D13 D14 D15
A11AAA 0
SK
CE
DI
DO HIGH-Z D0
123456789101112 222324
1
D1D2D3D14 D15 D0
AX11AAA (8)
(1)
6
CAT24C44
Doc. No. 1083, Rev. R © 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
WREN/WRDS
The CAT24C44 powers up in the program disable state
(the write enable latch is reset). Any programming after
power-up or after a WRDS (RAM write/EEPROM store
disable) instruction must first be preceded by the WREN
(RAM write/EEPROM store enable) instruction. Once
writing/storing is enabled, it will remain enabled until
power to the device is removed, the WRDS instruction is
sent, or an EEPROM store has been executed (STO).
Figure 4. Write Cycle Timing
Figure 3. Read Cycle Timing
x12n
SK
CE
tSKL
tSKH
1/FSK
tCEH
tDH
tDS
tCES tCDS
DI
HIGH-Z
tPD
67891011
tPD tZ
VIH
HIGH-Z
SK CYCLE #
SK
CE
DI
DO D0 D1 Dn
The WRDS (write/store disable) can be used to disable
all CAT24C44 programming functions, and will prevent
any accidental writing to the RAM, or storing to the
EEPROM.
Data can be read normally from the CAT24C44 regard-
less of the write enable latch status.
CAT24C44
7Doc. No. 1083, Rev. R
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
RCL/RECALLRECALL
RECALLRECALL
RECALL
Data is transferred from the EEPROM data memory to
RAM by either sending the RCL instruction or by pulling
the RECALL input pin low. A recall operation must be
performed before the EEPROM store, or RAM write
operations can be executed. Either a hardware or soft-
ware recall operation will set the previous recall latch
internal to the CAT24C44.
POWER-ON RECALL
The CAT24C44 has a power-on recall function that
transfers the EEPROM data to the RAM. After Power-
up, all functions are inhibited for at least 200ns (Tpur)
from stable Vcc.
STO/STORESTORE
STORESTORE
STORE
Data in the RAM memory area is stored in the EEPROM
memory either by sending the STO instruction or by
pulling the STORE input pin low. As security against any
inadvertent store operations, the following conditions
must each be met before data can be transferred into
nonvolatile storage:
The previous recall latch must be set (either a
software or hardware recall operation).
The write enable latch must be set (WREN
instruction issued).
STO instruction issued or STORE input low.
During the store operation, all other CAT24C44 func-
tions are inhibited. Upon completion of the store opera-
tion, the write enable latch is reset. The device also
provides false store protection whenever VCC falls below
a 3.5V level. If VCC falls below this level, the store
operation is disabled and the write enable latch is
reset.
Figure 6. Hardware Store Cycle Timing
Figure 5. Recall Cycle Timing
RECALL
tRCZ
tORC
tRCC
tRCP
tARC
VALID DATA
UNDEFINED DATA
DO HIGH-Z
STORE
tST
tSTP
DO
tSTZ HIGH-Z
8
CAT24C44
Doc. No. 1083, Rev. R © 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 7. Non-Data Operations
SK
CE
DI
12345678
1XXXX
OP-CODE
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT24C44SI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Prefix Device # Suffix
24C44 S I -TE13
Product
Number Tape & Reel
Package
P: PDIP
S: SOIC, JEDEC
L: PDIP (Lead-free, Halogen-free)
V: SOIC, JEDEC (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GV: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
CAT
Temperature Range
Blank = Commercial (0˚C to 70˚C)
I = Industrial (-40˚C to 85˚C)
A = Automotive (-40˚C to 105˚C)
E = Extended (-40˚C to 125˚C)
Optional
Company ID
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.caalyst-semiconductor.com
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 MiniPot™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
REVISION HISTORY
etaDnoisiveRstnemmoC
4002/71/40O ogoLeerFdaeLddA serutaeFetadpU noitarugifnoCniPetadpU margaiDkcolBetadpU teSnoitcurtsnIetadpU noitarepOeciveDetadpU noitamrofnIgniredrOetadpU yrotsiHnoisiveRddA rebmuNveRetadpU
4002/61/11P noitarugifnoCniPetadpU noitamrofnIgniredrOetadpU
4002/71/40Q noitamrofnIgniredrOetadpU
5002/30/80R noitarugifnoCniPetadpU scitsiretcarahCytilibaileRetadpU noitamrofnIgniredrOetadpU
Publication #: 1083
Revison: R
Issue date: 08/03/05