PTN3360DBS - NXP Semiconductors

1. General description

The PTN3360D is a high-speed level shif ter device which converts four lanes of low-swing

AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain

current-steering differential output signals, up to 3.0 Gbit/s per lane to support 36-bit

deep color mode, 4K 2K video format or 3D video data transport. Each of these lanes

provides a level-shifting differential buffer to translate from low-swing AC-coupled

differential signaling on the source side, to TMDS-type DC-coupled differential

current-mode signaling terminated into 50  to 3.3 V on the sink side. Additionally, the

PTN3360D provides a single-en ded active buf fer for volt age translation o f the HPD sig nal

from 5 V on the sink side to 3.3 V on the source side and provides a channel with active

buffering and level shifting of the DDC channel (consisting of a clock and a data line)

between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using

active I2C-bus buffer technology providing capacitive isolation, redriving and level shifting

as well as disablement (isolation between source and sink) of the clock and data lines.

The low-swing AC-coup led differential input signals to the PTN3360D typically com e from

a display source with multi-mode I/O, which supports multiple display standards, for

example, DisplayPort, HDMI and DVI. While the input dif ferential signals are configured to

carry DVI or HDMI coded data, they do not comply with the electrical requirements of the

DVI v1.0 or HDMI v1.4b specification. By using PTN3360D, chip set vendors are able to

implement such reconfigurable I/Os on multi-mode di splay source devices, allowing the

support of multiple display standards while keeping the number of chip set I/O pins low.

See Figure 1.

The PTN3360D main high-speed differential lanes feature low-swing self-biasing

differential inputs which are compliant to the electrical specifications of DisplayPort

Standard v1.2 an d/or PCI Express Standard v1.1, and open-drain current-steering

differential outputs compliant to DVI v1.0 and HDMI v1.4b electrical specifications. The

I2C-bus channel actively buffers as well as level-translates the DDC signals for optimal

capacitive isolation. The PTN3360D also supports power-saving modes in order to

minimize current consumption when no display is active or connected.

The PTN3360D is a fully featured HDMI as well as DVI level shifter. The PTN3360D

supersedes PTN3360B, and provides a better high speed performance with a

programmable equalizer.

PTN3360D is powered from a single 3.3 V power supply consuming a small amount of

power (230 mW typical) and is offered in a 48-terminal HVQFN48 package.

PTN3360D

Enhanced performance HDMI/DVI level shifter with active DDC

buffer, supporting 3 Gbit/s operation

Rev. 4 — 29 June 2012 Product data sheet

Product data sheet Rev. 4 — 29 June 2012 2 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].

Fig 1. Typical application system diagram

002aaf240

OUT_D1−

OUT_D1+

IN_D1−

IN_D1+

HPD_SOURCE HPD_SINK

SCL_SINK

SDA_SINK

DDC_EN

(0 V to 3.3 V)

SCL_SOURCE

SDA_SOURCE

OUT_D2−

OUT_D2+

IN_D2−

IN_D2+

OUT_D3−

OUT_D3+

IN_D3−

IN_D3+

OUT_D4−

OUT_D4+

IN_D4−

IN_D4+

PTN3360D

OE_N

DVI/HDMI CONNECTOR

5 V

0 V to 5 V0 V to 3.3 V

3.3 V

AC-coupled

differential pair

clock

CLOCK LANE

DATA LANE

AC-coupled

differential pair

TMDS data

AC-coupled

differential pair

TMDS data

AC-coupled

differential pair

TMDS data

TMDS

clock

pattern

MULTI-MODE DISPLAY SOURCE

TMDS

coded

data

TMDS

coded

data

TMDS

coded

data

PCIe PHY ELECTRICAL

CONFIGURATION

DDC I/O

C-bus)

PCIe

output buffer

reconfigurable I/Os

PCIe

output buffer

PCIe

output buffer

PCIe

output buffer

EQ5

quinary input

Product data sheet Rev. 4 — 29 June 2012 3 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

2. Features and benefits

2.1 High-speed TMDS level shifting

Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and

HDMI v1.4b compliant open-drain current-steering differential output signals

TMDS level shifting operation up to 3.0 Gbit/s per lane (300 MHz character clock)

supporting 4K 2K and 3D video formats

Programmable equalizer

Integrated 50  termination resistors for self-biasing differential inputs

Back-current safe outputs to disallow current when device power is off and monitor is

Disable feature to turn off TMDS inputs and outputs and to enter low-power state

2.2 DDC level shifting

Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side)

Rise time accelerator on sink-side DDC ports

0Hz to 400kHz I

2C-bus clock frequency

Back-power safe sink-side terminals to disallow backdrive current when power is off or

when DDC is not enabled

2.3 HPD level shifting

HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or

from 5 V on the sink side to 3.3 V on the source side

Integrated 200 k pull-down resistor on HPD sink input guarantees ‘input LOW’ when

no display is plugged in

Back-power safe design on HPD_SINK to disallow backdrive current when power is off

2.4 General

Power supply 3.0 V to 3.6 V

ESD resilience to 6 kV HBM, 1 kV CDM

Power-saving modes (using output enable)

Back-current-safe design on all sink-side main link, DDC and HPD terminals

Transparent operation: no re-timing or software configuration required

48-terminal HVQFN48 package

3. Applications

PC motherboard/graphics card

Docking station

DisplayPort to HDMI adapters supporting 4K 2K and 3D video formats

DisplayPort to DVI adapters required to drive long cables

Product data sheet Rev. 4 — 29 June 2012 4 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

4. Ordering information

5. Functional diagram

Table 1. Ordering information

Type number Topside mark Package

Name Description Version

PTN3360DBS PTN3360DBS HVQFN48 plastic thermal enhanced very thin quad flat package;

no leads; 48 terminals; body 7 70.85 mm SOT619-1

Fig 2. Functional diagram of PTN3360D

002aaf241

OUT_D1−

OUT_D1+

input bias

50 Ω50 Ω

IN_D1−

IN_D1+

HPD level shifter

HPD_SOURCE

(0 V to 3.3 V) HPD_SINK

(0 V to 5 V)

200 kΩ

SCL_SINK

SDA_SINK

DDC_EN (0 V to 3.3 V)

SCL_SOURCE

SDA_SOURCE

OUT_D2−

OUT_D2+

IN_D2−

IN_D2+

OUT_D3−

OUT_D3+

IN_D3−

IN_D3+

OUT_D4−

OUT_D4+

IN_D4−

IN_D4+

PTN3360D

OE_N

enable

input bias

50 Ω50 Ω

input bias

50 Ω50 Ω

input bias

50 Ω50 Ω

enable

DDC BUFFER

AND

LEVEL SHIFTER

EQ5

Product data sheet Rev. 4 — 29 June 2012 5 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

6. Pinning information

6.1 Pinning

HVQFN48 package supply ground is connected to both GND pins and exposed center pad.

GND pins and the exposed center pad must be connected to supply ground for proper device

operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs

to be soldered to the board using a corresponding thermal pad on the board and for proper heat

conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad

region.

Fig 3. Pin confi gura tio n for HVQFN48

OUT_D4+

OUT_D4−

OUT_D3+

OUT_D3−

GND

OUT_D2+

OUT_D2−

OUT_D1+

OUT_D1−

GND

OE_N

GND

SCL_SINK

SDA_SINK

HPD_SINK

GND

DDC_EN

n.c.

GND

n.c.

SCL_SOURCE

SDA_SOURCE

HPD_SOURCE

REXT

GND

n.c.

EQ5

GND

IN_D4+

IN_D4−

IN_D3+

IN_D3−

GND

IN_D2+

IN_D2−

IN_D1+

IN_D1−

GND

002aaf242

PTN3360DBS

12 25

11 26

10 27

9 28

8 29

7 30

6 31

5 32

4 33

3 34

2 35

1 36

terminal 1

index area

Transparent top view

Product data sheet Rev. 4 — 29 June 2012 6 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

6.2 Pin description

Table 2. Pin description

Symbol Pin Type Description

OE_N, IN_Dx and OUT_Dx signals

OE_N 25 3.3 V low-voltage

CMOS single-ended

input

Output Enable and power saving function for

high-speed differential level shifter path.

When OE_N = HIGH:

IN_Dx termination = high-impedance

OUT_Dx outputs = high-impedance; zero

output current

When OE_N = LOW:

IN_Dx termination = 50 

OUT_Dx outpu ts = active

IN_D4+ 48 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D4+ makes a differential pair with IN_D4.

The input to this pin must be AC coupled

externally.

IN_D447 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D4makes a differentia l pair with IN_D4+.

The input to this pin must be AC coupled

externally.

IN_D3+ 45 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D3+ makes a differential pair with IN_D3.

The input to this pin must be AC coupled

externally.

IN_D344 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D3makes a differentia l pair with IN_D3+.

The input to this pin must be AC coupled

externally.

IN_D2+ 42 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D2+ makes a differential pair with IN_D2.

The input to this pin must be AC coupled

externally.

IN_D241 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D2makes a differentia l pair with IN_D2+.

The input to this pin must be AC coupled

externally.

IN_D1+ 39 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D1+ makes a differential pair with IN_D1.

The input to this pin must be AC coupled

externally.

Product data sheet Rev. 4 — 29 June 2012 7 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

IN_D138 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D1makes a differentia l pair with IN_D1+.

The input to this pin must be AC coupled

externally.

OUT_D4+ 13 TMDS differential

output HDMI compliant TMDS output. OUT_D4+ makes

a differential pair with OUT_D4. OUT_D4+ is in

phase with IN_D4+.

OUT_D414 TMDS differentia l

output HDMI compliant TMDS output. OUT_D4 makes

a differential pair with OUT_D4+. OUT_D4 is in

phase with IN_D4.

OUT_D3+ 16 TMDS differential

output HDMI compliant TMDS output. OUT_D3+ makes

a differential pair with OUT_D3. OUT_D3+ is in

phase with IN_D3+.

OUT_D317 TMDS differentia l

output HDMI compliant TMDS output. OUT_D3 makes

a differential pair with OUT_D3+. OUT_D3 is in

phase with IN_D3.

OUT_D2+ 19 TMDS differential

output HDMI compliant TMDS output. OUT_D2+ makes

a differential pair with OUT_D2. OUT_D2+ is in

phase with IN_D2+.

OUT_D220 TMDS differentia l

output HDMI compliant TMDS output. OUT_D2 makes

a differential pair with OUT_D2+. OUT_D2 is in

phase with IN_D2.

OUT_D1+ 22 TMDS differential

output HDMI compliant TMDS output. OUT_D1+ makes

a differential pair with OUT_D1. OUT_D1+ is in

phase with IN_D1+.

OUT_D123 TMDS differentia l

output HDMI compliant TMDS output. OUT_D1 makes

a differential pair with OUT_D1+. OUT_D1 is in

phase with IN_D1.

HPD and DDC signals

HPD_SINK 30 5 V CMOS

single-ende d input 0 V to 5 V (nominal) input signal. This signal

comes from the DVI or HDMI sink. A HIGH value

indicates that the sink is connected; a LOW value

indicates that the sink is disconnected.

HPD_SINK is pulled down by an integrated

200 k pull-down resistor.

HPD_SOURCE 7 3.3 V CMOS

single-ended output 0 V to 3.3 V (nominal) output signal. This is

level-shifted version of the HPD_SINK signal.

SCL_SOURCE 9 single-ended 3.3 V

open-drain DDC I/O 3.3 V source-side DDC clock I/O. Pulled up by

external termination to 3.3 V. 5 V tolerant I/O.

SDA_SOURCE 8 single-ended 3.3 V

open-drain DDC I/O 3.3 V source-side DDC data I/O. Pulled up by

external termination to 3.3 V. 5 V tolerant I/O.

SCL_SINK 28 single-ended 5 V

open-drain DDC I/O 5 V sink-side DDC clock I/O. Pulled up by

external termination to 5 V. Provides rise time

acceleration for LOW-to-HIGH transitions.

SDA_SINK 29 single-ended 5 V

open-drain DDC I/O 5 V sink-side DDC data I/O. Pulled up by

external termination to 5 V. Provides rise time

acceleration for LOW-to-HIGH transitions.

Table 2. Pin description …continued

Symbol Pin Type Description

Product data sheet Rev. 4 — 29 June 2012 8 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

[1] HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins and

the exposed center pad must be connected to supply ground for proper device operation. For enhanced

thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using

a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias

need to be incorporated in the PCB in the thermal pad region.

DDC_EN 32 3.3 V CMOS input Enables the DDC buffer and level shifter.

When DDC_EN = LOW, buffer/level shifter is

disabled.

When DDC_EN = HIGH, buffer and level shifter

are enabled.

Supply and ground

VDD 2, 11,

15, 21,

26, 33,

40, 46

3.3 V DC supply Supply voltage; 3.3 V 10 %.

GND[1] 1, 5,

12, 18,

24, 27,

31, 36,

37, 43

ground Supply ground. All GND pins must be connected

to ground for proper operation.

Feature control signals

REXT 6 analog I/O Current sense port used to provide an accurate

current reference for the differential outputs

OUT_Dx. For best output voltage swing

accuracy, use of a 10 k resistor (1 % tolerance)

from this terminal to GND is recommended. May

also be tied to either VDD or GND directly (0 ).

See Section 7.2 for details.

n.c. 4, 10,

34, 35 - not connected

EQ5 3 3.3 V low-voltage

CMOS quinary input Equalizer setting input pin. This pin can be

board-strapped to one of five decode valu es:

short to GND, resistor to GND, open-circuit,

resistor to VDD, short to VDD. See Table 4 for

truth table.

Table 2. Pin description …continued

Symbol Pin Type Description

Product data sheet Rev. 4 — 29 June 2012 9 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

7. Functional description

Refer to Figure 2 “Functional diagram of PTN3360D”.

The PTN3360D level shift s four lanes of low-swing AC-coupled dif ferential input signals to

DVI and HDMI compliant open-drain current-steering differential output signals, up to

3.0 Gbit/s per lane to support 36-bit deep color mode. It has integrated 50  termination

resistors for AC-coupled differential input signals. An enable signal OE_N can be used to

turn off the TM DS input s and o utputs, ther eby minimizing power consumption. Th e TMDS

outputs are back-power safe to disallow current flow from a powered sink while the

PTN3360D is unpowered.

The PTN3360D's DDC channel provides active level shifting and buf fer ing, allowing 3.3 V

source-side termination and 5 V sink-side termination. The sink-side DDC ports are

equipped with a rise time accelerator enabling drive of long cables or high bus

capacit ance. This enables the system designer to isolate bus capacit ance to meet/exceed

HDMI DDC specification. The PTN3360D offers back-power safe sink-side I/Os to

disallow backdrive current from the DDC clock and data lines when power is off or when

DDC is not enabled. An enable signal DCC_EN enables the DDC level shifter block.

The PTN3360D also provides voltage translation for the Hot Plug Detect (HPD) signal

from 0 V to 5 V on the sink side to 0 V to 3.3 V on the source side.

The PTN3360D does not re-time any data. It contains no state machines. No inputs or

outputs of the device are latched or clocked. Because the PTN3360D acts as a

transparent level shifter, no reset is required.

7.1 Enable and disable features

PTN3360D offers different ways to enable or disable functionality, using the Output

Enable (OE_N), and DDC Enable (DDC_EN) inputs. Whenever the PTN3360D is

disabled, the device will be in Standby mode and power consumption will be minimal;

otherwise the PTN3360D will be in active mode and power consumption will be nominal.

These two inputs each affect the operation of PTN3360D differently: OE_N controls the

TMDS channels, DDC_EN affects only the DDC channel, and HPD_SINK does not affect

either of the channels. The following sections and truth table describe their detailed

operation.

7.1.1 Hot plug detect

The HPD channel of PTN3360D functions as a level-shifting buffer to pass the HPD logic

signal from the display sink device (via input HPD_SINK) on to the display source device

(via output HPD_SOURCE).

The output logic state of HPD_SOURCE output always follows the logic state of input

HPD_SINK, regardless of whether the device is in Active mode or Standby mode.

Product data sheet Rev. 4 — 29 June 2012 10 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

7.1.2 Output Enable function (OE_N)

When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully

functional. Input termination resistors are enabled and the internal bias circuits are turned

on.

When OE_N is de-ass er te d (in ac tive HIGH), th e OUT _ Dx ou tp uts are in a

high-impedance state and drive zero output curr ent. The IN_Dx inpu t buffers are disabled

and IN_Dx termination is disabled. Power consumption is minimized.

Remark: Note that OE_N signal level has no influence on the HPD_SINK inp ut,

HPD_SOURCE output, or the SCL and SDA level shif ters. A transition from HIGH to LOW

at OE_N may disable the DDC channel for up to 20 s.

7.1.3 DDC channel enable function (DDC_EN)

The DDC_EN pin is active HIGH and can be used to isolate a badly behaved sla ve. When

DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should never

change state during an I2C-bus operation. Note that disabling DDC_EN during a bus

operation may hang the bus, while enabling DDC_EN during bus traffic would corrupt the

I2C-bus operation. Hence, DDC_EN should only be toggled while the bus is idle. (See

I2C-bus specification).

Product data sheet Rev. 4 — 29 June 2012 11 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

7.1.4 Enable/disable truth table

[1] A HIGH level on input OE_N disables only the TMDS channels. A transition from HIGH to LOW at OE_N may disable the DDC channel

for up to 20 s.

[2] A LOW level on input DDC_EN disables only the DDC channel.

[3] OUT_Dx channels ‘enabled’ means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching.

[4] DDC channel ‘enabled’ means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE.

[5] The HPD_SOURCE output logic state always follows the HPD_SINK input logic state.

Table 3. HPD_ SINK, OE_N and DDC_EN enabling truth table

Inputs Channels Mode

HPD_SINK OE_N

[1] DDC_EN

[2] IN_Dx OUT_Dx[3] DDC[4] HPD_SOURCE[5]

LOW LOW LOW 50  termination

to VRX(bias)

enabled high-impedance LOW Active; DDC

disabled

LOW LOW HIGH 50  termination

to VRX(bias)

enabled SDA_SINK

connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

LOW Active; DDC

enabled

LOW HIGH LOW high-impedance high-impedance;

zero output current high-impedance LOW Standby

LOW HIGH HIGH high-impedance high-impedance;

zero output current SDA_SINK

connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

LOW Standby;

DDC

enabled

HIGH LOW LOW 50  termination

to VRX(bias)

enabled high-impedance HIGH Active; DDC

disabled

HIGH LOW HIGH 50  termination

to VRX(bias)

enabled SDA_SINK

connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

HIGH Active; DDC

enabled

HIGH HIGH LOW high-impedance high-impedance;

zero output current high-impedance HIGH Standby

HIGH HIGH HIGH high-impedance high-impedance;

zero output current SDA_SINK

connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

HIGH Standby;

DDC

enabled

Product data sheet Rev. 4 — 29 June 2012 12 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

7.2 Analog current reference

The REXT pin (pin 6) is a n ana log cu rr ent se nse por t used to pr ovide an a ccurate cu rr ent

reference for the differential outputs OUT_Dx. For best output voltage swing accuracy,

use of a 10 k resistor (1 % tolerance) connected between this terminal and GND is

recommended.

If an external 10 k1 % resistor is not used, this pin can be connected to GND or VDD

directly (0 ). In any of these cases, the output will function normally but at reduced

accuracy over voltage and temperature of the following parameters: output levels (VOL),

differential output voltage swing, and rise and fall time accuracy.

7.3 Equalizer

The PTN3360D supports 5 level equalization setting by the quinary input pin EQ5.

7.4 Backdrive current protection

The PTN3360D is designed for backdrive prevention on all sink-side TMDS outputs,

sink-side DDC I/Os and the HPD_SINK input. This supports user scenarios where the

display is connected and powered, but the PTN3360D is unpowered. In these cases, the

PTN3360D will sink no more than a negligible amount of leakage current, and will block

the display (sink) termination network from driving the power supply of the PTN3360D or

that of the inactive DVI or HDMI source.

7.5 Active DDC buffer with rise time accelerator

The PTN3360D DDC channel, besides providing 3.3 V to 5 V level shifting, includes

active bufferin g and rise time acceleration which allows up to 18 meters bus extension for

reliable DDC applications. While retaining all the operating modes and features of the

I2C-bus system during the level shifts, it permits extension of the I2C-bus by providing

bidirectional buffering for both the data (SDA) and the clock (SCL) line as well as the

rise time accelerator on the sink- s id e port (SCL_SINK and SDA_SINK) enabling the bus

to drive a lo ad up to 14 00 pF or distance of 18 m on the sink-side port, and 4 00 pF on the

source-side port (SCL_SOURCE and SCA_SOURCE). Using the PTN3360D for DVI or

HDMI level shifting enables the system designer to isolate bus capacitance to

meet/exceed HDMI DDC specification. The SDA and SCL pins are overvoltage tolerant

and are high-impedance when the PTN3360D is unpowered or when DDC_EN is LOW.

Table 4. Equalizer settings

Inputs Quinary notation Equalizer mode

EQ5

short to GND 050dB

10 k resistor to GND 152dB

open-circuit 253.5 dB

10 k resistor to VDD 359dB

short to VDD 457dB

Product data sheet Rev. 4 — 29 June 2012 13 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

PTN3360D has rise time accelerators on the sink-side port (SCL_SINK and SDA_SINK)

only. During positive bus transitions on the sink-side port, a current source is switched on

to quickly slew the SCL_SINK and SDA_SINK lines HIGH once the 5 V DDC bus VIL

threshold level of around 1.5 V is exceeded, and turns off as the 5 V DDC bus VIH

threshold voltage of approximately 3.5 V is approached.

8. Limiting values

[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -

Component level; Electrostatic Discharge Association, Rome, NY, USA.

[2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device

Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.

9. Recommended operating conditions

[1] Input signals to these pins must be AC-coupled.

[2] Operation without external reference resistor is possible but will result in reduced output voltage swing

accuracy. For details, see Section 7.2.

9.1 Current consumption

Table 5. Limitin g values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.3 +4.6 V

VIinput voltage 3.3 V CMOS inputs 0.3 VDD +0.5 V

5.0 V CMOS inputs 0.3 6.0 V

Tstg storage temperature 65 +150 C

VESD electrostatic discharge

voltage HBM [1] - 6000 V

CDM [2] - 1000 V

Table 6. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3.0 3.3 3.6 V

VIinput voltage 3.3 V CMOS inputs 0 - 3.6 V

5.0 V CMOS inputs 0 - 5.5 V

VI(AV) average input

voltage IN_Dn+, IN_Dn inputs [1] -0 -V

Rref(ext) external reference

resistance connected between pin

REXT (pin 6) and GND [2] -101% - k

Tamb ambient temperature ope rating in free air 40 - +85 C

Table 7. Current consumption

Symbol Parameter Conditions Min Typ Max Unit

IDD supply current OE_N = 0; Active mode - 70 100 mA

OE_N = 1 and DDC_EN = 0;

Standby mode --5mA

Product data sheet Rev. 4 — 29 June 2012 14 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

10. Characteristics

10.1 Differential inputs

[1] UI (unit interval) = tbit (bit time).

[2] UI is determined by the display mode. Nominal bit rate ranges from 250 Mbit/s to 3.0 Gbit/s per lane.

[3] VRX_DIFFp-p = 2 VRX_D+ VRX_D. Applies to IN_Dx signals.

[4] Vi(cm)M(AC) = VRX_D+ +V

RX_D/2VRX(cm).

VRX(cm) = DC (avg) of VRX_D+ +V

RX_D/2.

[5] Differential inputs will switch to a high-impedance state when OE_N is HIGH.

10.2 Differential outputs

The level shifter’s differential outputs are designed to meet HDMI version 1.4a and

DVI version 1.0 specifications.

[1] VTT is the DC termination voltage in the HDMI or DVI sink. VTT is nominally 3.3 V.

[2] The open-drain output pulls down from VTT.

[3] Swing down from TMDS termination voltage (3.3 V 10 %).

Table 8. Differential input characteristics for IN_Dx signals

Symbol Parameter Conditions Min Typ Max Unit

UI unit interva l[1] [2] 333 - 4000 ps

VRX_DIFFp-p differential input peak-to-peak voltage [3] 0.175 - 1.200 V

tRX_EYE receiver eye time minimum eye width at

IN_Dx input pair 0.8 - - UI

Vi(cm)M(AC) peak co mmon-mode input voltage (AC) includes al l frequencies

above 30 kHz [4] --100mV

ZRX_DC DC input impedance 40 50 60 

VRX(bias) bias receiver voltage 1.0 1.2 1.4 V

ZI(se) single-ended input impedance inputs in

high-impedance state [5] 100 - - k

Table 9. Differential output ch aracteristics for OUT_Dx signals

Symbol Parameter Conditions Min Typ Max Unit

VOH(se) single-ended HIGH-level

output voltage [1] VTT 0.01 VTT VTT +0.01 V

VOL(se) single-ended LOW-level

output voltage [2] VTT 0.60 VTT 0.50 VTT 0.40 V

VO(se) single-ended ou tput

voltage variation logic 1 and logic 0 state applied

respectively to differential inputs

IN_Dn; Rref(ext) connected;

see Table 6

[3] 400 500 600 mV

IOZ OFF-state output current single-ended - - 10 A

trrise time 20 % to 80 % 75 - 240 ps

tffall time 80 % to 20 % 75 - 240 ps

tsk skew time intra-pair [4] --10ps

inter-pair [5] --250ps

tjit(add) added jitter time jitter contribution [6] -10-ps

Product data sheet Rev. 4 — 29 June 2012 15 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

[4] This differential skew budget is in addition to the skew presented between IN_D+ and IN_D paired input pins.

[5] This lane-to-lane skew budget is in addition to skew between differential input pairs.

[6] Jitter budget for differential signals as they pass through the level shifter.

10.3 HPD_SINK input, HPD_SOURCE output

[1] Low-speed input changes state on cable plug/unplug.

[2] Time from HPD_SINK changing state to HPD_SOURCE changing state. Includes HPD_SOURCE rise/fall time.

[3] Time required to transition from VOH to VOL or from VOL to VOH.

[4] Guarantees HPD_SINK is LOW when no display is plugged in.

10.4 OE_N, DDC_EN inputs

[1] Measured with input at VIH maximum and VIL minimum.

Table 10. HPD chara cteristics

Symbol Parameter Conditions Min Typ Max Unit

VIH HIGH-level input voltage HPD_SINK [1] 2.0 5.0 5.3 V

VIL LOW-level input voltage HPD_SINK 0 - 0.8 V

ILI input leakage current HPD_SINK - - 15 A

VOH HIGH-level output voltage HPD_SOURCE 2.5 - VDD V

VOL LOW-level output voltage HPD_SOURCE 0 - 0.2 V

tPD propagation delay from HPD_SINK to HPD_SOURCE;

50 % to 50 % [2] --200ns

tttransition time HPD_SOURCE rise/fall; 10 % to 90 % [3] 1 - 20 ns

Rpd pull-down resistance HPD_SINK input pull-down resistor [4] 100 200 300 k

Table 11. OE_N, DDC_EN input characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIH HIGH-level input voltage 2.0 - V

VIL LOW-level input voltage - 0.8 V

ILI input leakage current OE_N pin [1] --10A

Product data sheet Rev. 4 — 29 June 2012 16 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

10.5 DDC characteristics

[1] VCC1 is the pull-up voltage for DDC source.

[2] VCC2 is the pull-up voltage for DDC sink.

Table 12. DDC characteristics

Symbol Parameter Conditions Min Typ Max Unit

Input and output SCL_SOURCE and SDA_SOURCE, VCC1 = 3.0 V to 3.6 V[1]

VIH HIGH-level input voltage 0.7VCC1 -3.6 V

VIL LOW-level input voltage 0.5 - +0.3VCC1 V

VILc contention LOW-level input voltage 0.5 0.4 - V

ILI input leakage current VI=3.6V - - 10 A

IIL LOW-level input current VI=0.2V - - 10 A

VOL LOW-level output voltage IOL =100A or 6 mA 0.47 0.52 0.6 V

VOLVILc difference between LOW-level output

and LOW-level input voltage

contention

guaranteed by design - - 70 mV

Cio input/output capacitance VI=3V or 0V; V

DD =3.3V - 6 7 pF

VI= 3 V or 0 V; VDD =0V - 6 7 pF

Input and output SDA_SINK and SCL_SINK, VCC2 =4.5V to 5.5V

[2]

VIH HIGH-level input voltage 0.7VCC2 -5.5 V

VIL LOW-level input voltage 0.5 - +1.5 V

ILI input leakage current VI=5.5V - - 10 A

IIL LOW-level input current VI=0.2V - - 10 A

VOL LOW-level output voltage IOL =6mA - 0.1 0.2 V

Cio input/output capacitance VI=3V or 0V; V

DD =3.3V - - 7 pF

VI= 3 V or 0 V; VDD =0V - 6 7 pF

Itrt(pu) transient bo osted pull-up current VCC2 =4.5V;

slew rate = 1.25 V/s-6-mA

Product data sheet Rev. 4 — 29 June 2012 17 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

11. Package outline

Fig 4. Package outline SOT619-1 (HVQFN48)

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 7.1

6.9

5.25

4.95

7.1

6.9 5.25

4.95

5.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT619-1 MO-220 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT619-1

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;

48 terminals; body 7 x 7 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 24

48 37

01-08-08

02-10-18

terminal 1

index area

terminal 1

index area

1/2 e

1/2 e AC

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 4 — 29 June 2012 18 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

12. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

12.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit boar d

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 4 — 29 June 2012 19 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

12.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 5) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 13 and 14

Moisture sensitivity precautions, as indicated on the packin g, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 5.

Table 13. SnPb eutec t ic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 14. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 4 — 29 June 2012 20 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

13. Abbreviations

MSL: Moisture Sensitivity Level

Fig 5. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 15. Ab breviations

Acronym Description

CDM Charged-Device Model

CEC Consumer Electronics Control

DDC Data Display Channel

DVI Digital Visual Interface

EMI ElectroMagnetic Interference

ESD ElectroStatic Discharge

HBM Human Body Model

HDMI High-Definition Multimedia Interface

HPD Hot Plug Detect

I2C-bus Inter-IC bus

I/O Input/Output

NMOS Negative-channel Metal-Oxide Semiconductor

TMDS Transition Minimized Differential Signaling

VESA Video Electronic Standards Association

Product data sheet Rev. 4 — 29 June 2012 21 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

14. Revision history

Table 16. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PTN3360D v.4 20120629 Product data sheet - PTN3360D v.3

Modifications: •phrase changed from “HDMI v1.4a” to “HDMI v.1.4b” throughout this data sheet

PTN3360D v.3 20120326 Product data sheet - PTN3360D v.2

PTN3360D v.2 20101119 Product data sheet - PTN3360D v.1

PTN3360D v.1 20100616 Product data sheet - -

Product data sheet Rev. 4 — 29 June 2012 22 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The prod uct sta tus of device (s) descri bed in this d ocument m ay have cha nged since thi s docume nt was publish ed and ma y diffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information se e the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed be tween

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors product s are not designed,

authorized or warranted to be suitable for use in life support, life-crit ical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings onl y and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 4 — 29 June 2012 23 of 24

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automo tive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b )

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive appl ications beyond NXP Semiconductors’

standard warrant y and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

15.4 Licenses

15.5 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Purchase of NXP ICs with HDMI technology

Use of an NXP IC with HDMI technology in equipment that co mplies with

the HDMI standard re quires a license from HDMI Licensing LLC, 1060 E.

Arques Avenue Suite 100, Sunnyval e CA 94085, USA, e-mail:

admin@hdmi.org.

NXP Semiconductors PTN3360D

HDMI/DVI level shifter supporting 3 Gbit/s operation

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 June 2012

Document iden tifier: PTN3360D

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 3

2.1 High-speed TMDS level shifting . . . . . . . . . . . . 3

2.2 DDC level shifting. . . . . . . . . . . . . . . . . . . . . . . 3

2.3 HPD level shifting . . . . . . . . . . . . . . . . . . . . . . . 3

2.4 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7 Functional description . . . . . . . . . . . . . . . . . . . 9

7.1 Enable and disable features. . . . . . . . . . . . . . . 9

7.1.1 Hot plug detect . . . . . . . . . . . . . . . . . . . . . . . . 9

7.1.2 Output Enable function (OE_N) . . . . . . . . . . . 10

7.1.3 DDC channel enable function (DDC_EN). . . . 10

7.1.4 Enable/disable truth table. . . . . . . . . . . . . . . . 11

7.2 Analog current reference . . . . . . . . . . . . . . . . 12

7.3 Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.4 Backdrive current protection. . . . . . . . . . . . . . 12

7.5 Active DDC buffer with rise time accelerator . 12

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13

9 Recommended operating conditions. . . . . . . 13

9.1 Current consumption . . . . . . . . . . . . . . . . . . . 13

10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 14

10.1 Differential inputs . . . . . . . . . . . . . . . . . . . . . . 14

10.2 Differential outputs . . . . . . . . . . . . . . . . . . . . . 14

10.3 HPD_SINK input, HPD_SOURCE output. . . . 15

10.4 OE_N, DDC_EN inputs. . . . . . . . . . . . . . . . . . 15

10.5 DDC characteristics . . . . . . . . . . . . . . . . . . . . 16

11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17

12 Soldering of SMD packages . . . . . . . . . . . . . . 18

12.1 Introduction to soldering . . . . . . . . . . . . . . . . . 18

12.2 Wave and reflow soldering . . . . . . . . . . . . . . . 18

12.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 18

12.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 19

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

15.4 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

15.5 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

16 Contact information . . . . . . . . . . . . . . . . . . . . 23

17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24