11C90DCQRNOPB - National Semiconductor

TL/F/9892

11C90/11C91 650 MHz Prescalers

Not Intended For New Designs

August 1992

11C90/11C91

650 MHz Prescalers

General Description

The 11C90 and 11C91 are high-speed prescalers designed

specifically for communication and instrumentation applica-

tions. All discussions and examples in this data sheet are

applicable to the 11C91 as well as the 11C90.

The 11C90 will divide by 10 or 11 and the 11C91 by 5 or 6,

both over a frequency range from DC to typically 650 MHz.

The division ratio is controlled by the Mode Control. The

divide-by-10 or -11 capability allows the use of pulse swal-

lowing techniques to control high-speed counting modulos

by lower-speed circuits. The 11C90 may be used with either

ECL or TTL power supplies.

In addition to the ECL outputs Q and Q, the 11C90 contains

an ECL-to-TTL converter and a TTL output. The TTL output

operates from the same VCC and VEE levels as the counter,

but a separate pin is used for the TTL circuit VEE. This mini-

mizes noise coupling when the TTL output switches and

also allows power consumption to be reduced by leaving

the separate VEE pin open if the TTL output is not used.

To facilitate capacitive coupling of the clock signal, a 400X

resistor (VREF) is connected internally to the VBB reference.

Connecting this resistor to the Clock Pulse input (CP) auto-

matically centers the input about the switching threshold.

Maximum frequency operation is achieved with a 50% duty

cycle.

Each of the Mode Control inputs is connected to an internal

2kXresistor with the other end uncommitted (RM1and

RM2). An M input can be driven from a TTL circuit operating

from the same VCC by connecting the free end of the asso-

ciated 2 kXresistor to VCCA. When an M input is driven

from the ECL circuit, the 2 kXresistor can be left open or, if

required, can be connected to VEE to act as a pull-down

resistor.

Logic Symbol

TL/F/9892–2

Pin Names Description

CE Count Enable Input (Active LOW)

CP Clock Pulse Input

MnCount Modulus Control Input

MS Asynchronous Master Set Input

Q, Q ECL Outputs

QTTL TTL Output

RMn2kXResistor to Mn

VREF 400XResistor to VBB

Connection Diagram

16-Pin DIP

TL/F/9892–1

C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings

Above which the useful life may be impaired

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature b65§Ctoa

150§C

Maximum Junction Temperature (TJ)a150§C

Supply Voltage Range b7.0V to GND

Input Voltage (DC) VEE to GND

Output Current (DC Output HIGH) b50 mA

Operating Range b5.7V to b4.7V

Lead Temperature

(Soldering, 10 sec.) 300§C

Recommended Operating

Conditions

Min Typ Max

Ambient Temperature (TA)

Commercial 0§Ca75§C

Military b55§Ca125§C

Supply Voltage (VEE)

Commercial b5.7V b5.2V b4.7V

Military b5.7V b5.2V b4.7V

TTL Input/Output Operation

DC Electrical Characteristics

Over Operating Temperature and Voltage Range unless otherwise noted, Pins 12 and 13 eGND

Symbol Parameter Min Typ Max Units Conditions

(Note 3)

VIH Input HIGH Voltage 4.1 V Guaranteed Input HIGH Threshold

M1and M2Inputs Voltage (Note 4), VCC eVCCA e5.0V

VIL Input LOW Voltage 3.3 V Guaranteed Input LOW Threshold

M1and M2Inputs Voltage (Note 4), VCC eVCCA e5.0V

VOH Output HIGH Voltage 2.3 3.3 V VCC eVCCA eMin,

QTTL Output IOH eb

640 mA

VOL Output LOW Voltage 0.2 0.5 V VCC eVCCA eMin,

QTTL Output IOL e20.0 mA

IIL Input LOW Current b2.3 b5.0 mA VCC eVCCA eMax,

M1and M2Inputs VIN e0.4V, Pins 6, 7 eVCC

ISC Output Short Circuit b20 b35 b80 mA VCC eVCCA eMax,

Current VOUT e0.0V, Pin 14 eVCC

AC Electrical Characteristics

VCC eVCCA e5.0V Nominal, VEE eGND, TAea

25§C

Symbol Parameter Min Typ Max Units Conditions

tPLH Propagation Delay, (50% to 50%) 61014 ns

See

Figure 1

tPHL CP to QTTL

tPLH Propagation Delay, (50% to 50%) 12 17 ns

MS to QTTL

tsMode Control Setup Time 4 2 ns

thMode Control Hold Time 0 b2ns

TLH Output Rise Time 10 ns

(20% to 80%)

tTHL Output Fall Time 2ns

(80% to 20%)

fMAX Count Frequency 550 650 MHz b55§Ctoa

125§C

600 650 0§Ctoa

75§C

Clock Input AC Coupled

350 mV Peak-to-Peak

Sinewave (Note 5)

ECL OperationÐCommercial Version

DC Electrical Characteristics

VCC eVCCA eGND, VEE eb

5.2V

Symbol Parameter Min Typ Max Units TAConditions

VOH Output HIGH Voltage b1060 b995 b905 0§C Load e50Xto b2V

Q and Q b1025 b960 b880 mV a25§C

b980 b910 b805 a75§C

VOL Output LOW Voltage b1820 b1705 b1620 mV 0§Cto

Q and Q a75§C

VIH Input HIGH Voltage b1135 b840 0§C Guaranteed Input HIGH

b1095 b810 mV a25§C Signal (Note 6)

b1035 b720 a75§C

VIL Input LOW Voltage b1870 b1500 0§C Guaranteed Input LOW

b1850 b1485 mV a25§C Signal

b1830 b1460 a75§C

IIH Input HIGH Current VIN eVIHA

CP Input (Note 1) 400 a25§C

MS Input 400 mAa25§C

M1and M2Input 250 a25§C

IIL Input LOW Current 0.5 mAa25§CV

IN eVILB

IEE Power Supply Current b110 b75 mA 0§C to Pins 6, 7, 13 not connected

b119 a75§C

VEE Operating Supply b5.7 b5.2 b4.7 V 0§Cto

Voltage Range a75§C

VREF Reference Voltage b1550 b1150 mV a25§CVRM1eVRM2eb

5.2V

INeb

10.0 mA

AC Electrical Characteristics

TAe0§Ctoa

75§C, VCC eVCCA eGND, VEE eb

5.2V

Symbol Parameter 0§Ca25§Ca75§CUnits Conditions

Typ Min Typ Max Typ

tPLH Propagation Delay, 1.8 1.3 2.0 3.0 2.5 ns Output:

tPHL (50% to 50%) CP to Q RLe50Xto b2.0V

tPLH Propagation Delay, 3.7 4.0 6.0 4.5 ns Input:

(50% to 50%) MS to Q tri etfi e2.0 g0.1 ns

tsSetup Time, M to CP 2.0 4.0 2.0 2.0 ns (20% to 80%)

thHold Time, M to CP b2.0 0.0 b2.0 b2.0 ns See

Figure 1

tTLH Output Rise Time 1.0 1.0 2.0 1.0 ns

(20% to 80%)

tTHL Output Fall Time 1.0 1.0 2.0 1.0 ns

(80% to 20%)

fMAX Maximum Clock Frequency AC Coupled Input 350 mV

650 600 650 625 MHz Peak-to-Peak. fMAX is

Guaranteed to be 575 MHz

Min at 0§Ctoa

75§C.

ECL OperationÐMilitary Version

DC Electrical Characteristics

VCC eVCCA eGND, VEE eb

5.2V

Symbol Parameter Min Typ Max Units TAConditions

VOH Output HIGH Voltage b1100 b1030 b900 b55§C Load e100Xto b2V

Q and Q b980 b910 b820 mV a25§C

b910 b820 b670 a125§C

VOL Output LOW Voltage b1820 b1705 b1620 mV b55§Cto

Q and Q a125§C

VIH Input HIGH Voltage b1190 b905 b55§C Guaranteed Input HIGH

b1095 b810 mV a25§C Signal (Note 6)

b975 b690 a125§C

VIL Input LOW Voltage b1890 b1525 b55§C Guaranteed Input LOW

b1850 b1485 mV a25§C Signal

b1800 b1435 a125§C

IIH Input HIGH Current VIN eVIHA

CP Input (Note 1) 400 a25§C

MS Input 400 mAa25§C

M1and M2Input 250 a25§C

IIL Input LOW Current 0.5 mAa25§CV

IN eVILB

IEE Power Supply Current b110 b75 mA a25§C Pins 6, 7, 13 not connected

b119 mA b55§Cto

125§C

VEE Operating Supply b5.7 b5.2 b4.7 V b55§Cto

Voltage Range a125§C

VREF Reference Voltage b1550 b1150 mV a25§CVRM1eVRM2eb

5.2V

INeb

10.0 mA

AC Electrical Characteristics

TAeb

55§Ctoa

125§C, VCC eVCCA eGND, VEE eb

5.2V

Symbol Parameter b55§Ca25§Ca125§CUnits Conditions

Typ Min Typ Max Typ

tPLH Propagation Delay, 1.5 1.3 2.0 3.0 3.0 ns Output:

tPHL (50% to 50%) CP to Q RLe50Xto b2.0V

tPLH Propagation Delay, 3.5 4.0 6.0 5.0 ns

(50% to 50%) MS to Q Input:

tsSetup Time, M to CP 2.0 4.0 2.0 2.0 ns

tri etfi e2.0 g0.1 ns

thHold Time, M to CP b2.0 0.0 b2.0 b2.0 ns

(20% to 80%)

tTLH Output Rise Time 1.0 1.0 2.0 1.0 ns

See

Figure 1

(20% to 80%)

tTHL Output Fall Time 1.0 1.0 2.0 1.0 ns

(80% to 20%)

fMAX Maximum Clock Frequency AC Coupled Input 350 mV

700 600 650 600 MHz Peak-to-Peak. fMAX is

Guaranteed to be 550 MHz

Min at b55§Ctoa

125§C.

Note 1: Conditions for testing, not shown in the Table, are chosen to guarantee operation under ‘‘worst case’’ conditions.

Note 2: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these ‘‘worst case’’ values normally occur at the temperature and supply

voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.

Note 3: Typical limits are at VCC e5.0V and TAea

25§C.

Note 4: The M1and M2threshold specifications are normally referenced to the VCC potential, as shown in the ECL operation tables. Using VEE (GND) as the

reference, as in normal TTL practice, effectively makes the threshold vary directly with VCC. Threshold is typically 1.3V below VCC (e.g., a3.7V at VCC ea

5V). A

signal swing about threshold of g0.4V is adequate, which gives the state VIH and VIL values. The internal 2 kXresistors are intended to pull TTL outputs up to the

required VIH range, as discussed in the Functional Description and shown in

Figure 5.

Note 5: TTL Output Signal swing is guaranteed at fMAX over temperature range.

Note 6: M1or M2can be tied to VCC for fixed divide-by-ten operation.

TL/F/9892–3

TL/F/9892–4

Conditions:

VCC ea

2.0V

VEE eb

3.2V

RTe50X(scope input impedance)

CLeJig and stray capacitance k5.0 pF

I1eL2eequal 50Ximpedance lines

Ce0.1 pF

Note 7: Use high impedance to test QTTL.

Connect pin 13 to VEE.

Note 8: For High frequency test use AC coupled input as in

Figure 3

Adjust input amplitude to 350 mV peak-to-peak.

FIGURE 1. AC Test Circuit

Functional Description

The 11C90 contains four ECL Flip-Flops, an ECL to TTL

converter and a Schottky TTL output buffer with an active

pull-up. Three of the Flip-Flops operate as a synchronous

shift counter driving the fourth Flip-Flop operating as an

asynchronous toggle. The internal feedback logic is such

that the TTL output and the Q ECL output are HIGH for six

clock periods and LOW for five clock periods. The Mode

Control (M) inputs can modify the feedback to make the

output HIGH for five clock periods and LOW for five clock

periods, as indicated in the Count Sequence Table.

The feedback logic is such that the instant the output goes

HIGH, the circuit is already committed as to whether the

output period will be 10 or 11 clock periods long. This

means that subsequent changes in an M input signal, in-

cluding decoding spikes, will have no effect on the current

output period. The only timing restriction for an M input sig-

nal is that it be in the desired state at least a setup time

before the clock that follows the HHLL state shown in the

table. The allowable propagation delay through external log-

ic to an M input is maximized by designing it to use the

positive transition of the 11C90 output as its active edge.

This gives an allowable delay of ten clock periods, minus

the CP to Q delay of the 11C90 and the M to CP setup time.

If the external logic uses the negative output transition as its

active edge, the allowable delay is reduced to five clock

periods minus the previously mentioned delay and setup

time.

Capacitively coupled triggering is simplified by the 400Xre-

sistor which connects pin 15 to the internal VBB reference.

By connecting this to the CP input, as shown in

Figure 3

, the

clock is automatically centered about the input threshold. A

clock duty cycle of 50% provides the fastest operation,

since the Flip-Flops are Master-Slave types with offset clock

thresholds between master and slave. This feature ensures

that the circuit will operate with clock waveforms having

very slow rise and fall times, and thus, there is no maximum

frequency restriction. Recommended minimum and maxi-

mum clock amplitude as a function of a frequency and tem-

perature are shown in the graph labeled

Figure 2

. When the

CP or any other input is driven from another ECL circuit,

normal ECL termination methods are recommended. One

method is indicated in

Figure 4

. Other ECL termination

methods are discussed in the F100K ECL Design Guide

(Section 5 of Databook).

TL/F/9892–5

FIGURE 2. AC Coupled Triggering Characteristics

TL/F/9892–10

FIGURE 3. Capacitively Coupled Clocking

TL/F/9892–11

ZOX50 75 100

R1X80.6 121 162

R2X130 196 261

VEE eb

5.2V, VCC e0V, VTT eb

2.0V

FIGURE 4. Clocking by ECL Source via Terminated Line

When an M input is to be driven from a TTL output operating

from the same VCC and ground (VEE), the internal 2 kX

resistor can be used to pull the TTL output up as shown in

Figure 5

. Some types of TTL outputs will only pull up to

within two diode drops of VCC, which is not high enough for

11C90 inputs. The resistor will pull the signal up through the

threshold region, although this final rise may be somewhat

slow, depending on wiring capacitance. A resistor network

that gives faster rise and also lower impedance is shown in

Figure 6

TL/F/9892–12

FIGURE 5. Using Internal Pull-Up with TTL Source

TL/F/9892–13

FIGURE 6. Faster Low Impedance TTL to ECL Interface

Functional Description (Continued)

The ECL outputs have no pull-down resistors and can drive

series or parallel terminated transmission lines. For short

interconnections that do not require impedance matching, a

270Xto 510Xresistor to VEE can be used to establish the

VOL level. Both VCC pins must always be used and should

be connected together as close to the package as possible.

Pin 12 must always be connected to the VEE side of the

supply, while pin 13 is required only if the TTL output is

used. Low impedance VCC and VEE distribution and RF by-

pass capacitors are recommended to prevent crosstalk.

Logic Diagram 11C90

TL/F/9892–6

Note: This diagram is provided for understanding of logic operation only. It should not be used for evaluation of propagation delays as many internal functions are

achieved more efficiently than shown.

Count Sequence Table 11C90

TL/F/9892–7

Note: A HIGH on MS forces all Qs HIGH.

Operating Mode Table 11C90

Inputs Output

MS CE M1M2Response

H X X X Set HIGH

L H X X Hold

LLLL

LLHX

LLXH

HeHIGH Voltage Level

LeLOW Voltage Level

XeDon’t Care

Logic Diagram 11C91

TL/F/9892–8

Count Sequence Table 11C91

TL/F/9892–9

Note: A HIGH on MS forces all Qs HIGH.

Operating Mode Table 11C91

Inputs Output

MS CE M1M2Response

H X X X Set HIGH

L H X X Hold

LLLL

LLXH

LLHX

HIGH Voltage Level

LeLOW Voltage Level

XeDon’t Care

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

11C90/91 D C QR

Device Number Special Variations

(basic) QR eCommercial grade device

with burn-in

Package Code

DeCeramic Dual In-Line Temperature Range

CeCommercial (0§Ctoa

85§C)

11C90/11C91 650 MHz Prescalers

Physical Dimensions inches (millimeters)

16 Lead Ceramic Dual-In-Line Package (D)

NS Package Number J16A

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failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

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