Semiconductor Components Industries, LLC, 2001
February, 2001 – Rev. 7 1Publication Order Number:
MC14536B/D
MC14536B
Programmable Timer
The MC14536B programmable timer is a 24–stage binary ripple
counter with 16 stages selectable by a binary code. Provisions for an
on–chip RC oscillator or an external clock are provided. An on–chip
monostable circuit incorporating a pulse–type output has been
included. By selecting the appropriate counter stage in conjunction
with the appropriate input clock frequency, a variety of timing can be
achieved.
•24 Flip–Flop Stages — Will Count From 20 to 224
•Last 16 Stages Selectable By Four–Bit Select Code
•8–Bypass Input Allows Bypassing of First Eight Stages
•Set and Reset Inputs
•Clock Inhibit and Oscillator Inhibit Inputs
•On–Chip RC Oscillator Provisions
•On–Chip Monostable Output Provisions
•Clock Conditioning Circuit Permits Operation With Very Long Rise
and Fall Times
•Test Mode Allows Fast Test Sequence
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol Parameter Value Unit
VDD DC Supply Voltage Range –0.5 to +18.0 V
Vin, Vout Input or Output Voltage Range
(DC or Transient) –0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current
(DC or Transient) per Pin ±10 mA
PDPower Dissipation,
per Package (Note 3.) 500 mW
TAOperating Temperature Range –55 to +125 °C
Tstg Storage Temperature Range –65 to +150 °C
TLLead Temperature
(8–Second Soldering) 260 °C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
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A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14536BCP PDIP–16 2000/Box
MC14536BDW SOIC–16 47/Rail
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC14536BCP
AWLYYWW
MC14536BDWR2 SOIC–16 1000/Tape & Reel
SOIC–16
DW SUFFIX
CASE 751G
1
16
14536B
AWLYYWW
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14536B
ALYW
MC14536BF SOEIAJ–16 See Note 1.
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2
STAGES 9 THRU 24
Q
24
Q
23
Q
22
Q
21
Q
20
Q
19
Q
18
Q
17
Q
16
Q
15
Q
14
Q
13
Q
12
Q
11
Q
10
Q
9
DECODER
MONOSTABLE
MULTIVIBRATOR
DECODE
OUT
13MONO-IN15
D12
C11
B10
A9
VDD = PIN 16
VSS = PIN 8
STAGES
1 THRU 8
8 BYPASSSETRESETCLOCK INH.
7216
5
OUT2
4
OUT1
3
IN1
OSC. INHIBIT14
Figure 1. Pin Assignment
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
D
DECODE
OSC INH
MONO-IN
VDD
A
B
C
OUT 1
IN 1
RESET
SET
VSS
CLOCK INH
8-BYPASS
OUT 2
Figure 2. Block Diagram
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
– 55C 25C 125C
Characteristic Symbol VDD
Vdc Min Max Min Typ
(Note 4.) Max Min Max Unit
Output Voltage “0” Level
Vin = VDD or 0 VOL 5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD VOH 5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL 5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH 5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc) Pins 4 & 5
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH 5.0
5.0
10
15
– 1.2
– 0.25
– 0.62
– 1.8
—
—
—
—
– 1.0
– 0.25
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
—
—
—
—
mAdc
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc) Pin 13
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL 5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current Iin 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
Input Capacitance
(Vin = 0) Cin — — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package) IDD 5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.010
0.020
0.030
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current (Note 5., 6.)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (1.50 µA/kHz) f + IDD
IT = (2.30 µA/kHz) f + IDD
IT = (3.55 µA/kHz) f + IDD
µAdc
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 7.) (CL = 50 pF, TA = 25C)
Characteristic Symbol VDD Min Typ
(Note 8.) Max Unit
Output Rise and Fall Time (Pin 13)
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL 5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q1, 8–Bypass (Pin 6) High
tPLH, tPHL = (1.7 ns/pF) CL + 1715 ns
tPLH, tPHL = (0.66 ns/pF) CL + 617 ns
tPLH, tPHL = (0.5 ns/pF) CL + 425 ns
tPLH,
tPHL 5.0
10
15
—
—
—
1800
650
450
3600
1300
1000
ns
Clock to Q1, 8–Bypass (Pin 6) Low
tPLH, tPHL = (1.7 ns/pF) CL + 3715 ns
tPLH, tPHL = (0.66 ns/pF) CL + 1467 ns
tPLH, tPHL = (0.5 ns/pF) CL + 1075 ns
tPLH,
tPHL 5.0
10
15
—
—
—
3.8
1.5
1.1
7.6
3.0
2.3
µs
Clock to Q16
tPHL, tPLH = (1.7 ns/pF) CL + 6915 ns
tPHL, tPLH = (0.66 ns/pF) CL + 2967 ns
tPHL, tPLH = (0.5 ns/pF) CL + 2175 ns
tPLH,
tPHL 5.0
10
15
—
—
—
7.0
3.0
2.2
14
6.0
4.5
µs
Reset to Qn
tPHL = (1.7 ns/pF) CL + 1415 ns
tPHL = (0.66 ns/pF) CL + 567 ns
tPHL = (0.5 ns/pF) CL + 425 ns
tPHL 5.0
10
15
—
—
—
1500
600
450
3000
1200
900
ns
Clock Pulse Width tWH 5.0
10
15
600
200
170
300
100
85
—
—
—
ns
Clock Pulse Frequency
(50% Duty Cycle) fcl 5.0
10
15
—
—
—
1.2
3.0
5.0
0.4
1.5
2.0
MHz
Clock Rise and Fall Time tTLH,
tTHL 5.0
10
15 No Limit —
Reset Pulse Width tWH 5.0
10
15
1000
400
300
500
200
150
—
—
—
ns
7. The formulas given are for the typical characteristics only at 25C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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PIN DESCRIPTIONS
INPUTS
SET (Pin 1) — A high on Set asynchronously forces
Decode Out to a high level. This is accomplished by setting
an output conditioning latch to a high level while at the same
time resetting the 24 flip–flop stages. After Set goes low
(inactive), the occurrence of the first negative clock
transition on IN1 causes Decode Out to go low. The
counter’s flip–flop stages begin counting on the second
negative clock transition of IN1. When Set is high, the
on–chip RC oscillator is disabled. This allows for very
low–power standby operation.
RESET (Pin 2) — A high on Reset asynchronously
forces Decode Out to a low level; all 24 flip–flop stages are
also reset to a low level. Like the Set input, Reset disables
the on–chip RC oscillator for standby operation.
IN1 (Pin 3) — The device’s internal counters advance on
the negative–going edge of this input. IN1 may be used as an
external clock input or used in conjunction with OUT1 and
OUT2 to form an RC oscillator. When an external clock is
used, both OUT1 and OUT2 may be left unconnected or
used to drive 1 LSTTL or several CMOS loads.
8–BYPASS (Pin 6) — A high on this input causes the first
8 flip–flop stages to be bypassed. This device essentially
becomes a 16–stage counter with all 16 stages selectable.
Selection is accomplished by the A, B, C, and D inputs. (See
the truth tables.)
CLOCK INHIBIT (Pin 7) — A high on this input
disconnects t h e first counter stage from the clocking source.
This holds the present count and inhibits further counting.
However, the clocking source may continue to run.
Therefore, when Clock Inhibit is brought low, no oscillator
start–up time is required. When Clock Inhibit is low, the
counter will start counting on the occurrence of the first
negative edge of the clocking source at IN1.
OSC INHIBIT (Pin 14) — A high level on this pin stops
the RC oscillator which allows for very low–power standby
operation. May also be used, in conjunction with an external
clock, with essentially the same results as the Clock Inhibit
input.
MONO–IN (Pin 15) — Used as the timing pin for the
on–chip monostable multivibrator. If the Mono–In input is
connected to VSS, the monostable circuit is disabled, and
Decode Out is directly connected to the selected Q output.
The monostable circuit is enabled if a resistor is connected
between Mono–In and VDD. This resistor and the device’s
internal capacitance will determine the minimum output
pulse widths. With the addition of an external capacitor to
VSS, the pulse width range may be extended. For reliable
operation the resistor value should be limited to the range of
5 kΩ to 100 kΩ and the capacitor value should be limited to
a maximum of 1000 pf. (See figures 3, 4, 5, and 10).
A, B, C, D (Pins 9, 10, 11, 12) — These inputs select the
flip–flop stage to be connected to Decode Out. (See the truth
tables.)
OUTPUTS
OUT1, OUT2 (Pin 4, 5) — Outputs used in conjunction
with IN1 to form an RC oscillator. These outputs are
buffered and may be used for 20 frequency division of an
external clock.
DECODE OUT (Pin 13) — Output function depends on
configuration. When the monostable circuit is disabled, this
output is a 50% duty cycle square wave during free run.
TEST MODE
The test mode configuration divides the 24 flip–flop
stages into three 8–stage sections to facilitate a fast test
sequence. The test mode is enabled when 8–Bypass, Set and
Reset are at a high level. (See Figure 8.)
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TRUTH TABLES
Input
Stage Selected
8–Bypass D C B A
Stage
Selected
for Decode Out
0 0 0 0 0 9
0 0 0 0 1 10
0 0 0 1 0 11
0 0 0 1 1 12
0 0 1 0 0 13
0 0 1 0 1 14
0 0 1 1 0 15
0 0 1 1 1 16
0 1 0 0 0 17
0 1 0 0 1 18
0 1 0 1 0 19
0 1 0 1 1 20
0 1 1 0 0 21
0 1 1 0 1 22
0 1 1 1 0 23
0 1 1 1 1 24
Input
Stage Selected
8–Bypass D C B A
Stage
Selected
for Decode Out
1 0 0 0 0 1
1 0 0 0 1 2
1 0 0 1 0 3
1 0 0 1 1 4
1 0 1 0 0 5
1 0 1 0 1 6
1 0 1 1 0 7
1 0 1 1 1 8
1 1 0 0 0 9
1 1 0 0 1 10
1 1 0 1 0 11
1 1 0 1 1 12
1 1 1 0 0 13
1 1 1 0 1 14
1 1 1 1 0 15
1 1 1 1 1 16
FUNCTION TABLE
In1Set Reset Clock
Inh OSC
Inh Out 1 Out 2 Decode
Out
0 0 0 0 No
Change
0 0 0 0 Advance to
next state
X 1 0 0 0 0 1 1
X 0 1 0 0 0 1 0
X 0 0 1 0 — — No
Change
X 0 0 0 1 0 1 No
Change
0 0 0 0 X 0 1 No
Change
1 0 0 0 Advance to
next state
X = Don’t Care
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LOGIC DIAGRAM
STAGES
18 THRU
23
2417
STAGES
10 THRU
15
16
T9
STAGES
2 THRU 7 8
T1
6
2
RESET
8-BYPASS
14
OSC INHIBIT
3
IN1
4
OUT 1
OUT 2 5
SET
17
CLOCK
INHIBIT
R
En
CS
Q
A9
B10
C11
D12
DECODER
DECODER
OUT
13
15
MONO-IN
VDD= PIN 16
VSS = PIN 8
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Figure 1. RC Oscillator Stability Figure 2. RC Oscillator Frequency as a
Function of RTC and C
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C
RS = 120 kΩ, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
RTC = 56 kΩ,
C = 1000 pF
VDD = 15 V
10 V
5.0 V
8.0
4.0
0
-4.0
-8.0
-12
-16
-55 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)*
*Device Only.
FREQUENCY DEVIATION (%)
TYPICAL RC OSCILLATOR CHARACTERISTICS
(For Circuit Diagram See Figure 11 In Application)
100
0.1
0.2
0.5
1.0
2.0
5.0
10
20
50
1.0 k 10 k 100 k 1.0 M
0.0001 0.001 0.01 0.1
RTC, RESISTANCE (OHMS)
C, CAPACITANCE (µF)
f, OSCILLATOR FREQUENCY (kHz)
f AS A FUNCTION
OF C
(RTC = 56 kΩ)
(RS = 120 k)
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS ≈ 2RTC)
VDD = 10 V
Figure 3. Typical CX versus Pulse Width
@ VDD = 5.0 V Figure 4. Typical CX versus Pulse Width
@ VDD = 10 V
100
0.1
1.0
10
1000100101.0
CX, EXTERNAL CAPACITANCE (pF)
, PULSE WIDTH (t Wµs)
RX = 100 kΩ
50 kΩ
10 kΩ
5 kΩ
TA = 25°C
VDD = 5 V
FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 RX • CX 0.85
WHERE R IS IN kΩ, CX IN pF.
1000100101.0
CX, EXTERNAL CAPACITANCE (pF)
100
0.1
1.0
10
, PULSE WIDTH (t Wµs)
FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 RX • CX 0.85
WHERE R IS IN kΩ, CX IN pF.
RX = 100 kΩ
50 kΩ
10 kΩ
5 kΩTA = 25°C
VDD = 10 V
Figure 5. Typical CX versus Pulse Width
@ VDD = 15 V
1000100101.0
CX, EXTERNAL CAPACITANCE (pF)
100
0.1
1.0
10
, PULSE WIDTH (t Wµs)
FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 RX • CX 0.85
WHERE R IS IN kΩ, CX IN pF.
RX = 100 kΩ
50 kΩ
10 kΩ
5 kΩTA = 25°C
VDD = 15 V
MONOSTABLE CHARACTERISTICS
(For Circuit Diagram See Figure 10 In Application)
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Figure 6. Power Dissipation Test
Circuit and Waveform Figure 7. Switching Time Test Circuit and Waveforms
VDD
0.01 µF
CERAMIC
500 µFID
CL
CL
CL
VSS
PULSE
GENERATOR
SET
RESET
8-BYPASS
IN1
C INH
MONO-IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT
20 ns 20 ns
90%
10% 50%
50%
DUTY CYCLE
PULSE
GENERATOR
SET
RESET
8-BYPASS
IN1
C INH
MONO-IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT CL
VSS
VDD
20 ns 20 ns
50%
IN1
tWL tWH
50%
tPHL
90%
10%
tPLH tTLH tTHL
OUT
FUNCTIONAL TEST SEQUENCE
Test function (Figure 8) has been included for the
reduction of test time required to exercise all 24 counter
stages. This test function divides the counter into three
8–stage sections and 255 counts are loaded in each of the
8–stage sections in parallel. All flip–flops are now at a “1”.
The counter is now returned to the normal 24–stages in
series configuration. One more pulse is entered into In1
which will cause the counter to ripple from an all “1” state
to an all “0” state.
Figure 8. Functional Test Circuit
VDD
VSS
PULSE
GENERATOR
SET
RESET
8-BYPASS
IN1
C INH
MONO-IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT
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FUNCTIONAL TEST SEQUENCE
Inputs Outputs Comments
In1Set Reset 8–Bypass Decade Out
Q1 thru Q24 All 24 stages are in Reset mode.
1 0 1 1 0
All
24
stages
are
in
Reset
mode
.
1 1 1 1 0 Counter is in three 8 stage sections in parallel mode.
0 1 1 1 0 First “1” to “0” transition of clock.
1
0
—
—
—
1 1 1 255 “1” to “0” transitions are clocked in the counter.
0 1 1 1 1 The 255 “1” to “0” transition.
0 0 0 0 1 Counter converted back to 24 stages in series mode.
Set and Reset must be connected together and simultaneously
go from “1” to “0”.
1 0 0 0 1 In1 Switches to a “1”.
0 0 0 0 0 Counter Ripples from an all “1” state to an all “0” state.
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NOTE: When power is first applied to the device, DECODE OUT can be either at a high or low state.
On the rising edge of a SET pulse the output goes high if initially at a low state. The output
remains high if initially at a high state. Because CLOCK INH is held high, the clock source
on the input pin has no effect on the output. Once CLOCK INH is taken low, the output goes
low on the first negative clock transition. The output returns high depending on the 8–BY-
PASS, A, B, C, and D inputs, and the clock input period. A 2n frequency division (where n
= the number of stages selected from the truth table) is obtainable at DECODE OUT. A
20–divided output of IN1 can be obtained at OUT1 and OUT2.
Figure 9. Time Interval Configuration Using an External Clock, Set,
and Clock Inhibit Functions
(Divide–by–2 Configured)
PULSE
GEN.
PULSE
GEN.
CLOCK
8-BYPASS
A
B
C
D
RESET
OSC INH
MONO-IN
SET
CLOCK INH
IN1VSS
DECODE OUT
OUT 2
OUT 1
8
16
+V
6
9
10
11
12
2
14
15
1
7
313
5
4
DECODE OUT
CLOCK INH
SET
IN1
POWER UP
VDD
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Figure 10. Time Interval Configuration Using an External Clock, Reset,
and Output Monostable to Achieve a Pulse Output
(Divide–by–4 Configured)
NOTE: When Power is first applied to the device with the RESET input going high, DECODE OUT initializes low. Bringing the
RESET input low enables the chip’s internal counters. After RESET goes low, the 2n/2 negative transition of the clock
input causes DECODE OUT to go high. Since the MONO–IN input is being used, the output becomes monostable. The
pulse width of the output is dependent on the external timing components. The second and all subsequent pulses occur
at 2n x (the clock period) intervals where n = the number of stages selected from the truth table.
PULSE
GEN.
CLOCK
8-BYPASS
A
B
C
D
RESET
SET
CLOCK INH
MONO-IN
OSC INH
IN1VSS
DECODE OUT
OUT 2
OUT 1
8
16
+V
6
9
10
11
12
2
1
7
15
14
313
5
4
DECODE OUT
RESET
IN1
POWER UP
VDD
RX
CX
*tw ≈.00247 • RX • CX0.85
tw in µsec
RX in kΩ
CX in pF
*tw
MC14536B
http://onsemi.com
13
Figure 11. Time Interval Configuration Using On–Chip RC Oscillator and
Reset Input to Initiate Time Interval
(Divide–by–2 Configured)
NOTE: This circuit is designed to use the on–chip oscillation function. The oscillator frequency is deter-
mined by the external R and C components. When power is first applied to the device, DECODE
OUT initializes to a high state. Because this output is tied directly to the OSC INH input, the oscillator
is disabled. This puts the device in a low–current standby condition. The rising edge of the RESET
pulse will cause the output to go low . This in turn causes OSC INH to go low. However , while RESET
is high, the oscillator is still disabled (i.e.: standby condition). After RESET goes low , the output re-
mains low for 2n/2 of the oscillator’s period. After the part times out, the output again goes high.
PULSE
GEN.
8-BYPASS
A
B
C
D
RESET
OSC INH
MONO-IN
SET
CLOCK INH
IN1VSS
DECODE OUT
OUT 2
OUT 1
8
16
+V
6
9
10
11
12
2
14
15
1
7
313
5
4
VDD
RS
RTC
C
OUT 2
OUT 1
RESET
POWER UP
Rs
F
R
C
DECODE OUT
tw
≥Rtc
= Hz
= Ohms
= FARADS
fosc 1
2.3RtcC
MC14536B
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14
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
HGD
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
SOIC–16
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–03
ISSUE B
D
14X
B16X
SEATING
PLANE
S
A
M
0.25 B S
T
16 9
81
hX 45
M
B
M
0.25
H8X
E
B
A
eT
A1
A
L
C
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D10.15 10.45
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
0 7
MC14536B
http://onsemi.com
15
PACKAGE DIMENSIONS
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
10 0
10
LEQ1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
MC14536B
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16
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