CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1993 9-13
SEMICONDUCTOR
DG200, DG201
CMOS Dual/Quad SPST Analog Switches
Description
The DG200 and DG201 solid state analog gates are
designed using an improved, high voltage CMOS monolithic
technology. They provide ease-of-use and performance
advantages not previously available from solid state
switches. Destructive latch-up of solid state analog gates
has been eliminated by Harris's CMOS technology.
The DG200 and DG201 are completely specification and
pinout compatible with the industry standard devices.
Ordering Information
PART NUMBER TEMPERATURE PACKAGE
DG200AA -55oC to +125oC 10 Pin Metal Can
DG200AK -55oC to +125oC 14 Lead Ceramic DIP
DG200BA -25oC to +85oC 10 Pin Metal Can
DG200BK -25oC to +85oC 14 Lead Ceramic DIP
DG200CJ 0oC to +70oC 14 Lead Plastic DIP
DG200AA/883B -55oC to +125oC 10 Pin Metal Can
DG200AK/883B -55oC to +125oC 14 Lead Ceramic DIP
DG201AK -55oC to +125oC 16 Lead Ceramic DIP
DG201BK -25oC to +85oC 16 Lead Ceramic DIP
DG201CJ 0oC to +70oC 16 Lead Plastic DIP
DG201AK/883B -55oC to +125oC 16 Lead Ceramic DIP
Features
• Switches Greater than 28V P-P Signals with±15 Supplies
• Break-Before-Make Switching tOFF 250ns, tON 700ns
Typical
• TTL, DTL, CMOS, PMOS Compatible
• Non-Latching with Supply Turn-Off
• Complete Monolithic Construction
• Industry Standard (DG200, DG201)
Applications
• Data Acquisition
• Sample and Hold Circuits
• Operational Amplifier Gain Switching Networks
December 1993
Pinouts
DG200
(CDIP, PDIP)
TOP VIEW
DG200
(TO-100 METAL CAN)
TOP VIEW
DG201
(CDIP, PDIP)
TOP VIEW
IN2
NC
GND
NC
S2
D2
V-
IN1
NC
V+ (SUBSTRATE)
NC
S1
D1
VREF
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+
D1
D2
S2
IN22
5
1
3
10
4
8
9
7
6
S1
VREF
V-
GND
IN1
(SUBSTRATE AND CASE)
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN1
D1
S1
V-
GND
S4
IN4
D4
IN2
S2
V+(SUBSTRATE)
VREF
S3
D3
IN3
D2
File Number 3115
9-14
DG200, DG201
Schematic Diagram
(1/2 DG200, 1/4 DG201)
Functional Diagram
DG200, DG201 SWITCH CELL
Q3
VREF
INPUT
GATE
PROTECTION
RESISTOR
Q4
V-
Q7
V+
Q8
Q5
Q10
Q12
V+
Q13
Q11 D1
S1
Q14
Q6
V-
Q9
Q15
Q1
Q2
NP
IN
S
D
9-15
Specifications DG200
Absolute Maximum Ratings Thermal Information
V+, V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V
V+ - VD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VD - V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VD - VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <28V
VIN - GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
Thermal Resistance θJA θJC
Ceramic DIP Package. . . . . . . . . . . . . . . 95oC/W 24oC/W
Plastic DIP Package . . . . . . . . . . . . . . . . 100oC/W -
Metal Can Package. . . . . . . . . . . . . . . . . 136oC/W 65oC/W
Operating Temperature Range
“A” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC
“B” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25oC to +85oC
“C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications (TA = +25oC, V+ = +15V, V- = -15V)
PARAMETER TEST CONDITIONS
MILITARY COMMERCIAL / INDUSTRIAL
UNITS-55oC +25oC +125oC0oC TO
-25oC +25oC+70oC TO
+85oC
Input Logic Current,
IIN(ON)
VIN = 0.8V (Notes 2, 3) ±10 ±1±10-±10 ±10 µA
Input Logic Current,
IN(OFF)
VIN = 2.4V (Notes 2, 3) ±10 ±1±10-±10 ±10 µA
Drain-Source On Resis-
tance, rDS(ON)
IS = 10mA, VANALOG =
±10V 70 70 100 80 80 100 Ω
Channel-to-Channel
rDS(ON) Match, rDS(ON)
- 25 (Typ) - - 30 (Typ) - Ω
Minimum Analog Signal
Handling Capability,
VANALOG
-±15V - - ±15V - V
Switch OFF Leakage
Current, ID(OFF)
VANALOG = -14V to +14V - ±2 100 - ±5100 nA
Switch OFF Leakage
Current, IS(OFF)
VANALOG = -14V to +14V - ±2 100 - ±5100 nA
Switch ON Leakage Cur-
rent, ID(ON) + IS(ON)
VD = VS = -14V to +14V - ±2 200 - ±10 200 nA
Switch “ON” Time
(Note 1), tON
RL = 1kΩ, VANALOG =
-10V to +10V (Figure 5) - 1.0 - - 1.0 - µs
Switch “OFF” Time, tOFF RL = 1kΩ, VANALOG =
-10V to +10V (Figure 5) - 0.5 - - 0.5 - µs
Charge Injection, Q(INJ.) Figure 6 - 15 (Typ) - - 20 (Typ) - mV
Minimum Off Isolation
Rejection Ratio, OIRR f = 1MHz, RL = 100Ω,
CL≤5pF
(Figure 7, Note 1)
- 54 (Typ) - - 50 (Typ) - dB
+Power Supply
Quiescent Current, IV1
VIN = 0V or VIN = 5V 1000 1000 2000 1000 1000 2000 µA
-Power Supply
Quiescent Current, IV2
1000 1000 2000 1000 1000 2000 µA
Minimum Channel to
Channel Cross Coupling
Rejection Ratio, CCRR
One Channel Off - 54 (Typ) - - 50 (Typ) - dB
NOTES:
1. Pull Down Resistor must be ≤2kΩ.
2. Typical values are for design aid only, not guaranteed and not subject to production testing.
3. All channels are turned off by high “1” logic inputs and all channels are turned on by low “0” inputs; however 0.8V to 2.4V describes the
minimum range for switching properly. Peak input current required for transition is typically -120µA.
9-16
Specifications DG201
Absolute Maximum Ratings Thermal Information
V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V
V+ to VD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VD to VS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <28V
VREF to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <33V
VREF to VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V
VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V
Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<30mA
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
Thermal Resistance θJA θJC
Ceramic DIP Package. . . . . . . . . . . . . . . 80oC/W 24oC/W
Plastic DIP Package . . . . . . . . . . . . . . . . 145oC/W -
Operating Temperature Range
“A” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC
“B” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25oC to +85oC
“C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications (TA = +25oC, V+ = +15V, V- = -15V)
PARAMETER TEST CONDITIONS
MILITARY COMMERCIAL / INDUSTRIAL
UNITS-55oC +25oC +125oC0oC TO
-25oC +25oC+70oC TO
+85oC
Input Logic Current,
IIN(ON)
VIN = 0.8V (Note 1) 10 ±110±1±110µA
Input Logic Current,
IN(OFF)
VIN = 2.4V (Note 1) 10 ±110±1±110µA
Drain-Source On Resis-
tance, rDS(ON)
IS = 10mA, VANALOG =
±10V 80 80 125 100 100 125 Ω
Channel-to-Channel
rDS(ON) Match, rDS(ON)
- 25 (Typ) - - 30 (Typ) - Ω
Minimum Analog Signal
Handling Capability,
VANALOG
-±15 (Typ) - - ±15 (Typ) - V
Switch OFF Leakage
Current, ID(OFF)
VANALOG = -14V to +14V - ±1 100 - ±5100 nA
Switch OFF Leakage
Current, IS(OFF)
VANALOG = -14V to +14V - ±1 100 - ±5100 nA
Switch ON Leakage Cur-
rent, ID(ON) + IS(ON)
VD = VS = -14V to +14V - ±2 200 - ±5 200 nA
Switch “ON” Time
(Note 2), tON
RL = 1kΩ, VANALOG =
-10V to +10V (Figure 5) - 1.0 - - 1.0 - µs
Switch “OFF” Time
(Note 2), tOFF
RL = 1kΩ, VANALOG =
-10V to +10V (Figure 5) - 0.5 - - 0.5 - µs
Charge Injection, Q(INJ.) Figure 6 - 15 (Typ) - - 20 (Typ) - mV
Minimum Off Isolation
Rejection Ratio, OIRR f = 1MHz, RL = 100Ω,
CL≤5pF, (Figure 7) - 54 (Typ) - - 50 (Typ) - dB
+Power Supply
Quiescent Current, I+Q
VIN = 0V or VIN = 5V 2000 1000 2000 2000 1000 2000 µA
-Power Supply
Quiescent Current, I-Q
2000 1000 2000 2000 1000 2000 µA
Minimum Channel to
Channel Cross Coupling
Rejection Ratio, CCRR
One Channel Off - 54 (Typ) - - 50 (Typ) - dB
NOTES:
1. Typical values are for design aid only, not guaranteed and not subject to production testing.
2. All channels are turned off by high “1” logic inputs and all channels are turned on by low “0” inputs; however 0.8V to 2.4V describes the
minimum range for switching properly. Peak input current required for transition is typically -120µA.
9-17
DG200, DG201
Performance Curves
FIGURE 1. RDS(ON) vs VD AND TEMPERATURE FIGURE 2. rDS(ON) vs VD AND POWER SUPPLY VOLTAGE
FIGURE 3. ID(ON) vs TEMPERATURE FIGURE 4. IS(OFF) OR ID(OFF) vs TEMPERATURE
100
50
0
-15 -10 -5 0 5 10 15
DRAIN SOURCE ON RESISTANCE (Ω)
DRAIN VOLTAGE (V)
+125oC
+25oC
-55oC
V+ = +15V
V- = -15V 100
50
0
-15 -10 -5 0 5 10 15
DRAIN SOURCE ON RESISTANCE (Ω)
DRAIN VOLTAGE (V)
A
B
C
D
A: V+ = +15V, V- = -15V
B: V+ = +12V, V- = -12V
C: V+ = +10V, V- = -10V
D: V+ = +8V, V- = -8V
10
1
0.1
0.01
CHANNEL ON LEAKAGE CURRENT (nA)
25 45 65 85 105 125
TEMPERATURE (oC)
10
1
0.1
0.01
SOURCE OR DRAIN OFF LEAKAGE CURRENT (nA)
25 45 65 85 105 125
TEMPERATURE (oC)
DG201 (16 LEAD DIP)
PIN SYMBOL DESCRIPTION
1IN
1Logic control for switch 1
2D
1Drain (output) terminal for switch 1
3S
1Source (input) terminal for switch 1
4 V- Negative power supply terminal
5 GND Ground terminal (Logic Common)
6S
4Source (input) terminal for switch 4
7D
4Drain (output) terminal for switch 4
8IN
4Logic control for switch 4
9IN
3Logic control for switch 3
10 D3Drain (output) terminal for switch 3
11 S3Source (input) terminal for switch 3
12 VREF Logic reference voltage
13 V+ Positive power supply terminal (substrate)
14 S2Source (input) terminal for switch 2
15 D2Drain (output) terminal for switch 2
16 IN2Logic control for switch 2
Pin Description
DG200 (14 LEAD DIP)
PIN SYMBOL DESCRIPTION
1IN
2Logic control for switch 2
2 NC No Connection
3 GND Ground Terminal (Logic Common)
4 NC No Connection
5S
2Source (input) terminal for switch 2
6D
2Drain (output) terminal for switch 2
7 V- Negative power supply terminal
8V
REF Logic reference voltage
9D
1Drain (output) terminal for switch 1
10 S1Source (input) terminal for switch 1
11 NC No Connection
12 V+ Positive power supply terminal (substrate)
13 NC No Connection
14 IN1Source (input) terminal for switch 1
9-18
DG200, DG201
Test Circuits
FIGURE 5. FIGURE 6.
FIGURE 7.
0V
3V
LOGIC
INPUT
ANALOG
INPUT 10V
≤2kΩ10pF
VOUT
1kΩ
NOTE: All channels are turned off by high “1” logic inputs and
all channels are turned on by low “0” inputs; however 0.8V to
2.4V describes the minimum range for switching properly.
Peak input current required for transition is typically -120µA.
0V
3V
LOGIC
INPUT
ANALOG
INPUT 10V
10,000pF
VOUT
VOUT
100Ω
2VP-P AT 1MHz
LOGIC
INPUT * 51Ω
* Pull Down Resistor must be ≤ 2kΩ.
Typical Applications
Using the VREF Terminal
The DG200 and DG201 have an internal voltage divider set-
ting the TTL threshold on the input control lines for V+ equal
to +15V. The schematic shown in Figure 8 with nominal
resistor values, gives approximately 2.4V on the VREF pin.
As the TTL input signal goes from +0.8V to +2.4V, Q1 and
Q2 switch states to turn the switch ON and OFF.
FIGURE 8.
V+ (+15V)
Q1
31kΩ
VREF
6kΩ
REXT
Q2
GATE
PROTECTION
RESISTOR
INPUT
If the power supply voltage is less than +15V, then a resistor
must be added between V+ and the VREF pin, to restore
+2.4V at VREF. The table shows the value of this resistor for
various supply voltages, to maintain TTL compatibility. If
CMOS logic levels on a +5V supply are being used, the
threshold shifts are less critical, but a separate column of
suitable values is given in the table. For logic swings of -5V
to + 5V, no resistor is needed.
In general, the “low” logic level should be <0.8V to prevent
Q1 and Q2 from both being ON together (this will cause
incorrect switch function).
TABLE 1.
V+ SUPPLY (V) TTL RESISTOR
(kΩ)CMOS RESISTOR
(kΩ)
+15 - -
+12 100 -
+10 51 -
+9 (34) 34
+8 (27) 27
+7 18 18
9-19
DG200
Metallization Topology
DIE DIMENSIONS:
74 x 77 x 14 ± 1mils
METALLIZATION:
Type: Al
Thickness: 10kű1kÅ
GLASSIVATION:
Type: SiO2/Si3N4
SiO2 Thickness: 7kű 1.4kÅ
Si3N4 Thickness: 8kű 1.2kÅ
WORST CASE CURRENT DENSITY:
1 x 105 A/cm2
Metallization Mask Layout
DG200
S1 (10)
V- (SUBSTRATE)* (12)
V-
(7)
D1
(9)
(5) S2
(6)
(14)
IN1
(1)
IN2
(3)
GND
D2
* Backside of Chip is V+
9-20
DG201
Metallization Topology
DIE DIMENSIONS:
94 x 101 x 14 ± 1mils
METALLIZATION:
Type: Al
Thickness: 10kű1kÅ
GLASSIVATION:
Type: SiO2/Si3N4
SiO2 Thickness: 7kű 1.4kÅ
Si3N4 Thickness: 8kű 1.2kÅ
WORST CASE CURRENT DENSITY:
1 x 105 A/cm2
Metallization Mask Layout
DG201
S1 (3)
V- (4)
GND (5)
S4 (6)
IN2
(16)
IN1
(1)
D1
(2)
(11) S3
(13) V+ (SUBSTRATE)*
(14) S2
(15)
(7)
D4
(8)
IN4
(9)
IN3
(10)
D3
D2
* Backside of Chip is V+
