REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD13280
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
FEATURES
Dual, 80 MSPS Minimum Sample Rate
Channel-to-Channel Matching, 1% Gain Error
90 dB Channel-to-Channel Isolation
DC-Coupled Signal Conditioning
80 dB Spurious-Free Dynamic Range
Selectable Bipolar Inputs (1 V and 0.5 V Ranges)
Integral Single-Pole Low Pass Nyquist Filter
Two’s Complement Output Format
3.3 V Compatible Outputs
1.85 W per Channel
Industrial and Military Grade
APPLICATIONS
Radar Processing (Optimized for I/Q Baseband Operation)
Phased Array Receivers
Multichannel, Multimode Receivers
GPS Antijamming Receivers
Communications Receivers
Dual Channel, 12-Bit, 80 MSPS A/D Converter
with Analog Input Signal Conditioning
PRODUCT DESCRIPTION
The AD13280 is a complete dual channel signal processing
solution, including on-board amplifiers, references, ADCs, and
output termination components to provide optimized system
performance. The AD13280 has on-chip track-and-hold circuitry
and utilizes an innovative multipass architecture to achieve 12-bit,
80 MSPS performance. The AD13280 uses innovative high
density circuit design and laser-trimmed thin-film resistor networks
to achieve exceptional channel matching, impedance control,
and performance while still maintaining excellent isolation,
and providing for significant board area savings.
Multiple options are provided for driving the analog input,
including single-ended, differential, and optional series filtering.
The AD13280 also offers the user a choice of analog input
signal ranges to further minimize additional external signal
conditioning, while still remaining general-purpose.
The AD13280 operates with ±5.0 V for the analog signal condi-
tioning with a separate 5.0 V supply for the analog-to-digital
conversion, and 3.3 V digital supply for the output stage. Each
channel is completely independent, allowing operation with
independent encode and analog inputs, and maintaining minimal
crosstalk and interference.
The AD13280 is packaged in a 68-lead ceramic gull wing
package. Manufacturing is done on Analog Devices’ MIL-38534
Qualified Manufacturers Line (QML), and components are
available up to Class-H (–40°C to +85°C). The components are
manufactured using Analog Devices’ high speed complementary
bipolar process (XFCB).
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 80 MSPS.
2. Input signal conditioning included; gain and impedance match.
3. Single-ended, differential, or off-module filter options.
4. Fully tested/characterized full channel performance.
5. Compatible with 14-bit (up to) 65 MSPS family.
FUNCTIONAL BLOCK DIAGRAM
100 OUTPUT TERMINATORS
TIMING 3
9 12
VREF
DROUT
12
ENC
ENC D9A D10A D11A
(MSB)
D0B
(LSB)
D1B D3BD2B D4B D5B D6B
D7B
D8B
TIMING
D9B
7
5
ENC
ENC
B–IN
D10B
D11B (MSB)
(LSB) D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
AD13280
DROUTA
100 OUTPUT TERMINATORS
AMP-IN-B-2 AMP-IN-B-1
AMP-IN-A-2 AMP-IN-A-1
AMP-OUT-A
A–IN
A+IN B+IN
AMP-OUT-B
DROUTB
DROUT
VREF
REV. A
–2–
AD13280–SPECIFICATIONS
(AVCC = +5 V, AVEE = –5 V, DVCC = +3.3 V; applies to each ADC with Front-End
Amplifier, unless otherwise noted.)
Test Mil AD13280AZ/BZ
Parameter Temp Level Subgroup Min Typ Max Unit
RESOLUTION 12 Bits
DC ACCURACY
1
No Missing Codes Full IV 12 Guaranteed
Offset Error 25°CI 1 –2.2 ±1.0 +2.2 % FS
Full VI 2, 3 –2.2 ±1.0 +2.2 % FS
Offset Error Channel Match Full VI 1, 2, 3 –1.0 ±0.1 +1.0 %
Gain Error
2
25°CI 1 –3 –1.0 +1 % FS
Full VI 2, 3 –5.0 ±2.0 +5.0 % FS
Gain Error Channel Match 25°CI 1 –1.5 ±0.5 +1.5 %
Max VI 2 –3.0 ±1.0 +3.0 %
Min VI 3 –5 ±1.0 +5 %
SINGLE-ENDED ANALOG INPUT
Input Voltage Range
AMP-IN-X-1 Full V ±0.5 V
AMP-IN-X-2 Full V ±1.0 V
Input Resistance
AMP-IN-X-1 Full IV 12 99 100 101 Ω
AMP-IN-X-2 Full IV 12 198 200 202 Ω
Capacitance 25°CV 4.0 7.0 pF
Analog Input Bandwidth
3
Full V 100 MHz
DIFFERENTIAL ANALOG INPUT
Analog Signal Input Range
A+IN to A–IN and B+IN to B–IN
4
Full V ±1V
Input Impedance 25°CV 618 Ω
Analog Input Bandwidth Full V 50 MHz
ENCODE INPUT (ENC, ENC)
1
Differential Input Voltage Full IV 12 0.4 V p-p
Differential Input Resistance 25°CV 10 kΩ
Differential Input Capacitance 25°CV 2.5 pF
SWITCHING PERFORMANCE
Maximum Conversion Rate
5
Full VI 4, 5, 6 80 MSPS
Minimum Conversion Rate
5
Full IV 12 20 MSPS
Aperture Delay (t
A
)25°CV 1.5 ns
Aperture Delay Matching 25°CIV 12 250 500 ps
Aperture Uncertainty (Jitter) 25°CV 0.3 ps rms
ENCODE Pulsewidth High at Max Conversion Rate 25°CIV12 4.75 6.25 8 ns
ENCODE Pulsewidth Low at Max Conversion Rate 25°CIV12 4.75 6.25 8 ns
Output Delay (t
OD
)Full V 5 ns
Encode, Rising to Data Ready, Rising Delay Full V 8.5 ns
SNR
1, 6
Analog Input @ 10 MHz 25°CI 4 66.5 70 dBFS
Min II 6 64.5 dBFS
Max II 5 66.3 dBFS
Analog Input @ 21 MHz 25°CI 4 66.5 70 dBFS
Min II 6 64 dBFS
Max II 5 66.3 dBFS
Analog Input @ 37 MHz 25°CI 46365 dBFS
Min II 6 61.5 dBFS
Max II 5 63 dBFS
SINAD
1, 7
Analog Input @ 10 MHz 25°CI 46669 dBFS
Min II 6 63.5 dBFS
Max II 5 66 dBFS
Analog Input @ 21 MHz 25°CI 46468.5 dBFS
Min II 6 63 dBFS
Max II 5 64 dBFS
Analog Input @ 37 MHz 25°CI 45459 dBFS
Min II 6 53 dBFS
Max II 5 54 dBFS
REV. A –3–
AD13280
Test Mil AD13280AZ/BZ
Parameter Temp Level Subgroup Min Typ Max Unit
S
PURIOUS-FREE DYNAMIC RANGE
1, 8
Analog Input @ 10 MHz 25°CI 47580 dBFS
Min II 6 70
Max II 5 75
Analog Input @ 21 MHz 25°CI 46875 dBFS
Min II 6 67
Max II 5 67
Analog Input @ 37 MHz 25°CI 45662 dBFS
Min II 6 55
Max II 5 55
SINGLE-ENDED ANALOG INPUT
Pass-Band Ripple to 10 MHz 25°CV 0.05 dB
Pass-Band Ripple to 25 MHz 25°CV 0.1 dB
DIFFERENTIAL ANALOG INPUT
Pass-Band Ripple to 10 MHz 25°CV 0.3 dB
Pass-Band Ripple to 25 MHz 25°CV 0.82 dB
TWO-TONE IMD REJECTION
9
f
IN
= 9.1 MHz and 10.1 MHz 25°CI 4 75 80 dBc
f
1
and f
2
are –7 dB Min II 6 71
Max II 5 74
f
IN
= 19.1 MHz and 20.7 MHz 25°CV 4 77 dBc
f
1
and f
2
are –7 dB
f
IN
= 36 MHz and 37 MHz 25°CV 4 60 dBc
f
1
and f
2
are –7 dB
CHANNEL-TO-CHANNEL ISOLATION
10
25°CIV 12 90 dB
TRANSIENT RESPONSE 25°CV 25 ns
DIGITAL OUTPUTS
11
Logic Compatibility CMOS
DVCC = 3.3 V
Logic “1” Voltage Full I 1, 2, 3 2.5 DVCC – 0.2 V
Logic “0” Voltage Full I 1, 2, 3 0.2 0.5 V
DVCC = 5 V
Logic “1” Voltage Full V DVCC – 0.3 V
Logic “0” Voltage Full V 0.35 V
Output Coding Two’s Complement
POWER SUPPLY
AV
CC
Supply Voltage
12
Full IV 4.85 5.0 5.25 V
I (AV
CC
) Current Full I 1, 2, 3 310 338 mA
AV
EE
Supply Voltage
12
Full IV –5.25 –5.0 –4.75 V
I (AV
EE
) Current Full I 1, 2, 3 38 49 mA
DV
CC
Supply Voltage
12
Full IV 3.135 3.3 3.465 V
I (DV
CC
) Current Full I 1, 2, 3 34 46 mA
I
CC
(Total) Supply Current per Channel Full I 1, 2, 3 369 433 mA
Power Dissipation (Total) Full I 1, 2, 3 3.72 4.05 W
Power Supply Rejection Ratio (PSRR) Full V 0.01 % FSR/% V
S
NOTES
1
All ac specifications tested by driving ENCODE and ENCODE differentially. Single-ended input: AMP-IN-X-1 = 1 V p-p, AMP-IN-X-2 = GND.
2
Gain tests are performed on AMP-IN-X-1 input voltage range.
3
Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4
For differential input: +IN = 1 V p-p and –IN = 1 V p-p (signals are 180° out of phase). For single-ended input: +IN = 2 V p-p and = –IN = GND.
5
Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.
6
Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 80 MSPS. SNR is reported
in dBFS, related back to converter full scale.
7
Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 80 MSPS. SINAD is reported in dBFS,
related back to converter full scale.
8
Analog Input signal at –1 dBFS; SFDR is the ratio of converter full scale to worst spur.
9
Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.
10
Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B Channel.
11
Digital output logic levels: DV
CC
= 3.3 V, C
LOAD
= 10 pF. Capacitive loads >10 pF will degrade performance.
12
Supply voltage recommended operating range. AV
CC
may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AV
CC
= 5.0 V
to 5.25 V.
Specifications subject to change without notice.
REV. A
AD13280
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD13280 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL
1
AV
CC
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V
AV
EE
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V to 0 V
DV
CC
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . V
EE
to
V
CC
Analog Input Current . . . . . . . . . . . . . . –10 mA to +10 mA
Digital Input Voltage (ENCODE) . . . . . . . . . . . . . 0 to V
CC
ENCODE, ENCODE Differential Voltage . . . . . . . . 4 V max
Digital Output Current . . . . . . . . . . . . . . –10 mA to +10 mA
ENVIRONMENTAL
2
Operating Temperature (Case) . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 175°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Storage Temperature Range (Ambient) . . –65°C to +150°C
NOTES
1
Absolute maximum ratings are limiting values applied individually, and beyond
which the serviceability of the circuit may be impaired. Functional operability is not
necessarily implied. Exposure to absolute maximum rating conditions for an
extended period of time may affect device reliability.
2
Typical thermal impedance for “ES” package:
JC
2.2°C/W;
JA
24.3°C/W.
ORDERING GUIDE
Model Temperature Range (Case) Package Description Package Option
AD13280AZ –25°C to +85°C68-Lead Ceramic Leaded Chip Carrier ES-68C
AD13280AF –25°C to +85°C68-Lead Ceramic Leaded Chip Carrier ES-68C
with Nonconductive Tie-Bar
5962-0053001HXA –40°C to +85°C68-Lead Ceramic Leaded Chip Carrier ES-68C
AD13280/PCB 25°CEvaluation Board with AD13280AZ
TEST LEVEL
I. 100% Production Tested
II. 100% Production Tested at 25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III. Sample Tested Only
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI. 100% production tested with temperature at 25°C; sample
tested at temperature extremes.
REV. A
AD13280
–5–
PIN FUNCTION DESCRIPTIONS
Pin Number Mnemonic Function
1, 35 SHIELD Internal Ground Shield between Channels
2, 3, 9, 10, 13, 16 AGNDA A Channel Analog Ground. A and B grounds should be connected as close to the device as possible.
4A–IN Inverting Differential Input (Gain = 1)
5A+IN Noninverting Differential Input (Gain = 1)
6AMP-OUT-A Single-Ended Amplifier Output (Gain = 2)
7AMP-IN-A-1 Analog Input for A Side ADC (Nominally ±0.5 V)
8AMP-IN-A-2 Analog Input for A Side ADC (Nominally ±1.0 V)
11 AV
EE
AA Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V)
12 AV
CC
AA Channel Analog Positive Supply Voltage (Nominally 5.0 V)
14 ENCODEA Complement of Encode; Differential Input
15 ENCODEA Encode Input; Conversion Initiated on Rising Edge
17 DV
CC
AA Channel Digital Positive Supply Voltage (Nominally 5.0 V/ 3.3 V)
18, 19, 37, 38 NC No Connect
20–25, 28–33 D0A–D11A Digital Outputs for ADC A. D0 (LSB)
26, 27 DGNDA A Channel Digital Ground
34 DROUTA Data Ready A Output
36 DROUTB Data Ready B Output
39–42, 45–52 D0B–D11B Digital Outputs for ADC B. D0 (LSB)
43, 44 DGNDB B Channel Digital Ground
53 DV
CC
BB Channel Digital Positive Supply Voltage (Nominally 5.0 V/ 3.3 V)
54, 57, 60, 61, 67, 68 AGNDB B Channel Analog Ground. A and B grounds should be connected as close to the device as possible.
55 ENCODEB Encode Input. Conversion initiated on rising edge.
56 ENCODEB Complement of Encode. Differential input.
58 AV
CC
BB Channel Analog Positive Supply Voltage (Nominally 5.0 V)
59 AV
EE
BB Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V)
62 AMP-IN-B-2 Analog Input for B Side ADC (Nominally ±1.0 V)
63 AMP-IN-B-1 Analog Input for B Side ADC (Nominally ±0.5 V)
64 AMP-OUT-B Single-Ended Amplifier Output (Gain = 2)
65 B+IN Noninverting Differential Input (Gain = 1)
66 B–IN Inverting Differential Input (Gain = 1)
PIN CONFIGURATION
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
21
27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42
9618765 686766656463624321
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD13280
AGNDB
AVEEB
AVCCB
AGNDB
D10A
DROUTB
AGNDA
AVEEA
D0A(LSB)
D1A
D2A
D3A
D4A
D5A
AGNDB
ENCODEB
ENCODEB
DVCCB
D0B(LSB)
AGNDA
AGNDA
AMP-OUT-A
A+IN
A–IN
AGNDA
AMP-IN-A-2
AMP-IN-A-1
AGNDB
SHIELD
D1B
D2B
D3B
DGNDA
D11B(MSB)
D10B
D9B
DGNDB
AVCCA
AGNDB
B–IN
B+IN
AGNDB
AMP-IN-B-2
AMP-OUT-B
AMP-IN-B-1
D8B
D7B
D6B
D5B
D4B
DGNDB
NC
SHIELD
DROUTA
D11A(MSB)
D8A
D9A
D7A
D6A
DGNDA
ENCODEA
ENCODEA
AGNDA
AGNDA
DVCCA
NC
NC
NC = NO CONNECT
NC
REV. A
AD13280
–6–
FREQUENCY – MHz
–130 0
ENCODE = 80MSPS
AIN = 5MHz (–1dBFS)
SNR = 69.4dBFS
SFDR = 81.9dBc
5101520 2530
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
2
35 40
6
3
45
dB
TPC 1. Single Tone @ 5 MHz
FREQUENCY – MHz
–130 0
ENCODE = 80MSPS
AIN = 18MHz (–1dBFS)
SNR = 69.79dBFS
SFDR = 76.81dBc
5101520 2530
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
35 40
dB
TPC 2. Single Tone @ 18 MHz
FREQUENCY – MHz
–130 05101520 2530
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
35 40
ENCODE = 80MSPS
AIN = 9MHz AND
10MHz (–7dBFS)
SFDR = 82.77dBc
dB
TPC 3. Two Tone @ 9 MHz/10 MHz
ENCODE = 80MSPS
AIN = 10MHz (–1dBFS)
SNR = 69.19dBFS
SFDR = 79.55dBc
FREQUENCY – MHz
–130 05101520 2530
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
2
35 40
6
3
4
5
dB
TPC 4. Single Tone @ 10 MHz
ENCODE = 80MSPS
AIN = 37MHz (–1dBFS)
SNR = 68.38dBFS
SFDR = 57.81dBc
FREQUENCY – MHz
–130 05101520 2530
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
2
35 40
6
3
4
5
dB
TPC 5. Single Tone @ 37 MHz
ENCODE = 80MSPS
AIN = 19MHz AND
20MHz (–7dBFS)
SFDR = 74.41dBc
FREQUENCY – MHz
–130 05101520 2530
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
35 40
dB
TPC 6. Two Tone @ 19 MHz/20 MHz
–Typical Performance Characteristics
REV. A
AD13280
–7–
–1.0
0512
ENCODE = 80MSPS
DNL MAX = 0.688 CODES
DNL MIN = 0.385 CODES
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
1024 1536 2048 2560 3072 3584 4096
LSB
TPC 7. Differential Nonlinearity
FREQUENCY – MHz
1.0 3.5
dBFS
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
6.0 8.5 11.0 13.5 16.0 18.5 21.0 23.5 26.0
ENCODE = 80MSPS
ROLL-OFF = 0.0459dB
TPC 8. Pass-Band Ripple to 25 MHz
–3
ENCODE = 80MSPS
INL MAX = 0.562 CODES
INL MIN = 0.703 CODES
–2
0
2
3
1
–1
0512 1024 1536 2048 2560 3072 3584 4096
LSB
TPC 9. Integral Nonlinearity
REV. A
AD13280
–8–
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between a differential crossing of the ENCODE
and ENCODE command and the instant at which the analog
input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to the
converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage from the other pin,
which is 180 degrees out of phase. Peak-to-peak differential is
computed by rotating the inputs phase 180 degrees and taking
the peak measurement again. The difference is then computed
between both peak measurements.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic “1” state to achieve
rated performance; pulsewidth low is the minimum time the
ENCODE pulse should be left in low state. At a given clock
rate, these specs define an acceptable encode duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of the ENCODE
and ENCODE command and the time when all output data
bits are within valid logic levels.
Overvoltage Recovery Time
The amount of time required for the converter to recover to
0.02% accuracy after an analog input signal of the specified
percentage of full scale is reduced to midscale.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc. May be reported
in dB (i.e., degrades as signal level is lowered) or in dBFS
(always related back to converter full scale).
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc. May be reported
in dB (i.e., degrades as signal level is lowered) or in dBFS
(always related back to converter full scale).
Spurious-Free Dynamic Range
The ratio of the rms signal amplitude to the rms value of the peak
spurious spectral component. The peak spurious component may
or may not be a harmonic.
Transient Response
The time required for the converter to achieve 0.02% accuracy when
a one-half full-scale step function is applied to the analog input.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
t
A
AIN
ENC, ENC
D[11:0]
DRY
N
N+1
N+2
N+3
N+4
NN+1 N+2 N+3 N+4
N–3 N–2 N–1 N
t
ENCL
t
ENCH
t
ENC
t
E_DR
t
OD
Figure 1. Timing Diagram
REV. A
AD13280
–9–
AMP-IN-X-1
100
100
TO AD8037
AMP-IN-X-2
Figure 2. Single-Ended Input Stage
LOADS
LOADS
ENCODE
10k
10k
ENCODE
AV
CC
AV
CC
10k
10k
AV
CC
AV
CC
Figure 3. ENCODE Inputs
CURRENT MIRROR
CURRENT MIRROR
DR OUT
DVCC
VREF
DVCC
Figure 4. Digital Output Stage
CURRENT MIRROR
CURRENT MIRROR
D0–D11
100
DVCC
VREF
DVCC
Figure 5. Digital Output Stage
THEORY OF OPERATION
The AD13280 is a high dynamic range 12-bit, 80 MHz pipeline
delay (three pipelines) analog-to-digital converter. The custom
analog input section provides input ranges of 1 V and 2 V p-p
and input impedance configurations of 50 Ω, 100 Ω, and 200 Ω.
The AD13280 employs four monolithic ADI components per
channel (AD8037, AD8138, AD8031, and a custom ADC IC),
along with multiple passive resistor networks and decoupling
capacitors to fully integrate a complete 12-bit analog-to-digital
converter.
In the single-ended input configuration, the input signal is passed
through a precision laser-trimmed resistor divider allowing
the user to externally select operation with a full-scale signal of
±0.5 V or ±1.0 V by choosing the proper input terminal for the
application. The result of the resistor divider is to apply a full-scale
input approximately 0.4 V to the noninverting input of the internal
AD8037 amplifier.
The AD13280 analog input includes an AD8037 amplifier
featuring an innovative architecture that maximizes the dynamic
range capability on the amplifier’s inputs and outputs. The
AD8037 amplifier provides a high input impedance and gain for
driving the AD8138 in a single-ended to differential amplifier
configuration. The AD8138 has a –3 dB bandwidth at 300 MHz
and delivers a differential signal with the lowest harmonic
distortion available in a differential amplifier. The AD8138
differential outputs help balance the differential inputs to the
custom ADC, maximizing the performance of the device.
The AD8031 provides the buffer for the internal reference analog-
to-digital converter. The internal reference voltage of the custom
ADC is designed to track the offsets and drifts and is used to
ensure matching over an extended temperature range of operation.
The reference voltage is connected to the output common-mode
input on the AD8138. This reference voltage sets the output
common mode on the AD8138 at 2.4 V, which is the midsupply
level for the ADC.
The custom ADC has complementary analog input pins, AIN
and AIN. Each analog input is centered at 2.4 V and should
swing ±0.55 V around this reference. Since AIN and AIN are
180 degrees out of phase, the differential analog input signal is
2.2 V peak-to-peak. Both analog inputs are buffered prior to the
first track-and-hold.
The custom ADC digital outputs drive 100 Ω series resistors
(Figure 5). The result is a 12-bit parallel digital CMOS-compatible
word, coded as two’s complement.
USING THE SINGLE-ENDED INPUT
The AD13280 has been designed with the user’s ease of opera-
tion in mind. Multiple input configurations have been included
on-board to allow the user a choice of input signal levels and
input impedance. The standard inputs are ±0.5 V and 1.0 V.
The user can select the input impedance of the AD13280 on any
input by using the other inputs as alternate locations for the
GND. The following chart summarizes the impedance options
available at each input location.
AMP-IN-X-1 = 100 Ω when AMP-IN-X-2 is open.
AMP-IN-X-1 = 50 Ω when AMP-IN-X-2 is shorted to GND.
AMP-IN-X-2 = 200 Ω when AMP-IN-X-1 is open.
Each channel has two analog inputs AMP-IN-A-1 and AMP-IN-A-2
or AMP-IN-B-1 and AMP-IN-B-2. Use AMP-IN-A-1 or
REV. A
AD13280
–10–
AMP-IN-B-1 when an input of ±0.5 V full scale is desired. Use
AMP-IN-A-2 or AMP-IN-B-2 when ±1 V full scale is desired. Each
channel has an AMP-OUT that must be tied to either a noninver-
ting or inverting input of a differential amplifier with the remaining
input grounded. For example, Side A, AMP-OUT-A (Pin 6) must
be tied to A+IN (Pin 5) with A–IN (Pin 4) tied to ground for
noninverting operation or AMP-OUT-A (Pin 6) tied to A–IN
(Pin 4) with A+IN (Pin 5) tied to ground for inverting operation.
USING THE DIFFERENTIAL INPUT
Each channel of the AD13280 was designed with two optional
differential inputs, A+IN, A–IN and B+IN, B–IN. The inputs
provide system designers with the ability to bypass the AD8037
amplifier and drive the AD8138 directly. The AD8138 differen-
tial ADC driver can be deployed in either a single-ended or
differential input configuration. The differential analog inputs
have a nominal input impedance of 620 Ω and nominal full-
scale input range of 1.2 V p-p. The AD8138 amplifier drives a
differential filter and the custom analog-to-digital converter. The
differential input configuration provides the lowest even-order
harmonics and signal-to-noise (SNR) performance improvement
of up to 3 dB (SNR = 73 dBFS). Exceptional care was taken in
the layout of the differential input signal paths. The differential
input transmission line characteristics are matched and balanced.
Equal attention to system level signal paths must be provided in
order to realize significant performance improvements.
APPLYING THE AD13280
Encoding the AD13280
The AD13280 encode signal must be a high quality, extremely
low phase noise source, to prevent degradation of performance.
Maintaining 12-bit accuracy at 80 MSPS places a premium on
encode clock phase noise. SNR performance can easily degrade
3 dB to 4 dB with 37 MHz input signals when using a high jitter
clock source. See Analog Devices’ Application Note AN-501,
Aperture Uncertainty and ADC System Performance, for complete
details. For optimum performance, the AD13280 must be clocked
differentially. The encode signal is usually ac-coupled into the
ENCODE and ENCODE pins via a transformer or capacitors.
These pins are biased internally and require no additional bias.
Figure 6 shows one preferred method for clocking the AD13280.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD13280 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to the other portions of the AD13280, and limits the
noise presented to the ENCODE inputs. A crystal clock oscillator
can also be used to drive the RF transformer if an appropriate
limited resistor (typically 100 Ω) is placed in the series with
the primary.
T1-4T
100
0.1F
ENCODE
ENCODE
AD13280
HSMS2812
DIODES
CLOCK
SOURCE
Figure 6. Crystal Clock Oscillator—Differential Encode
If a low jitter ECL/PECL clock is available, another option is to
ac-couple a differential ECL/PECL signal to the encode input
pins as shown below. A device that offers excellent jitter perfor-
mance is the MC100LVEL16 (or same family) from Motorola.
ENCODE
ENCODE
AD13280
0.1F
ECL/PECL
VT
VT
0.1F
Figure 7. Differential ECL for Encode
Jitter Consideration
The signal-to-noise ratio (SNR) for any ADC can be predicted.
When normalized to ADC codes, Equation 1 accurately predicts
the SNR based on three terms. These are jitter, average DNL error,
and thermal noise. Each of these terms contributes to the noise
within the converter.
SNR f t V
NANALOG rms
NOISE rms
N
=× +
()
+×× × +
⁄
– log ( )20 1
222
2
212
επJ
(1)
f
ANALOG
=analog input frequency
t
J
rms
=rms jitter of the encode (rms sum of encode source
and internal encode circuitry)
ε=average DNL of the ADC (typically 0.50 LSB)
N=number of bits in the ADC
V
NOISE
rms
=the analog input of the ADC (typically 5 LSB)
For a 12-bit analog-to-digital converter like the AD13280, aperture
jitter can greatly affect the SNR performance as the analog fre-
quency is increased. The chart below shows a family of curves that
demonstrates the expected SNR performance of the AD13280
as jitter increases. The chart is derived from Equation 1.
For a complete discussion of aperture jitter, please consult Analog
Devices’ Application Note AN-501, Aperture Uncertainty and
ADC System Performance.
CLOCK JITTER – ps
0.0
0.2
0.6
1.0
1.4
1.8
2.2
2.6
3.0
3.4
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
SNR – –dBFS
60
AIN = 5MHz
AIN = 10MHz
AIN = 20MHz
AIN = 37MHz
61
62
63
64
65
66
67
68
69
70
71
59
58
3.8
4.0
Figure 8. SNR vs. Jitter
REV. A
AD13280
–11–
Power Supplies
Care should be taken when selecting a power source. Linear supplies
are strongly recommended. Switching supplies tend to have radiated
components that may be “received” by the AD13280. Each of
the power supply pins should be decoupled as closely as possible
to the package, using 0.1 µF chip capacitors.
The AD13280 has separate digital and analog power supply
pins. The analog supplies are denoted AV
CC
and the digital
supply pins are denoted DV
CC
. AV
CC
and DV
CC
should be
separate power supplies because the fast digital output swings
can couple switching current back into the analog supplies.
Note that AV
CC
must be held within 5% of 5 V. The AD13280
is specified for DV
CC
= 3.3 V as this is a common supply for
digital ASICs.
Output Loading
Care must be taken when designing the data receivers for the
AD13280. The digital outputs drive an internal series resistor
(e.g., 100 Ω) followed by a gate like 75LCX574. To minimize
capacitive loading, there should be only one gate on each output
pin. An example of this is shown in the evaluation board schematic
(Figure 9). The digital outputs of the AD13280 have a constant
output slew rate of 1 V/ns. A typical CMOS gate combined with
a PCB trace will have a load of approximately 10 pF. Therefore,
as each bit switches, 10 mA (10 pF × 1 V ÷ 1 ns) of dynamic current
per bit will flow in or out of the device. A full-scale transition can
cause up to 120 mA (12 bits × 10 mA/bit) of transient current
through the output stages. These switching currents are confined
between ground and the DV
CC
pin. Standard TTL gates should
be avoided since they can appreciably add to the dynamic switching
currents of the AD13280. It should also be noted that extra capacitive
loading will increase output timing and invalidate timing specifi-
cations. Digital output timing is guaranteed with 10 pF loads.
EVALUATION BOARD
The AD13280 evaluation board (Figure 9) is designed to
provide optimal performance for evaluation of the AD13280
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD13280. The board requires an analog input signal, encode
clock, and power supply inputs. The clock is buffered on-board
to provide clocks for the latches. The digital outputs and out
clocks are available at the standard 40-pin connectors J1 and J2.
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the associated components and the
analog section of the AD13280. The digital outputs of the
AD13280 are powered via banana jacks with 3.3 V. Contact the
factory if additional layout or applications assistance is required.
LAYOUT INFORMATION
The schematics of the evaluation board (Figures 10a–10c) repre-
sent a typical implementation of the AD13280. The pinout of the
AD13280 is very straightforward and facilitates ease of use and
the implementation of high frequency/high resolution design prac-
tices. It is recommended that high quality ceramic chip capacitors
be used to decouple each supply pin to ground directly at the device.
All capacitors can be standard high quality ceramic chip capacitors.
Care should be taken when placing the digital output runs. Because
the digital outputs have such a high slew rate, the capacitive load-
ing on the digital outputs should be minimized. Circuit traces for
the digital outputs should be kept short and connect directly to
the receiving gate. Internal circuitry buffers the outputs of the
ADC through a resistor network to eliminate the need to exter-
nally isolate the device from the receiving gate.
Figure 9. Evaluation Board Mechanical Layout
REV. A
AD13280
–12–
Bill of Materials List for Evaluation Board
Qty. Component Name Ref/Des Value Description Manufacturing Part Number
274LCX16373MTD U7, U8 Latch 74LCX16373MTD (Fairchild)
1AD13280AZ U1 AD13280 AD13280AZ
2ADP3330 U5, U6 Regulator ADP3330ART-3.3RL7
10 BJACK BJ1–BJ10 Banana Jacks 108-0740-001 (Johnson Components)
2BRES0805 R41, R53 25 Ω0805 SM Resistor ERJ-6GEYJ 240V
4BRES0805 R38, R39, R55, R56 33 kΩ0805 SM Resistor ERJ-6GEYJ 333V
28 CAP2 C1, C2, C5–C10, 0.1 µF0805 SM Capacitor GRM 40X7R104K025BL
C12, C16–C18,
C20–C26, C28,
C30–C38
2CAP2 C13, C27 0.47 µF0805 SM Capacitor VJ1206U474MFXMB
2H40DM J1, J2 2 × 20 40 Pin Male Connector TSW-120-08-G-D
6IND2 L1–L6 47 ΩSM Inductor 2743019447
4MC10EL16 U2, U4, U9, U11 Clock Drivers MC1016EP16D
2MC100ELT23 U4, U10 ECL/TTL Clock Drivers SY100ELT23L
8POLCAP2 C3, C4, C11, C14, 10 µFTantalum Polar Caps T491C106M016A57280
C15, C19, C29, C30
4RES2 R47–R50 0 Ω0805 SM Resistor ERJ-6GEY OR 00V
6RES2 R1, R2, R5, R7, R8, R54 50 Ω0805 SM Resistor ERJ-6GEYJ 510V
36 RES2 R3, R4, R6, R9, R12–R15, 100 Ω0805 SM Resistor ERJ-6GEYJ 101V
R19–R28, R31–R36, R37,
R42, R43, R44–R46 R51, R52
12 SMA J3–J14 SMA Connectors 142-0701-201
4Standoff Standoff 313-2477-016 (Johnson Components)
4Screws Screws (Standoff) MPMS 004 0005 PH (Building Fasteners)
1PCB AD13280 Eval Board (Rev. B) GS03361
REV. A
AD13280
–13–
AGNDA
10
AGNDA
11
12
–5VAA
13 +5VAA
14
D0A(LSB)
15
D1A
16
D2A
17
D3A
18
D4A
19
D5A
20
21
22
23
24
25
DGNDA
26
AGNDB 60
59
58
AGNDB
57
56
55
54
53
ENCBB
52
ENCB
51
+3.3VDB
50
D11B(MSB)
49
D7B 48
D6B 47
D5B 46
D4B 45
DGNDB 44
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
AGNDA
AMP IN A 2
A+IN
A–IN
AGNDA
SHIELD
AGNDB
AGNDB
D10A
D11A(MSBA)
SHIELD
DRBOUT
NC
NC
D1B
D2B
D3B
DGNDB
U1
AD13280
D1A
D2A
D3A
D4A
D5A
D0A
DGNDA
AGNDA
AGNDA
ENCAB
NC
NC
ENCA
AGNDA
+3VDA
NC0A
NC1A
AGNDA
ENCA
ENCAB
–5VAA
C9
0.1F
C10
0.1F
C36
0.1F
OUT 3.3VDA
C34
0.1F
+5VAA
AGNDA
AGNDA
C35
0.1F
AGNDA
AMP IN A 1
AMP OUT A
AGNDA
AGNDB
B–IN
B+IN
AMP OUT B
AMP IN B 1
AMP IN B 2
–5.2VAB
+5VAB
DGNDA
AGNDB
D8B
D9B
D10B
D0B(LSBB)
DRAOUT
D9A
D8A
D7A
D6A
DGNDA
D10A
D11A
DRBOUT
NC0B
NC1B
D1B
D2B
D3B
DGNDB
D0B
DRAOUT
D9A
D8A
D7A
D6A
DGNDA
E56 E55
LIDB E65
E48 E40
DGNDA DGNDB
E69 E70
E49
AGNDA
E51
E50
E72
E74
E77 E75
E73
E71
J4
SMA
AGNDA
J3
SMA
E76
E78
E83
E81
E79
AGNDA
J9
SMA
AGNDA
J13
SMA AGNDA
E68 E66 AGNDB
E54
E53 J7
SMA
AGNDB
E86E85
E52
AGNDB
AGNDB
J14
SMA
AGNDB
J8
SMA
AGNDB
J6
SMA
DGNDB
–5VAB
C33
0.1F
C18
0.1F
C37
0.1F
OUT 3.3VDB
C17
0.1F
+5VAB
AGNDB
AGNDB
C38
0.1F
AGNDB
AGNDB
ENCBB
ENCB
D11B
D7B
D6B
D5B
D4B
DGNDB
AGNDB
D8B
D9B
D10B
E67
LIDA
E80
E82
E84
NC = NO CONNECT
L1
C29
10F
+3VDA
U7
C62
0.1F
47
20%
@100MHz
DGNDA
DUT 3.3VDA
BJ10
1
L2
C30
10F
+3VDB
U8
C16
0.1F
47
20%
@100MHz
DGNDB
DUT 3.3VDB
BJ9
1
L3
C3
10F
+3VAA
U1
C20
0.1F
47
20% @100MHz
AGNDA
+5VAA
BJ6
1
AGNDA
L4
C4
10F
+5VAB
U1
C21
0.1F
47
20%@100MHz
AGNDB
+5VAB
BJ5
1
AGNDB
L5
C11
10F
–5VAA
U1
C32
0.1F
47
20%@100MHz
AGNDA
–5VAA
BJ2
1
AGNDA
L6
C19
10F
–5VAB
U1
C31
0.1F
47
20%@100MHz
AGNDB
–5VAB
BJ1
1
AGNDB
Figure 10a. Evaluation Board
REV. A
AD13280
–14–
MSB B11B
B10B
B9B
B8B
B7B
B6B
F1B
DGNDB
F2B
LSB B0B
B1B
B2B
B3B
DGNDB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
B5B
B4B
C14
10F
BUFLATB
R2
50
E64
E63 E62
DRAOUT
3.3VDB
DGNDB
J2
H40DN
F3B
F0B
U7
29
30
31
32
33
34
35
36
37
38
39
40
43
44
45
46
47
48
41
42
R11, DNI
25
26
27
28 113
112
VCC
111
110
GND
19
18
17
16
GND
15
13
12
GND
11
10
14
VCC
LE2
115
114
GND
O13
O12
VCC
O11
O10
GND
O9
O8
O7
O6
GND
O5
O3
O2
GND
O1
O0
O4
VCC
OE2
O15
O14
GND
20
19
18
17
16
15
14
13
12
11
10
9
6
5
4
3
2
1
8
7
24
23
22
21
DUT 3.3VDB
DGNDB
DGNDB
DGNDB
DUT 3.3VDB
DGNDB
DGNDB
R10, DNI
R30, DNI
R29, DNI
R28, 100
R27, 100
R26, 100
R12, 100
R9, 100
R35, 100
R34, 100
R33, 100
R32, 100
R31, 100
R25, 100
LE1 OE1
DUT 3.3VDB
DGNDB
DGNDB
DGNDB
DUT 3.3VDB
DGNDB
R49
0
R50
0
DGNDB
R8
50LATCHB
E57
NC0B
NC1B
LSB D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B
MSB D11B
F0B
F1B
F2B
F3B
B0B (LSB)
B1B
B2B
B3B
B4B
B5B
B6B
B7B
B8B
B9B
B10B
B11B (MSB)
DGNDB
74LCX16374
R36, 100
MSB B11A
B10A
B9A
B8A
B7A
B6A
F1A
DGNDA
F2A
LSB B0A
B1A
B2A
B3A
DGNDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
B5A
B4A
C15
10F
BUFLATA
R5
50
E61
E60 E59
DRAOUT
3.3VDA
DGNDA
H40DM
J1
F3A
F0A
U8
29
30
31
32
33
34
35
36
37
38
39
40
43
44
45
46
47
48
41
42
R18, DNI
25
26
27
28 113
112
VCC
111
110
GND
19
18
17
16
GND
15
13
12
GND
11
10
14
VCC
LE2
115
114
GND
O13
O12
VCC
O11
O10
GND
O9
O8
O7
O6
GND
O5
O3
O2
GND
O1
O0
O4
VCC
OE2
O15
O14
GND
20
19
18
17
16
15
14
13
12
11
10
9
6
5
4
3
2
1
8
7
24
23
22
21
DUT 3.3VDA
DGNDA
DGNDA
DGNDA
DUT 3.3VDA
DGNDA
DGNDA
R17, DNI
R40, DNI
R44, DNI
R45, 100
R46, 100
R15, 100
R14, 100
R13, 100
R24, 100
R23, 100
R22, 100
R21, 100
R20, 100
R19, 100
R15, 100
LE1 OE1
DUT 3.3VDA
DGNDA
DGNDA
DGNDA
DUT 3.3VDA
DGNDA
R47
0
R48
0
DGNDA
R7
50LATCHA
E58
NC0A
NC1A
LSB D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D9A
D10A
MSB D11A
F0A
F1A
F2A
F3A
B0A (LSB)
B1A
B2A
B3A
B4A
B5A
B6A
B7A
B8A
B9A
B10A
B11A (MSB)
DGNDA
74LCX16374
Figure 10b. Evaluation Board
REV. A
AD13280
–15–
NC = NO CONNECT
VCC
Q
VEE
NC
D
VBB
U2
MC10EL16
AGNDA
1
2
3
4
8
7
6
5
OUT
NR
IN
SD
U5
3
5
1
ERR
GND
4
ADP3330
5
AGNDA
DB QB
C13
0.47F
+3.3VA C7
0.1F
C8
0.1F
ENCAB
ENCA
AGNDA
R43
100
AGNDA
R56
33k
NC = NO CONNECT
VCC
Q
VEE
NC
D
VBB
U3
MC10EL16
1
2
3
4
8
7
6
5
DB QB
NC = NO CONNECT
VCC
Q0
VEE
NC
D
VBB
U4
MC100EPT23
1
2
3
4
8
7
6
5
DB Q1
+3.3VDA
C6
0.47F
R55
33k
DGNDA
C2
0.1F
R41
25
J12
SMA
J5
ENCODE
SMA
R1
50
C1
0.1F
AGNDA
AGNDA
AGNDA
DGNDA
DGNDA
AGNDA
R3
100
R4
100
DGNDA
DGND
C5
0.47F
+3.3VDA
LATCHA
BUFLATA
E23
E19
+5VAA
R42
100
2
E17
E27
E25
E21
E32
E44
E42
E10
E33
E6
E18
E28
E26
E20
E31
E43
E41
E9
E34
E5
DGNDA AGNDA
E38
E29
E1
E36
E14
E37
E30
E2
E35
E13
DGNDB AGNDB
SO1
SO2
SO4
SO5
SO6
E45
E3
E46
E4
SO3
E15
E7
E16
E12
DGNDA DGNDB
E11
E39
E8
E47
DGNDA DGNDB
AGNDB
1
BJ3
AGNDA
1
BJ4
DGNDB
1
BJ7
DGNDB
DGNDA
1
BJ8
DGNDA
NC = NO CONNECT
VCC
Q
VEE
NC
D
VBB
U11
MC10EL16 AGNDB
1
2
3
4
8
7
6
5
OUT
NR
IN
SD
U6
3
5
1
ERR
GND
4
ADP3330
5
AGNDB
DB QB
C27
0.47F
+3.3VB C24
0.1F
C28
0.1F
ENCBB
ENCB
AGNDB
R52
100
AGNDA
R38
33k
NC = NO CONNECT
VCC
Q
VEE
NC
D
VBB
U9
MC10EL16
1
2
3
4
8
7
6
5
DB QB
NC = NO CONNECT
VCC
Q0
VEE
NC
D
VBB
U10
MC100EPT23
1
2
3
4
8
7
6
5
DB Q1
+3.3VDB
C25
0.47F
R39
33k
DGNDB
C23
0.1F
R53
25
J11
SMA
J10
ENCODE
SMA
R54
50
C22
0.1F
AGNDB
AGNDB
AGNDB
DGNDB
DGNDB
DGNDB
R37
100
DGNDB
DGNDB
C26
0.1F
+3.3VDA
LATCHB
BUFLATB
E24
E22
+5VAB
R51
100
2
R6
100
Figure 10c. Evaluation Board
REV. A
AD13280
–16–
Figure 11a. Top Silk
Figure 11b. Top Layer
REV. A
AD13280
–17–
Figure 11c. GND1
Figure 11d. GND2
REV. A
AD13280
–18–
Figure 11e. Bottom Silk
Figure 11f. Bottom Layer
REV. A
AD13280
–19–
OUTLINE DIMENSIONS
68-Lead Ceramic Leaded Chip Carrier with Nonconductive Tie-Bar
(ES-68C)
Dimensions shown in inches and (millimeters)
DETAIL A
0.010 (0.254)
30
0.050 (1.27)
0.020 (0.508)
0.175 (4.45)
MAX
0.235 (5.97)
MAX
DETAIL A 0.010 (0.25)
0.008 (0.20)
0.007 (0.18)
PIN 1
TOP VIEW
(PINS DOWN)
0.800 (20.32)
BSC
0.960 (24.38)
0.950 (24.13) SQ
0.940 (23.88)
0.055 (1.40)
0.050 (1.27)
0.045 (1.14)
0.020 (0.508)
0.017 (0.432)
0.014 (0.356)
0.040 (1.02)
45
0.015 (0.3)
45
3 PLS
0.040 (1.02) R
TYP
0.350
(8.89)
TYP
2.000
(50.80)
TYP
REV. A
–20–
C02386–0–8/02(A)
PRINTED IN U.S.A.
AD13280
Revision History
Location Page
8/02–Data Sheet changed from REV. 0 to REV. A.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Packages updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
OUTLINE DIMENSIONS
68-Lead Ceramic Leaded Chip Carrier [CLCC]
(ES-68C)
Dimensions shown in inches and (millimeters)
TOE DOWN
ANGLE
0–8 DEGREES
0.010 (0.254)
30
0.050 (1.27)
0.020 (0.508)
DETAIL A
ROTATED 90 CCW
1.190 (30.23)
1.180 (29.97) SQ
1.170 (29.72)
PIN 1
10 26
9
61
60
43
27
44
TOP VIEW
(PINS DOWN)
0.800
(20.32)
BSC
0.960 (24.38)
0.950 (24.13) SQ
0.940 (23.88)
0.055 (1.40)
0.050 (1.27)
0.045 (1.14)
0.020 (0.508)
0.017 (0.432)
0.014 (0.356)
0.175 (4.45)
MAX
0.235 (5.97)
MAX
DETAIL A
0.010 (0.25)
0.008 (0.20)
0.007 (0.18)
0.060 (1.52)
0.050 (1.27)
0.040 (1.02)
1.070
(27.18)
MIN
