FARRIS SEMICONDUCTOR A DIVISION OF HARRIS CORPORATION ~ 2048-Bit Field Programmable Bipolar PROM FEATURES DESCRIPTION : The HM-7620 (open collector) and HM-7621 (three- e 512 Words, 4 Bits per Word state) are fully decoded, high speed, 2048-bit programm- e@Simple, High Speed Programming Procedure (2 Seconds) able ROMS organized as 512 words by 4 bits per word. Inputs and Outputs TTL Compatible They are supplied with all bits storing a logical 1 (out- puts high), and can be selectively programmed for a >Low Input Current - 400 uA Logic "0", 404A Logic "1" logical 0" (outputs low). >Full Output Drive - 15mA Sink/2mA Source The nichrome fuse technology is the same as is used in the @ Fast Access Time - 70ns Over Commercial Temperature JAN approved MIL 38510/201 PROM, and in ail other Harris PROMS. & Voltage, 85ns Over Military Temperature & Voltage The field programmabie PROM can be custom program- @ Expandable - Wired-Or" Outputs With Chip Select med to any pattern using a simple programming pro- cedure. Schottky Bipolar circuitry provides extremely fast access time, and features temperature and voltage compensation to minimize variations in access time. @ Upward Pin Compatibility With 256 x 4 Proms The pinout is compatible with the industry standard > Ss 256x4 PROM with the exception that the CS? input on be pin 14 is replaced by Address Input A8. Systems using = PACKAGE 256 x 4 PROMS can be upgraded to store twice the num- CODE 1D 16 LEAD CERAMIC D.I.P. ber of bits within the same board area, while maintaining the same system power requirements. Alternatively, both ALL DIMENSIONS IN INCHES. the package count and the system power can be halved by 8765 432 1] iwoey ALL DIMENSIONS +.010 UNLESS using the HM-7620/HM-7621 in place of the 256 x 4 2 NOTCH OTHERWISE SHOWN. PROM 910 11 12 13:14 18 16 9 ja = 80CMW STILL AIR In addition to the conventional storage array, two test 1 300 = rows and two test columns are included to assure high = ae [== programmability, and guarantee parametric and A.C. per- tI oy formance. These fuses are blown prior to shipment. ozowwn. {| {| I | js "ae 100 OWS O03 FI ge on BLOCK DIAGRAM Ag Ag Ag Ag AT Ag (4) (3) (25) 14} Veec = PIN (16) A i L t GND =PIN( 8 ADDRESS diss buss 0 G 64 X 16 1 OF 64 64X16 MEMORY ROW MEMORY ARRAY &3 DECODER 83 ARRAY ce J 14 ra Ta x > avoress | | 10F8 [| 10F8 te oF 8 . od aurrens [7i5e| COLUMN 1 Secones DECODER GECODER ts, 43) { ) e 9) 110) a (12) 4 03 0 Oy Me-32SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Stresses above those listed under the Absolute Maxi- Output or Supply Voltage (Operating) 7.0V mum Rating may cause permanent damage to the de- Address/Enable Input Voltage 6.8V vice. This is a stress only rating and functional opera- Address/Enable Input Current ~20mA tion of the device at these or at any other condition Output Sink Current 70m/A above those indicated in the operational sections of Storage Temperature . +150 this specification is not implied. (While programming, berating lesen yee follow the programming specifications.) aximum ELECTRICAL CHARACTERISTICS (OPERATING) HM-7620-5 HM-7621-5 Vec 5V +5% 5V +5% TA 0C to +70C 0C to +70C TEST PARAMETER SYMBOL } MIN. TYP. | MAX. | MIN. TYP. MAX. | UNITS CONDITIONS Address/Enable T'l Ips. IRE 0 40 0 40 MA Vin = Voc Max Input Current O"') pa, leg -0.1 -0.4 -0.1 -0.4 mA Vii = 0.45V Input Threshold "TT Vig 2.0 2.0 Vv Voc = VecMin Voltage o" Vib 0.8 0.8 v Vee = Ve cMax Output Voltage TT Von N/A 24 3.4 V oy =-2.0mA Veg = VocMin O") Vor 0.35 0.45 0.35 0.45 Vv lo = t15mA, Vee = VeeMin Output Disabled "Vl lQHE 108 100 BA | Vou. Voc = Vec max D.C. Current O"l loLE N/A -100 BA | VoL =+0.3V, Voc = Veg Max Output Leakage my lou 100 N/A BA Vou. Vec = Ver Max Power Supply lec 90 130 90 130 mA Voc = Voc Max Current All Inputs Grounded Input Clamp Voltage Vet | -1.5 -1.5 Vv lig = -10ma Output Short Circuit los N/A N/A 15 23 30 mA Veco = Voc Max. Vout = 0.0V Current One output only for a Max of 1 sec Ac Address Acces Time taa 40 70 40 70 ns Vcc and Ta Over Full Range Enable Access Time tea 15 25 16 25 ns Vcc and Tg Over Full Range Typical Measurements are at Ta = 25C, Veco = +5V HM-7620-2 HM-7621-2 Vee 5V +10% BV +10% TA ~55C to +1269C -559C to +125C TEST PARAMETER SYMBOL | MIN. TYP. MAX. | MIN. TYP. MAX. | UNITS CONDITIONS Address/Enable TT (pa, lpeE 0 *40 0 *40 BA Vin = Ver Max Input Current "O"| leg, lee 01 1*-0.4 01 |*-0.4 mA | Vy, = 0.45V Input Threshold TE Vig 2.0 2.0 Vv Vec= Vec Mia Voltage OT Vit 0.8 0.8 Vv Vec = Mec Max Output Voltage T') Voy N/A *2.4 3.4 Vv lon = -2.0mA; Veg =Viec Min O") Vor 035 | *0.45 0.35 |*0.45 V | Igy =+18mA; Vee =Veg Min D.C, Output Disabled V") lgHe *100 *100 BA | Von. Voc = Vee Max Current O") love N/A 100 BA | Voz = +0.3V, Voc = Veg Max Output Leakage "T) Toy *100 N/A BA Vow: Vee = Vec Max Power Supply Current lec 90 *130 90 *130 mA Vec = Vcc Max All Inputs Grounded Input Clamp Voltage Vet *15 15 Vo} lig = -10ma Output Short Circuit los N/A N/A 15 23 *30 mA Veco = Voc Max, Vout = 0.0V Current One output only for a Max of 1 sec AC Address Access Time taA 40 *35 40 *35 ns Veg and Ta Over Full Range Enable Access Time tea 15 *30 15 *30 ns Vec and Tg Over Full Range Typical Measurements are at Ta = 25C, Voc = +5V *100% Tested For DASH 8 CAPACITANCE (1): T, = 25C PARAMETER | SYMBOL | TYP. | UNITS | TEST CONDITIONS Add. Input Cap. Cin a. CS 8 pF Vcc = 5V, Vin = 2.0V, f= IMHz Output Cap. Cout 8 pF Vec = 5V, Vout = 2.0V, f= IMHz NOTE: (1) These parameters are only periodically sampled and are not 100% tested. Me-33SWITCHING TIME DEFINITIONS A.C. TEST LOAD | 1 I ADDRESS 15v IE Lv! : i 0.0V ; tea tea_-!' [. uf lo ta cn | | | OUTPUT 15V KE 0 OUTPUT isv fisv ' tp, te < SNS *Includes jig & probe total capacitance PROGRAMMING The HM-7620/7621 is manufactured with all bits/outputs Logical 1 (Output High). Any desired bit/output can be pro- grammed to a Logical 0 (Output Low) by following the simple procedure shown below. One may build his own programmer to satisfy the specifications described in Table 1, or buy any of the commercially available programmers which meet these spec- ifications. The HM-7620/7621 can be programmed automatically or by the manual procedure shown below. PROGRAMMING SPECIFICATIONS SCHEMATIC DIAGRAMS HM-7620 RECOM- +5.0V MEND PARAMETER SYMBOL MIN. | VALUE | MAX. | UNITS Address Input VIH 2.4 5.0 5.0 Vv , - e Voltage (1) Vit 0.0 0.4 0.8 V FROM 10F Ox : ; 8 COLUMN OQ a Programming/Verify Veu 11.5 12.0 12.5 V DECODE Core TTT 7 Oo Voltage to Vcc Vey 3.75 4.0 4.25 I | = t 1 = Programming ( | Voltage Current lece 600 mA I | Limit (2) TO OR-TIE | ortors | Programming (Vcc) ' 1 1 10 ! cocumn | Voltage Rise and r us | oecove | Fall Time ty 1 1 10 HS = L= = qj Programming oT PROGAMMING CIRCUITRY td 10 10 100 MS Delay OPEN COLLECTOR OUTPUT Programming Pulse Width - tp1 100 100 200 Us First Attempts HM-7621 Programming Pulse Width - tp2 10 10 20 ms +5.0V Subsequent Programming Duty Cycle Output Voltage Enable Vope 9.5 10.0 10.5 V seam 108 Disable (3) Vopp 0 45 5.8 V 8 COLUMN O * Output Voltage DEGODE ey mee 3 lop 10 mA Enable Current Limit Ore Case Temp Tc 75 oC ! P . Toor-rie | 1. Address and chip select should not be left open for V 44). or 10F8 | 2. Verification at Voc = 4.0 + .25 Volts, Ta = 25C is + coumn | recommended to guardband performance over full tem- TO CHIP - DECODE perature and voltage range. SELECT (= = J 3. Disable condition will be met with output open circuit. THREE-STATE OUTPUT PROGRAMMING CIRCUITRY Me-34PROGRAMMING PROCEDURE Address the PROM with the binary address of the selected word to be programmed. Address inputs are TTL compatible. An open circuit should not be used to address the PROM. Disable the chip by applying an input high (Vj})) to programmed. The output enable pulses must be separated by a minimum interval of tq. Return VCC to 4.0 .25 V following a delay of ty from the last programming enable pulse applied to an output. Enable the PROM for verification by applying a the chip select input. The chip select input is TTL compatible. An open circuit should not be used to 9 disable the chip. 3. Disable the programming circuitry by applying an Output Voltage Disable of less than V gpp to the out- put of the PROM. The output may be left open cir- cuit to achieve the disable. 4. Raise Voc to Vpyy with rise time equal to t,. logic 0 (V;,) to the CSq input. (f any bit does not verify as programmed, repeat steps 2 through using an output pulse enable width of tot for up to 15 additional pulses to enhance program- ming speed. If the bit is still unprogrammed, follow with at least 16 repetitive pulses of tp2 in width, to achieve high programming yield. In the event that the bit is still unprogrammed, the part is considered a pro- gramming reject and should be returned to the factory. The address and incorrect and desired contents of a location in which a programming faiiure has occured in any returned device must be included with that return. Repeat steps 1 thru 9 for all other bits to be pro- grammed in the PROM. 5. After a delay equal to or greater than ty, apply a pulse with amplitude equal to Vgpg and duration of tp1 to the output selected for programming. Note that the PROM is supplied with fuses intact generating an output high. Programming a fuse will cause the out- put to go low in the verify mode. 10. 6. Other bits in the same word may be programmed while the Vc input is raised to Vpy by applying output enable pulses to each output which is to be RECOMMENDED PROGRAMMING CIRCUIT The circuit and timing diagram shown in Figures 1 and 2 will establish the proper programming conditian for the output enable pulse. This allows the use of standard TTL parts for all logic inputs to the PROM. Note the gate which senses the output must be input protected to withstand input up to 12.5 Volts during programming. Vp cs, Ag DATA-4 ll >0 Vpy-------- We ny ot le > Ay 490% Ate > Ay Voc wf, i\u DATA-3 Ye, _ y! 1 _ A3 1 et it ha r ) jot ___ bane ty ee! l AS DATA-2 4 | ' \ Ag DATA1 ! r P ' Aq | | Ag DATA-1 ___ | jy t 8 DATA-2 cst ; HIGH VOLTAGE | | TTL GATE DATA-3 LS i 1 I SENCE GATE DATAS l_t-" 7 =|Io FIGURE 2 04 FIGURE 1 Me-36