LTC2488
1
2488fb
For more information www.linear.com/LTC2488
RSOURCE (Ω)
1
+FS ERROR (ppm)
–20
0
20
1k 100k
2488 TA01b
–40
–60
–80 10 100 10k
40
60
80 VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
CIN = 1µF
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
16-Bit 2-/4-Channel ΔS
ADC with Easy Drive Input
Current Cancellation
The LT C
®
2488 is a 4-channel (2-channel differential),
16-bit, No Latency ΔS™ ADC with Easy Drive™ technology.
The patented sampling scheme eliminates dynamic input
current errors and the shortcomings of on-chip buffering
through automatic cancellation of differential input current.
This allows large external source impedances and rail-to-
rail input signals to be directly digitized while maintaining
exceptional DC accuracy.
The LTC2488 includes an integrated oscillator. This device
can be configured to measure an external signal from
combinations of 4 analog input channels operating in single
ended or differential modes. It automatically rejects line
frequencies of 50Hz and 60Hz simultaneously.
The LTC2488 allows a wide common mode, input range
(0V to VCC), independent of the reference voltage. Any
combination of single-ended or differential inputs can
be selected and the first conversion after a new channel
selection is valid.
Data Acquisition System
n Up to 2 Differential or 4 Single-Ended Inputs
n Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
n Directly Digitizes High Impedance Sensors with
Full Accuracy
n 600nV RMS Noise (0.02LSB Transition Noise)
n GND to VCC Input/Reference Common Mode Range
n Simultaneous 50Hz/60Hz Rejection
n 2ppm INL, No Missing Codes
n 1ppm Offset and 15ppm Full-Scale Error
n No Latency: Digital Filter Settles in a Single Cycle,
Even After a New Channel is Selected
n Single Supply 2.7V to 5.5V Operation (0.8mW)
n Internal Oscillator
n Tiny 4mm × 3mm DFN Package
n Direct Sensor Digitizer
n Direct Temperature Measurement
n Instrumentation
n Industrial Process Control
Fullscale Error vs Source Resistance
SDI
SCK
SDO
CS
FO
REF+
VCC
2.7V TO 5.5V
10µF
COM
REF–
16-BIT ΔΣ ADC
WITH EASY DRIVE
4-CHANNEL
MUX
IN+
IN–
2488 TA01a
4-WIRE
SPI INTERFACE
CH0
CH1
CH3
CH2
0.1µF
OSC
L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and
No Latency ΔS and Easy Drive are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
LTC2488
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For more information www.linear.com/LTC2488
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) ................................... –0.3V to 6V
Analog Input Voltage
(CH0 to CH3, COM) ...................–0.3V to (VCC + 0.3V)
REF+, REF– ................................–0.3V to (VCC + 0.3V)
Digital Input Voltage......................–0.3V to (VCC + 0.3V)
Digital Output Voltage ...................–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2488C ................................................ 0°C to 70°C
LTC2488I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 16 Bits
Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
l 2
1
20 ppm of VREF
ppm of VREF
Offset Error 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14) l0.5 5 µV
Offset Error Drift 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 10 nV/°C
Positive Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF l32 ppm of VREF
Positive Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 0.1 ppm of VREF/°C
Negative Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF l32 ppm of VREF
Negative Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF 0.1 ppm of VREF/°C
Total Unadjusted Error 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
15
15
15
ppm of VREF
ppm of VREF
ppm of VREF
Output Noise 2.7V < VCC < 5.5V, 2.5V ≤ VREF ≤ VCC,
GND ≤ IN+ = IN– ≤ VCC (Note 13)
0.6 µVRMS
PIN CONFIGURATION
1
2
3
4
5
6
7
14
13
12
11
10
9
8
REF–
REF+
VCC
CH3
CH2
CH1
CH0
FO
SDI
SCK
CS
SDO
GND
COM
DE PACKAGE
14-LEAD (4mm x 3mm) PLASTIC DFN
15
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2488CDE#PBF LTC2488CDE#TRPBF 2488 14-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC2488IDE#PBF LTC2488IDE#TRPBF 2488 14-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
Consult LT C Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container.
Consult LT C Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC2488
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For more information www.linear.com/LTC2488
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) l140 dB
Input Common Mode Rejection 50Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) l140 dB
Input Common Mode Rejection 60Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) l140 dB
Input Normal Mode Rejection 50Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7) l110 120 dB
Input Normal Mode Rejection 60Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8) l110 120 dB
Input Normal Mode Rejection 50Hz/60Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 9) l87 dB
Reference Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) l120 140 dB
Power Supply Rejection DC VREF = 2.5V, IN+ = IN– = GND 120 dB
Power Supply Rejection, 50Hz ±2% VREF = 2.5V, IN+ = IN– = GND (Notes 7, 9) 120 dB
Power Supply Rejection, 60Hz ±2% VREF = 2.5V, IN+ = IN– = GND (Notes 8, 9) 120 dB
ANALOG INPUT AND REFERENCE
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IN+Absolute/Common Mode IN+ Voltage (IN+ Corresponds
to the Selected Positive Input Channel)
GND – 0.3V VCC + 0.3V V
IN–Absolute/Common Mode IN– Voltage (IN– Corresponds
to the Selected Negative Input Channel or COM)
GND – 0.3V VCC + 0.3V V
VIN Input Voltage Range (IN+ – IN–) Differential/Single-Ended l–FS +FS V
FS Full Scale of the Input (IN+ – IN–) Differential/Single-Ended l0.5VREF V
LSB Least Significant Bit of the Output Code lFS/216
REF+Absolute/Common Mode REF+ Voltage l0.1 VCC V
REF–Absolute/Common Mode REF– Voltage lGND REF+ – 0.1V V
VREF Reference Voltage Range (REF+ – REF–)l0.1 VCC V
CS(IN+) IN+ Sampling Capacitance 11 pF
CS(IN–) IN– Sampling Capacitance 11 pF
CS(VREF) VREF Sampling Capacitance 11 pF
IDC_LEAK(IN+)IN+ DC Leakage Current Sleep Mode, IN+ = GND l–10 1 10 nA
IDC_LEAK(IN–)IN– DC Leakage Current Sleep Mode, IN– = GND l–10 1 10 nA
IDC_LEAK(REF+)REF+ DC Leakage Current Sleep Mode, REF+ = VCC l–100 1 100 nA
IDC_LEAK(REF–)REF– DC Leakage Current Sleep Mode, REF– = GND l–100 1 100 nA
tOPEN MUX Break-Before-Make 50 ns
QIRR MUX Off Isolation VIN = 2VP-P DC to 1.8MHz 120 dB
LTC2488
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For more information www.linear.com/LTC2488
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage (CS, FO, SDI) 2.7V ≤ VCC ≤ 5.5V (Note 18) lVCC – 0.5 V
VIL Low Level Input Voltage (CS, FO, SDI) 2.7V ≤ VCC ≤ 5.5V l0.5 V
VIH High Level Input Voltage (SCK) 2.7V ≤ VCC ≤ 5.5V (Notes 10, 15) lVCC – 0.5 V
VIL Low Level Input Voltage (SCK) 2.7V ≤ VCC ≤ 5.5V (Notes 10, 15) l0.5 V
IIN Digital Input Current (CS, FO, SDI) 0V ≤ VIN ≤ VCC l–10 10 µA
IIN Digital Input Current (SCK) 0V ≤ VIN ≤ VCC (Notes 10, 15) l–10 10 µA
CIN Digital Input Capacitance (CS, FO, SDI) 10 pF
CIN Digital Input Capacitance (SCK) (Notes 10, 15) 10 pF
VOH High Level Output Voltage (SDO) IO = –800µA lVCC – 0.5 V
VOL Low Level Output Voltage (SDO) IO = 1.6mA l0.4 V
VOH High Level Output Voltage (SCK) IO = –800µA (Notes 10, 17) lVCC – 0.5 V
VOL Low Level Output Voltage (SCK) IO = 1.6mA (Notes 10, 17) l0.4 V
IOZ Hi-Z Output Leakage (SDO) l–10 10 µA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage l2.7 5.5 V
ICC Supply Current Conversion Current (Note 12)
Sleep Mode (Note 12)
l
l
160
1
275
2
µA
µA
LTC2488
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For more information www.linear.com/LTC2488
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range (Note 16) l10 1000 kHz
tHEO External Oscillator High Period l0.125 100 µs
tLEO External Oscillator Low Period l0.125 100 µs
tCONV Conversion Time Simultaneous 50Hz/60Hz
External Oscillator
l144.1 146.9
41036/fEOSC (in kHz)
149.9 ms
ms
fISCK Internal SCK Frequency Internal Oscillator (Notes 10, 17)
External Oscillator (Notes 10, 11, 15)
38.4
fEOSC/8
kHz
kHz
DISCK Internal SCK Duty Cycle (Notes 10, 17) l45 55 %
fESCK External SCK Frequency Range (Notes 10, 11, 15) l4000 kHz
tLESCK External SCK Low Period (Notes 10, 11, 15) l125 ns
tHESCK External SCK High Period (Notes 10, 11, 15) l125 ns
tDOUT_ISCK Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 17)
External Oscillator (Notes 10, 11, 15)
l0.61 0.625
192/fEOSC (in kHz)
0.64 ms
ms
tDOUT_ESCK External SCK 24-Bit Data Output Time 24/fESCK (in kHz) ms
t1CS↓ to SDO Low l0 200 ns
t2CS↑ to SDO High Z l0 200 ns
t3CS↓ to SCK↓Internal SCK Mode l0 200 ns
t4CS↓ to SCK↑External SCK Mode l50 ns
tKQMAX SCK↓ to SDO Valid l200 ns
tKQMIN SDO Hold After SCK↓(Note 5) l15 ns
t5SCK Set-Up Before CS↓l50 ns
t7SDI Setup Before SCK↑(Note 5) l100 ns
t8SDI Hold After SCK↑(Note 5) l100 ns
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: Unless otherwise specified:
VCC = 2.7V to 5.5V
VREFCM = VREF/2, FS = 0.5VREF
VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2,
where IN+ and IN– are the selected input channels.
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless other wise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: fEOSC = 256kHz ±2% (external oscillator).
Note 8: fEOSC = 307.2kHz ±2% (external oscillator).
Note 9: Simultaneous 50Hz/60Hz (internal oscillator) or fEOSC = 280kHz
±2% (external oscillator).
Note 10: The SCK can be configured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as a digital input and the
driving clock is fESCK. In the internal SCK mode, the SCK pin is used as a
digital output and the output clock signal during the data output is fISCK.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses its internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations. VREF ≤ VCC.
Note 14: Guaranteed by design and test correlation.
Note 15: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 16: Refer to Applications Information section for performance vs
data rate graphs.
Note 17: The converter in internal SCK mode of operation such that the
SCK pin is used as a digital output.
Note 18: For VCC < 3V, VIH is 2.5V for pin fO.
LTC2488
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For more information www.linear.com/LTC2488
VIN(CM) (V)
–1
OFFSET ERROR (ppm OF VREF)
0.1
0.2
0.3
2 4
2488 G07
0
–0.1
0 1 3 5 6
–0.2
–0.3
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
TEMPERATURE (°C)
–45
–0.3
OFFSET ERROR (ppm OF VREF)
–0.2
0
0.1
0.2
–15 15 30 90
2488 G08
–0.1
–30 0 45 60 75
0.3
VCC = 5V
VREF = 5V
VIN = 0V
FO = GND
VCC (V)
2.7
OFFSET ERROR (ppm OF V
REF
)
0.1
0.2
0.3
3.9 4.7
2488 G09
0
–0.1
3.1 3.5 4.3 5.1 5.5
–0.2
–0.3
REF+ = 2.5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
INPUT VOLTAGE (V)
–3
INL (ppm OF V
REF
)
–1
1
3
–2
0
2
–1.5 –0.5 0.5 1.5
2488 G01
2.5–2–2.5 –1 0 1 2
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
FO = GND
85°C
–45°C 25°C
INPUT VOLTAGE (V)
–3
INL (ppm OF V
REF
)
–1
1
3
–2
0
2
–0.75 –0.25 0.25 0.75
2488 G02
1.25–1.25
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
–45°C, 25°C, 85°C
INPUT VOLTAGE (V)
–3
INL (ppm OF V
REF
)
–1
1
3
–2
0
2
–0.75 –0.25 0.25 0.75
2488 G03
1.25–1.25
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
–45°C, 25°C, 85°C
INPUT VOLTAGE (V)
–12
TUE (ppm OF V
REF
)
–4
4
12
–8
0
8
–1.5 –0.5 0.5 1.5
2488 G04
2.5–2–2.5 –1 0 1 2
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
FO = GND 85°C
25°C
–45°C
INPUT VOLTAGE (V)
–12
TUE (ppm OF V
REF
)
–4
4
12
–8
0
8
–0.75 –0.25 0.25 0.75
2488 G05
1.25–1.25
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
85°C
25°C
–45°C
INPUT VOLTAGE (V)
–12
TUE (ppm OF V
REF
)
–4
4
12
–8
0
8
–0.75 –0.25 0.25 0.75
2488 G06
1.25–1.25
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND 85°C
25°C
–45°C
Offset Error vs VIN(CM)
Offset Error vs Temperature
Offset Error vs VCC
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
LTC2488
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For more information www.linear.com/LTC2488
VREF (V)
0
–0.3
OFFSET ERROR (ppm OF VREF)
–0.2
–0.1
0
0.1
0.2
0.3
1 2 3 4
2488 G10
5
VCC = 5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Error vs VREF
TEMPERATURE (°C)
–45
100
CONVERSION CURRENT (µA)
120
160
180
200
–15 15 30 90
2488 G16
140
–30 0 45 60 75
VCC = 5V
VCC = 2.7V
FO = GND
CS = GND
SCK = NC
SDO = NC
SDI = GND
FREQUENCY AT VCC (Hz)
0
–140
REJECTION (dB)
–120
–80
–60
–40
0
20 100 140
2488 G14
–100
–20
80 180 220200
40 60 120 160
VCC = 4.1V DC ±1.4V
VREF = 2.5V
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
30600
–60
–40
30750
2488 G15
–80
–100
30650 30700 30800
–120
–140
–20
REJECTION (dB)
VCC = 4.1V DC ±0.7V
VREF = 2.5V
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
TEMPERATURE (°C)
–45
0
SLEEP MODE CURRENT (µA)
0.2
0.6
0.8
1.0
2.0
1.4
–15 15 30 90
2488 G17
0.4
1.6
1.8
1.2
–30 0 45 60 75
VCC = 5V
VCC = 2.7V
FO = GND
CS = VCC
SCK = NC
SDO = NC
SDI = GND
OUTPUT DATA RATE (READINGS/SEC)
0
SUPPLY CURRENT (µA)
500
450
400
350
300
250
200
150
100
2488 G18
20 3010
VREF = VCC
IN+ = GND
IN– = GND
SCK = NC
SDO = NC
SDI = GND
CS GND
FO = EXT OSC
TA = 25°C
VCC = 5V
VCC = 3V
FREQUENCY AT VCC (Hz)
1
0
–20
–40
–60
–80
–100
–120
–140 1k 100k
2488 G13
10 100 10k 1M
REJECTION (dB)
VCC = 4.1V DC
VREF = 2.5V
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
TEMPERATURE (°C)
–45 –30
300
FREQUENCY (kHz)
304
310
–15 30 45
2488 G11
302
308
306
150 60 75 90
VCC = 4.1V
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
FO = GND
VCC (V)
2.5
300
FREQUENCY (kHz)
302
304
306
308
310
3.0 3.5 4.0 4.5
2488 G12
5.0 5.5
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
FO = GND
TA = 25°C
On-Chip Oscillator Frequency
vs Temperature
On-Chip Oscillator Frequency
vs VCC
PSRR vs Frequency at VCC
PSRR vs Frequency at VCC
PSRR vs Frequency at VCC
Conversion Current
vs Temperature
Sleep Mode Current
vs Temperature
Conversion Current
vs Output Data Rate
LTC2488
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PIN FUNCTIONS
FO (Pin 1): Frequency Control Pin. Digital input that controls
the internal conversion clock rate. When FO is connected to
ground, the converter uses its internal oscillator running
at 307.2kHz. The conversion clock may also be overridden
by driving the FO pin with an external clock in order to
change the output rate and the digital filter rejection null.
SDI (Pin 2): Serial Data Input. This pin is used to select
the input channel. The serial data input is applied under
control of the serial clock (SCK) during the data output/
input operation. The first conversion following a new input
is valid.
SCK (Pin 3): Bidirectional, Digital I/O, Clock Pin. In Internal
Serial Clock Operation mode, SCK is generated internally
and is seen as an output on the SCK pin. In External Serial
Clock Operation mode, the digital I/O clock is externally
applied to the SCK pin. The Serial Clock operation mode
is determined by the logic level applied to the SCK pin at
power up and during the most recent falling edge of CS.
CS (Pin 4): Active LOW Chip Select. A LOW on this pin enables
the digital input/output and wakes up the ADC. Following
each conversion, the ADC automatically enters the Sleep
mode and remains in this low power state as long as CS
is HIGH. A LOW-to-HIGH transition on CS during the data
output aborts the data transfer and starts a new conversion.
SDO (Pin 5): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select pin is HIGH, the SDO pin is in a high
impedance state. During the conversion and sleep periods,
this pin is used as the conversion status output. When
the conversion is in progress this pin is HIGH; once the
conversion is complete SDO goes low. The conversion
status is monitored by pulling CS LOW.
GND (Pin 6): Ground. Connect this pin to a common ground
plane through a low impedance connection.
COM (Pin 7): The common negative input (IN–) for all
single ended multiplexer configurations. The voltage on
CH0 to CH3 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN–) provide a bipolar input range
(VIN = IN+ – IN–) from –0.5 • VREF to 0.5 • VREF. Outside
this input range,
the converter produces unique over-range
and under-range output codes.
CH0 to CH3 (Pins 8-11): Analog Inputs. May be pro-
grammed for single-ended or differential mode.
VCC (Pin 12): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor as close to the part as possible.
REF+ (Pin 13), REF– (Pin 14): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 0.1V. The differential voltage (VREF =
REF+ – REF–) sets the fullscale range for all input channels.
Exposed Pad (Pin 15): Ground. This pin is ground and
must be soldered to the PCB ground plane. For prototyping
purposes, this pin may remain floating.
LTC2488
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FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
TEST CIRCUITS
1.69k
SDO
2488 TC01
Hi-Z TO VOH
VOL TO VOH
V
OH
TO Hi-Z
CLOAD = 20pF
1.69k
SDO
2488 TC02
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
CLOAD = 20pF
VCC
AUTOCALIBRATION
AND CONTROL
DIFFERENTIAL
3RD ORDER
ΔΣ MODULATOR
DECIMATING FIR
ADDRESS
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
GND
VCC
CH0
CH1
CH2
CH3
COM
MUX
IN+
IN–
SDO
SCK
REF+
REF–
CS
SDI
FO
(INT/EXT)
2488 BD
+
–
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TIMING DIAGRAMS
CS
SDO
SCK
SDI
t1
t3
t7
t8
SLEEP
tKQMAX
CONVERSIONDATA IN/OUT
tKQMIN
t2
2488 TD01
Hi-ZHi-Z
CS
SDO
SCK
SDI
t1
t5
t4
t7
t8
SLEEP
tKQMAX
CONVERSIONDATA IN/OUT
tKQMIN
t2
2488 TD02
Hi-ZHi-Z
Timing Diagram Using Internal SCK (SCK HIGH with CS↓)
Timing Diagram Using External SCK (SCK LOW with CS↓)
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CONVERTER OPERATION
Converter Operation Cycle
The LTC2488 is a multi-channel, low power, delta-sigma,
analog-to-digital converter with an easy-to-use 4-wire in-
terface and automatic differential input current cancellation.
Its operation is made up of four states (See Figure 2). The
converter’s operating cycle begins with the conversion,
followed by the sleep state, and ends with the data input/
output cycle. The 4-wire interface consists of serial data
output (SDO), serial clock (SCK), chip select (CS) and
serial data input (SDI).The interface, timing, operation
cycle, and data output format is compatible with Linear’s
entire family of SPI ΔS converters.
Initially, at power up, the LTC2488 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in the sleep state, if CS is HIGH, power
consumption is reduced by two orders of magnitude. The
part remains in the sleep state as long as CS is HIGH. The
conversion result is held indefinitely in a static shift register
while the part is in the sleep state.
Once CS is pulled LOW, the device powers up, exits the
sleep state, and enters the data input/output state. If CS
is brought HIGH before the first rising edge of SCK, the
device returns to the sleep state and the power is reduced.
If CS is brought HIGH after the first rising edge of SCK, the
data output cycle is aborted and a new conversion cycle
begins. The data output corresponds to the conversion
just completed. This result is shifted out on the serial
data output pin (SDO) under the control of the serial
clock pin (SCK). Data is updated on the falling edge of
SCK allowing the user to reliably latch data on the rising
edge of SCK (See Figure 3). The channel selection data for
the next conversion is also loaded into the device at this
time. Data is loaded from the serial data input pin (SDI)
on each rising edge of SCK. The data input/output cycle
concludes once 24 bits are read out of the ADC or when
CS is brought HIGH. The device automatically initiates a
new conversion and the cycle repeats.
Through timing control of the CS and SCK pins, the LTC2488
offers several flexible modes of operation (internal or
external SCK and free-running conversion modes). These
various modes do not require programming and do not
disturb the cyclic operation described above. These modes
of operation are described in detail in the Serial Interface
Timing Modes section.
Ease of Use
The LTC2488 data output has no latency, filter settling
delay, or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straight forward. Each conversion,
immediately following a newly selected input, is valid and
accurate to the full specifications of the device.
The LTC2488 automatically performs offset and full scale
calibration every conversion cycle independent of the input
channel selected. This calibration is transparent to the user
and has no effect on the operation cycle described above.
The advantage of continuous calibration is extreme stability
of offset and full-scale readings with respect to time, sup-
ply voltage variation, input channel, and temperature drift.
Easy Drive Input Current Cancellation
The LTC2488 combines a high precision, delta-sigma ADC
with an automatic, differential, input current cancellation
front end. A proprietary front end passive sampling network
transparently removes the differential input current. This en-
ables external RC networks and high impedance sensorsto
Figure 2. LTC2488 State Transition Diagram
CONVERT
SLEEP
CHANNEL SELECT
DATA OUTPUT
POWER UP
IN+= CH0, IN–= CH1
2488 F02
CS = LOW
AND
SCK
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APPLICATIONS INFORMATION
directly interface to the LTC2488 without external amplifiers.
The remaining common mode input current is eliminated by
either balancing the differential input impedances or setting
the common mode input equal to the common mode refer-
ence (see Automatic Differential Input Current Cancellation
Section). This unique architecture does not require on-chip
buffers, thereby enabling signals to swing beyond ground
and VCC. Moreover, the cancellation does not interfere with
the transparent offset and full-scale auto-calibration and the
absolute accuracy (full scale + offset + linearity + drift) is
maintained even with external RC networks.
Power-Up Sequence
The LTC2488 automatically enters an internal reset state
when the power supply voltage VCC drops below ap-
proximately 2V. This feature guarantees the integrity of
the conversion result, input channel selection, and serial
clock mode.
When VCC rises above this threshold, the converter creates
an internal power-on-reset (POR) signal with a duration
of approximately 4ms. The POR signal clears all internal
registers. The conversion immediately following a POR
cycle is performed on the input channel IN+ = CH0, IN– =
CH1. The first conversion following a POR cycle is accurate
within the specification of the device if the power supply
voltage is restored to (2.7V to 5.5V) before the end of the
POR interval. A new input channel can be programmed
into the device during this first data input/output cycle.
Reference Voltage Range
This converter accepts a truly differential external reference
voltage. The absolute/common mode voltage range for
REF+ and REF– pins covers the entire operating range of
the device (GND to VCC). For correct converter operation,
VREF must be positive (REF+ > REF–).
The LTC2488 differential reference input range is 0.1V to
VCC. For the simplest operation, REF+ can be shorted to
VCC and REF– can be shorted to GND. The converter output
noise is determined by the thermal noise of the front end
circuits. Since the transition noise is well below 1LSB
(0.02LSB), a decrease in reference voltage will proportion-
ally improve the converter resolution and improve INL.
Input Voltage Range
The LTC2488 input measurement range is –0.5 • VREF to 0.5
• VREF in both differential and single-ended configurations
as shown in Figure 28. Highest linearity is achieved with
fully differential drive and a constant common mode voltage
(Figure 28b). Other drive schemes may incur an INL error
of approximately 50ppm. This error can be calibrated out
using a three point calibration and a second-order curve fit.
The analog inputs are truly differential with an absolute,
common mode range for the CH0 to CH3 and COM input
pins extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn
on and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2488 converts the
bipolar differential input signal VIN = IN+ – IN– (where
IN+ and IN– are the selected input channels), from –FS =
–0.5 • VREF to +FS = 0.5 • VREF where VREF = REF+ – REF–.
Outside this range, the converter indicates the overrange
or the underrange condition using distinct output codes
(see Table 1).
Signals applied to the input (CH0 to CH3, COM) may
extend 300mV below ground and above VCC. In order to
limit any fault current, resistors of up to 5k may be added
in series with the input. The effect of series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent error due to input leakage current. A 1nA input
leakage current will develop a 1ppm offset error on a 5k
resistor if VREF = 5V. This error has a very strong tem-
perature dependency.
SERIAL INTERFACE PINS
The LTC2488 transmits the conversion result, reads the
input channel selection, and receives a start of conversion
command through a synchronous 3- or 4-wire interface.
During the conversion and sleep states, this interface can
be used to access the converter status. During the data
output state, it is used to read the conversion result and
program the input channel.
Serial Clock Input/Output (SCK)
The serial clock pin (SCK) is used to synchronize the data
input/output transfer. Each bit is shifted out of the SDO
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APPLICATIONS INFORMATION
pin on the falling edge of SCK and data is shifted into the
SDI pin on the rising edge of SCK.
The serial clock pin (SCK) can be configured as either a
master (SCK is an output generated internally) or a slave
(SCK is an input and applied externally). Master mode
(Internal SCK) is selected by simply floating the SCK pin.
Slave mode (External SCK) is selected by driving SCK low
during power up and each falling edge of CS. Specific
details of these SCK modes are described in the Serial
Interface Timing Modes section.
Serial Data Output (SDO)
The serial data output pin (SDO) provides the result of the
last conversion as a serial bit stream (MSB first) during
the data output state. In addition, the SDO pin is used as
an end of conversion indicator during the conversion and
sleep states.
When CS is HIGH, the SDO driver is switched to a high
impedance state in order to share the data output line with
other devices. If CS is brought LOW during the conversion
phase, the EOC bit (SDO pin) will be driven HIGH. Once
the conversion is complete, if CS is brought LOW, EOC
will be driven LOW indicating the conversion is complete
and the result is ready to be shifted out of the device.
Chip Select (CS)
The active low CS pin is used to test the conversion status,
enable I/O data transfer, initiate a new conversion, control
the duration of the sleep state, and set the SCK mode.
At the conclusion of a conversion cycle, while CS is HIGH,
the device remains in a low power sleep state where the
supply current is reduced several orders of magnitude. In
order to exit the sleep state and enter the data output state,
CS must be pulled low. Data is now shifted out the SDO
pin under control of the SCK pin as described previously.
A new conversion cycle is initiated either at the conclusion
of the data output cycle (all 24 data bits read) or by pulling
CS HIGH any time between the first and 24th rising edges
of the serial clock (SCK). In this case, the data output is
aborted and a new conversion begins.
Serial Data Input (SDI)
The serial data input (SDI) is used to select the input chan-
nel. Data is shifted into the device during the data output/
input state on the rising edge of SCK while CS is low.
OUTPUT DATA FORMAT
The LTC2488 serial output stream is 24 bits long. The
first bit indicates the conversion status, the second bit is
always zero, and the third bit conveys sign information.
The next 17 bits are the conversion result, MSB first. The
remaining 4 bits are always LOW.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available on the SDO pin during the
conversion and sleep states whenever CS is LOW. This bit
is HIGH during the conversion cycle, goes LOW once the
conversion is complete, and is HIGH-Z when CS is HIGH.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign indicator
(SIG). If the selected input (VIN = IN+ – IN–) is greater than
or equal to 0V, this bit is HIGH. If VIN < 0, this bit is LOW.
Bit 20 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 21 also pro-
vides underrange and overrange indication. If both Bit 21
and Bit 20 are HIGH, the differential input voltage is above
+FS. If both Bit 21 and Bit 20 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2488 Status Bits
Input Range Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
MSB
VIN ≥ 0.5 • VREF 0011
0V ≤ VIN < 0.5 • VREF 0010
–0.5 • VREF ≤ VIN < 0V 0 0 0 1
VIN < –0.5 • VREF 0000
Bits 20 to 4 are the 16-bit plus sign conversion result
MSB first.
Bit 4 is the least significant bit (LSB16).
Bits 3 to 0 are always LOW.
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Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 3). Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time as a function of the internal oscillator or the clock
applied to the fO pin from HIGH to LOW at the completion
of a conversion. This signal may be used as an interrupt for
an external microcontroller. Bit 23 (EOC) can be captured
on the first rising edge of SCK. Bit 22 is shifted out of the
device on the first falling edge of SCK. The final data bit
(Bit 0) is shifted out on the on the falling edge of the 23rd
SCK and may be latched on the rising edge of the 24th
SCK pulse. On the falling edge of the 24th SCK pulse, SDO
goes HIGH indicating the initiation of a new conversion
cycle. This bit serves as EOC (Bit 23) for the next conver-
sion cycle. Table 2 summarizes the output data format.
As long as the voltage on the IN+ and IN– pins remains be-
tween –0.3V and VCC + 0.3V (absolute maximum operating
range) a conversion result is generated for any differential
input voltage VIN from –FS = –0.5 • VREF to +FS = 0.5 •
VREF. For differential input voltages greater than +FS, the
conversion result is clamped to the value corresponding
to +FS + 1LSB. For differential input voltages below –FS,
the conversion result is clamped to the value –FS – 1LSB.
INPUT DATA FORMAT
The LTC2488 serial input word is 8 bits long. The input
bits (SGL, ODD, A2, A1, A0) are used to select the input
channel.
EOC
CS
SCK
(EXTERNAL)
SDI
SDO
2488 F03
CONVERSION SLEEP DATA INPUT/OUTPUT
MSB
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
SIG
BIT 21
“0”
BIT 22BIT 23
1 0 EN SGL A2 A1 A0ODD
BIT 10 BIT 9 BIT 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 24
DON'T CAREDON'T CARE
Figure 3. Channel Selection and Data Output Timing
Table 2. Output Data Format
Differential Input Voltage
VIN*
Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
MSB
Bit 19 Bit 18 Bit 17 … Bit 4
LSB
Bits 3 to 0
Always 0
VIN* ≥ 0.5 • VREF** 0 0 1 1 0 0 0 … 0 0000
0.5 • VREF** – 1LSB 0 0 1 0 1 1 1 … 1 0000
0.25 • VREF** 0 0 1 0 1 0 0 … 0 0000
0.25 • VREF** – 1LSB 0 0 1 0 0 1 1 … 1 0000
0 0 0 1 0 0 0 0 … 0 0000
–1LSB 0 0 0 1 1 1 1 … 1 0000
–0.25 • VREF** 0 0 0 1 1 0 0 … 0 0000
–0.25 • VREF** – 1LSB 0 0 0 1 0 1 1 … 1 0000
–0.5 • VREF** 0 0 0 1 0 0 0 … 0 0000
VIN* < –0.5 • VREF** 0 0 0 0 1 1 1 … 1 0000
*The differential input voltage VIN = IN+ – IN–. **The differential reference voltage VREF = REF+ – REF–.
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After power up, the device initiates an internal reset cycle
which sets the input channel to CH0 to CH1 (IN+ = CH0, IN–
= CH1). The first conversion automatically begins at power
up using this default input channel. Once the conversion
is complete, a new word may be written into the device.
The first three bits of the input word consist of two pre-
amble bits and one enable bit. These three bits are used
to enable the input channel selection. Valid settings for
these three bits are 000, 100, and 101. Other combinations
should be avoided.
If the first three bits are 000 or 100, the following data
is ignored (don’t care) and the previously selected input
channel remains valid for the next conversion.
If the first three bits shifted into the device are 101, then
the next five bits select the input channel for the next
conversion cycle (see Table 3).
The first input bit (SGL) following the 101 sequence
determines if the input selection is differential (SGL =
0) or single-ended (SGL = 1). For SGL = 0, two adjacent
channels can be selected to form a differential input. For
SGL = 1, one of four channels is selected as the positive
input. The negative input is COM for all single ended
operations. The remaining four bits (ODD, A2, A1, A0)
determine which channel(s) is/are selected and the polarity
(for a differential input).
SERIAL INTERFACE TIMING MODES
The LTC2488’s 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes
of operation. These include internal/external serial clock,
3- or 4-wire I/O, single cycle or continuous conversion. The
following sections describe each of these timing modes
in detail. In all cases, the converter can use the internal
oscillator (FO = LOW) or an external oscillator connected
to the FO pin. For each mode, the operating cycle, data
input format, data output format, and performance remain
the same. Refer to Table 4 for a summary.
Table 3 Channel Selection
MUX ADDRESS CHANNEL SELECTION
SGL
ODD/
SIGN A2 A1 A0 0 1 2 3 COM
*0 0 0 0 0 IN+IN–
00001 IN+IN–
01000IN–IN+
01001 IN–IN+
10000IN+IN–
10001 IN+IN–
11000 IN+IN–
11001 IN+IN–
*Default at power up
Table 4. Serial Interface Timing Modes
CONFIGURATION
SCK
SOURCE
CONVERSION
CYCLE CONTROL
DATA OUTPUT
CONTROL
CONNECTION AND
WAVEFORMS
External SCK, Single Cycle
Conversion
External CS and SCK CS and SCK Figures 4, 5
External SCK, 3-Wire I/O External SCK SCK Figure 6
Internal SCK, Single Cycle
Conversion
Internal CS↓CS↓Figures 7, 8
Internal SCK, 3-Wire I/O,
Continuous Conversion
Internal Continuous Internal Figure 9
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External Serial Clock, Single Cycle Operation
This timing mode uses an external serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 4).
The external serial clock mode is selected during the power-
up sequence and on each falling edge of CS. In order to
enter and remain in the external SCK mode of operation,
SCK must be driven LOW both at power up and on each
CS falling edge. If SCK is HIGH on the falling edge of CS,
the device will switch to the internal SCK mode.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is complete and the device is in the sleep
state. Independent of CS, the device automatically enters
the sleep state once the conversion is complete; however,
in order to reduce the power, CS must be HIGH.
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device re-
mains in the sleep state until the first rising edge of SCK
is seen while CS is LOW. The input data is then shifted
in via the SDI pin on each rising edge of SCK (including
the first rising edge). The channel selection will be used
for the following conversion cycle. If the input channel
is changed during this I/O cycle, the new settings take
effect on the conversion cycle following the data input/
output cycle. The output data is shifted out the SDO pin
on each falling edge of SCK. This enables external circuitry
to latch the output on the rising edge of SCK. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 24th rising
edge of SCK. On the 24th falling edge of SCK, the device
begins a new conversion and SDO goes HIGH (EOC = 1)
indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Figure 4. External Serial Clock, Single Cycle Operation
VCC FO
REF+
REF–
CH0
CH1
CH2
CH3
COM
SCK
SDI
CS
SDO
GND
12 1
13
14
8
9
10
11
7
3
4
6
5
2
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2488
2.7V TO 5.5V
0.1µF
10µF
4-WIRE
SPI INTERFACE
Hi-Z
2488 F04
CS
SCK
(EXTERNAL)
SDI
SDO
CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION
EOC
1 2 3 4 5 6 7 8 9 19 20 21 22 23 24
1 0 EN SGL A2 A1 A0ODD DON'T CAREDON'T CARE
MSBSIG“0” LSB
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
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Typically, CS remains LOW during the data output/input
state. However, the data output state may be aborted by
pulling CS HIGH any time between the 1st falling edge
and the 24th falling edge of SCK (see Figure 5). On the
rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge
of SCK, the new input channel is loaded and valid for the
next conversion cycle.
External Serial Clock, 3-Wire I/O
This timing mode uses a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal (see Figure 6).
CS is permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle typically
concludes 4ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internally generated
or externally applied. In order to enter the external SCK
mode, SCK must be driven LOW prior to the end of the
POR cycle.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller. EOC = 1 while the conversion is in
progress and EOC = 0 once the conversion is complete.
On the falling edge of EOC, the conversion result is load-
ing into an internal static shift register. The output data
can now be shifted out the SDO pin under control of the
externally applied SCK signal. Data is updated on the fall-
ing edge of SCK. The input data is shifted into the device
through the SDI pin on the rising edge of SCK. On the
24th falling edge of SCK, SDO goes HIGH, indicating a
new conversion has begun. This data now serves as EOC
for the next conversion.
APPLICATIONS INFORMATION
VCC FO
SCK
SDI
GND 6
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2488
4-WIRE
SPI INTERFACE
REF+
REF–
CH0
CH1
CH2
CH3
COM
CS
SDO
12 1
13
14
8
9
10
11
7
3
4
5
2
2.7V TO 5.5V
0.1µF
10µF
Hi-Z
2488 F05
CS
SCK
(EXTERNAL)
SDI
SDO
CONVERSION SLEEP DATA INPUT/OUTPUT SLEEPCONVERSION
EOC
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15BIT 21BIT 22BIT 23
1 2 3 4 5 6 7 8
1 0 EN SGL A2 A1 A0ODD DON'T CAREDON'T CARE
MSBSIG“0”
Figure 5. External Serial Clock, Reduced Output Data Length and Valid Channel Selection
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Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 7).
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating or pulled HIGH
before the conclusion of the POR cycle and prior to each
falling edge of CS. An internal weak pull-up resistor is active
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled low in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while the conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC =
0), the device will exit sleep state. In order to return to the
sleep state and reduce the power consumption, CS must be
pulled HIGH before the device pulls SCK HIGH. When the
device is using its own internal oscillator (FO is tied LOW),
the first rising edge of SCK occurs 12µs (tEOCTEST = 12µs)
after the falling edge of CS. If FO is driven by an external
oscillator of frequency fEOSC, then tEOCTEST = 3.6/fEOSC.
If CS remains LOW longer than tEOCTEST, the first rising
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
After the 24th rising edge of SCK a new conversion au-
tomatically begins. SDO goes HIGH (EOC = 1) and SCK
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH any time between the 1st rising edge and the 24th
falling edge of SCK (see Figure 8). On the rising edge of
CS, the device aborts the data output state and immediately
initiates a new conversion. In order to program a new
input channel, 8 SCK clock pulses are required. If the data
output sequence is aborted prior to the 8th falling edge
VCC FO
SCK
SDI
GND
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2488
3-WIRE
SPI INTERFACE
REF+
REF–
CH0
CH1
CH2
CH3
COM
SDO
12 1
13
14
8
9
10
11
7
3
5
6
4
2
2.7V TO 5.5V
0.1µF
10µF
CS
EOC
CS
SCK
(EXTERNAL)
SDI
SDO
2488 F06
CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION
1 0 EN SGL A2 A1 A0ODD
BIT 0
DON'T CAREDON'T CARE
MSBSIG“0”
1 2 3 4 5 6 7 8 9 19 20 21 22 23 24
LSB
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Figure 6. External Serial Clock, 3-Wire Operation (CS = 0)
LTC2488
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For more information www.linear.com/LTC2488
APPLICATIONS INFORMATION
of SCK, the new input data is ignored and the previously
selected input channel remains valid. If the rising edge of
CS occurs after the 8th falling edge of SCK, the new input
channel is loaded and valid for the next conversion cycle.
Internal Serial Clock, 3-Wire I/O, Continuous
Conversion.
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal (see Figure 9). In this case, CS is
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 4ms after VCC exceeds 2V. An internal
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is floating or driven HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has finished and the device has entered
the sleep state. The device remains in the sleep state a
minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting and inputting data.
The input data is shifted through the SDI pin on the ris-
ing edge of SCK (including the first rising edge) and the
output data is shifted out the SDO pin on the falling edge
of SCK. The data input/output cycle is concluded and a
new conversion automatically begins after the 24th rising
edge of SCK. During the next conversion, SCK and SDO
remain HIGH until the conversion is complete.
The Use of a 10k Pull-Up on SCK for Internal SCK
Selection
If CS is pulled HIGH while the converter is driving SCK
LOW, the internal pull-up is not available to restore SCK
to a logic HIGH state if SCK is floating. This will cause the
device to exit the internal SCK mode on the next falling
edge of CS. This can be avoided by adding an external 10k
pull-up resistor to the SCK pin.
Figure 7. Internal Serial Clock, Single Cycle Operation
VCC FO
SCK
SDI
GND
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2488
4-WIRE
SPI INTERFACE
OPTIONAL
10k
VCC
REF+
REF–
CH0
CH1
CH2
CH3
COM
CS
12 1
13
14
8
9
10
11
7
3
4
6
5
2
2.7V TO 5.5V
0.1µF
10µF
SDO
Hi-Z
2488 F07
CS
SCK
(INTERNAL)
SDI
SDO
CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION
EOC
1 0 EN SGL A2 A1 A0ODD DON'T CAREDON'T CARE
MSBSIG“0”
<tEOCTEST
1 2 3 4 5 6 7 8 9 19 20 21 22 23 24
LSB
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
LTC2488
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APPLICATIONS INFORMATION
Figure 8. Internal Serial Clock, Reduced Data Output Length with Valid Channel and Configuration Selection
Figure 9. Internal Serial Clock, Continuous Operation
VCC FO
SCK
SDI
SDO
CS
GND
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2488
3-WIRE
SPI INTERFACE
OPTIONAL
10k
VCC
REF+
REF–
CH0
CH1
CH2
CH3
COM
12 1
13
14
8
9
10
11
7
3
5
6
4
2
2.7V TO 5.5V
0.1µF
10µF
EOC
CS
SCK
(INTERNAL)
SDI
SDO
2488 F09
CONVERSION DATA INPUT/OUTPUT CONVERSION
1 0 EN SGL A2 A1 A0ODD DON'T CAREDON'T CARE
MSBSIG“0”
2 31 4 5 6 7 8 9 19 20 21 22 23 24
LSB
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
VCC FO
SCK
SDI
GND
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2488
4-WIRE
SPI INTERFACE
OPTIONAL
10k
VCC
REF+
REF–
CH0
CH1
CH2
CH3
COM
12 1
13
14
8
9
10
11
7
3
4
6
5
2
2.7V TO 5.5V
0.1µF
10µF
CS
SDO
Hi-Z
2488 F08
CS
SCK
(INTERNAL)
SDI
SDO
CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION
EOC
BIT 14 BIT 13
1 2 3 4 5 6 7 8 9 10
1 0 EN SGL A2 A1 A0ODD DON'T CAREDON'T CARE
MSBSIG“0”
<tEOCTEST
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15
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APPLICATIONS INFORMATION
Whenever SCK is LOW, the LTC2488’s internal pull-up at
SCK is disabled. Normally, SCK is not externally driven if
the device is operating in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If the driver goes Hi-Z after outputting a
LOW signal, the internal pull-up is disabled. An external
10k pull-up resistor prevents the device from exiting the
internal SCK mode under this condition.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. If CS goes HIGH before the time tEOCtest,
the internal pull-up is activated. If SCK is heavily loaded,
the internal pull-up may not restore SCK to a HIGH state
before the next falling edge of CS. The external 10k pull-up
resistor prevents the device from exiting the internal SCK
mode under this condition.
PRESERVING THE CONVERTER ACCURACY
The LTC2488 is designed to reduce as much as possible
sensitivity to device decoupling, PCB layout, anti-aliasing
circuits, line frequency perturbations, and temperature
sensitivity. In order to achieve maximum performance a
few simple precautions should be observed.
Digital Signal Levels
The LTC2488’s digital interface is easy to use. Its digital
inputs SDI, FO, CS, and SCK (in external serial clock mode)
accept standard CMOS logic levels. Internal hysteresis
circuits can tolerate edge transition times as slow as 100µs.
The digital input signal range is 0.5V to VCC – 0.5V. During
transitions, the CMOS input circuits draw dynamic cur-
rent. For optimal performance, application of signals to
the serial data interface should be reserved for the sleep
and data output periods.
During the conversion period, overshoot and undershoot
of fast digital signals applied to both the serial digital in-
terface and the external oscillator pin (FO) may degrade
the converter performance. Undershoot and overshoot
occur due to impedance mismatch of the circuit board
trace at the converter pin when the transition time of an
external control signal is less than twice the propagation
delay from the driver to the input pin. For reference, on a
regular FR-4 board, the propagation delay is approximately
183ps/inch. In order to prevent overshoot, a driver with
a 1ns transition time must be connected to the converter
through a trace shorter than 2.5 inches. This becomes
difficult when shared control lines are used and multiple
reflections occur.
Parallel termination near the input pin of the LTC2488 will
eliminate this problem, but will increase the driver power
dissipation. A series resistor from 27Ω to 54Ω (depend-
ing on the trace impedance and connection) placed near
the driver will also eliminate over/under shoot without
additional driver power dissipation.
For many applications, the serial interface pins (SCK, SDI,
CS, FO) remain static during the conversion cycle and
no degradation occurs. On the other hand, if an external
oscillator is used (FO driven externally) it is active during
the conversion cycle. Moreover, the digital filter rejection
is minimal at the clock rate applied to FO. Care must be
taken to ensure external inputs and reference lines do not
cross this signal or run near it. These issues are avoided
when using the internal oscillator.
Driving the Input and Reference
The input and reference pins of the LTC2488 are connected
directly to a switched capacitor network. Depending on
the relationship between the differential input voltage and
the differential reference voltage, these capacitors are
switched between these four pins. Each time a capacitor
is switched between two of these pins, a small amount
of charge is transferred. A simplified equivalent circuit is
shown in Figure 10.
When using the LTC2488’s internal oscillator, the input
capacitor array is switched at 123kHz. The effect of the
charge transfer depends on the circuitry driving the input/
reference pins. If the total external RC time constant is less
than 580ns the errors introduced by the sampling process
are negligible since complete settling occurs.
Typically, the reference inputs are driven from a low imped-
ance source. In this case, complete settling occurs even
with large external bypass capacitors. The inputs (CH0 to
CH3, COM), on the other hand, are typically driven from
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larger source resistances. Source resistances up to 10k
may interface directly to the LTC2488 and settle completely;
however, the addition of external capacitors at the input
terminals in order to filter unwanted noise (anti-aliasing)
results in incomplete settling.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kΩ with no external bypass capacitor or up
to 500Ω with 0.001µF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization is possible.
For many applications, the sensor output impedance
combined with external input bypass capacitors produces
RC time constants much greater than the 580ns required
for 1ppm accuracy. For example, a 10kΩ bridge driving a
0.1µF capacitor has a time constant an order of magnitude
greater than the required maximum.
The LTC2488 uses a proprietary switching algorithm that
forces the average differential input current to zero indepen-
dent of external settling errors. This allows direct digitization
of high impedance sensors without the need of buffers.
The switching algorithm forces the average input current
on the positive input (IIN+) to be equal to the average input
current on the negative input (IIN–). Over the complete
conversion cycle, the average differential input current
(IIN+ – IIN–) is zero. While the differential input current is
zero, the common mode input current (IIN+ + IIN–)/2 is
proportional to the difference between the common mode
input voltage (VIN(CM)) and the common mode reference
voltage (VREF(CM)).
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balanced bridge, both the differential and com-
mon mode input currents are zero. The accuracy of the
converter is not compromised by settling errors.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between VIN(CM) and VREF(CM). For a reference
common mode voltage of 2.5V and an input common
mode of 1.5V, the common mode input current is ap-
proximately 0.74µA. This common mode input current
does not degrade the accuracy if the source impedances
APPLICATIONS INFORMATION
Figure 10. LTC2488 Equivalent Analog Input Circuit
IN+
IN–
10k
INTERNAL
SWITCH
NETWORK
10k
CEQ
12pF
10k
IIN–
REF+
IREF+
IIN+
IREF–
2488 F10
SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR
REF–
10k
100Ω
INPUT
MULTIPLEXER
100Ω
I IN+
( )
AVG =I IN–
( )
AVG =V
IN(CM) −VREF(CM)
0.5•REQ
I REF+
( )
AVG ≈1.5VREF +VREF(CM) – V
IN(CM)
( )
0.5•REQ
–V
IN
2
VREF •REQ
where:
VREF =REF+−REF−
VREF(CM) =REF+–REF−
2
V
IN =IN+−IN−,WHERE IN+ANDIN−ARE THE SELECTEDINPUT CHANNELS
VIN(CM) =IN+–IN−
2
REQ =2.98MΩINTERNAL OSCILLATOR
REQ =0.833•1012
( )
/fEOSC EXTERNAL OSCILLATOR
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APPLICATIONS INFORMATION
tied to IN+ and IN– are matched. Mismatches in source
impedance lead to a fixed offset error but do not effect
the linearity or full scale reading. A 1% mismatch in a 1k
source resistance leads to a 74µV shift in offset voltage.
In applications where the common mode input voltage
varies as a function of the input signal level (single ended
type sensors), the common mode input current varies
proportionally with input voltage. For the case of balanced
input impedances, the common mode input current effects
are rejected by the large CMRR of the LTC2488, leading
to little degradation in accuracy. Mismatches in source
impedances lead to gain errors proportional to the dif-
ference between the common mode input and common
mode reference. 1% mismatches in 1k source resistances
lead to gain errors on the order of 15ppm. Based on the
stability of the internal sampling capacitors and the ac-
curacy of the internal oscillator, a one-time calibration will
remove this error.
In addition to the input sampling current, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA Max), results
in a small offset shift. A 1k source resistance will create a
1µV typical and a 10µV maximum offset voltage.
Reference Current
Similar to the analog inputs, the LTC2488 samples the
differential reference pins (REF+ and REF–) transferring
small amounts of charge to and from these pins, thus
producing a dynamic reference current. If incomplete set-
tling occurs (as a function the reference source resistance
and reference bypass capacitance) linearity and gain errors
are introduced.
For relatively small values of external reference capacitance
(CREF < 1nF), the voltage on the sampling capacitor settles
for reference impedances of many kΩ (if CREF = 100pF up
to 10kΩ will not degrade the performance) (see Figures
11 and 12).
In cases where large bypass capacitors are required on
the reference inputs (CREF > 0.01µF) full-scale and linear-
ity errors are proportional to the value of the reference
resistance. Every ohm of reference resistance produces
a full-scale error of approximately 0.5ppm (while operat-
ing with the internal oscillator) (see Figures 13 and 14). If
the input common mode voltage is equal to the reference
common mode voltage, a linearity error of approximately
0.67ppm per 100Ω of reference resistance results (see
Figure 15). In applications where the input and reference
common mode voltages are different, the errors increase.
A 1V difference in between common mode input and
common mode reference results in a 6.7ppm INL error
for every 100Ω of reference resistance.
In addition to the reference sampling charge, the reference
ESD protection diodes have a temperature dependent leak-
age current. This leakage current, nominally 1nA (±10nA
max) results in a small gain error. A 100Ω reference
resistance will create a 0.5µV full scale error.
Figure 11. +FS Error vs RSOURCE at VREF (Small CREF)
Figure 12. –FS Error vs RSOURCE at VREF (Small CREF)
RSOURCE (Ω)
0
+FS ERROR (ppm)
50
70
90
10k
2488 F11
30
10
40
60
80
20
0
–10 10 100 1k 100k
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
CREF = 0.01µF
CREF = 0.001µF
CREF = 100pF
CREF = 0pF
RSOURCE (Ω)
0
–FS ERROR (ppm)
–30
–10
10
10k
2488 F12
–50
–70
–40
–20
0
–60
–80
–90 10 100 1k 100k
VCC = 5V
VREF = 5V
VIN+ = 1.25V
VIN– = 3.75V
FO = GND
TA = 25°C
CREF = 0.01µF
CREF = 0.001µF
CREF = 100pF
CREF = 0pF
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APPLICATIONS INFORMATION
Normal Mode Rejection and Anti-aliasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversample ratio, the LTC2488 significantly
simplifies anti-aliasing filter requirements. Additionally,
the input current cancellation feature allows external low
pass filtering without degrading the DC performance of
the device.
The SINC4 digital filter provides excellent normal mode
rejection at all frequencies except DC and integer multiples
of the modulator sampling frequency (fS). The modulator
sampling frequency is fS = 15,360Hz while operating with
its internal oscillator and fS = FEOSC/20 when operating
with an external oscillator of frequency FEOSC.
When using the internal oscillator, the LTC2488 is designed
to reject line frequencies. As shown in Figure 16, rejection
nulls occur at multiples of frequency fN, where fN = 55Hz
for simultaneous 50Hz/60Hz rejection. Multiples of the
modulator sampling rate (fS = fN • 256) only reject noise
to 15dB (see Figure 17), if noise sources are present at
these frequencies anti-aliasing will reduce their effects.
The user can expect to achieve this level of performance
using the internal oscillator, as shown in Figure 18.
Measured values of normal mode rejection are shown
superimposed over the theoretical values.
Traditional high order delta-sigma modulators suffer from
potential instabilities at large input signal levels. The
RSOURCE (Ω)
0
+FS ERROR (ppm)
300
400
500
800
2488 F13
200
100
0200 400 600 1000
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
CREF = 1µF, 10µF
CREF = 0.1µF
CREF = 0.01µF
RSOURCE (Ω)
0
–FS ERROR (ppm)
–200
–100
0
800
2488 F14
–300
–400
–500 200 400 600 1000
VCC = 5V
VREF = 5V
VIN+ = 1.25V
VIN– = 3.75V
FO = GND
TA = 25°C
CREF = 1µF, 10µF
CREF = 0.1µF
CREF = 0.01µF
Figure 13. +FS Error vs RSOURCE at VREF (Large CREF)
Figure 14. –FS Error vs RSOURCE at VREF (Large CREF)
VIN/VREF
–0.5
INL (ppm OF VREF)
2
6
10
0.3
2488 F15
–2
–6
0
4
8
–4
–8
–10 –0.3 –0.1 0.1 0.5
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
CREF = 10µF
R = 1k
R = 100Ω
R = 500Ω
Figure 15. INL vs Differential Input Voltage and Reference
Source Resistance for CREF > 1µF
INPUT SIGNAL FREQUENCY (Hz)
INPUT NORMAL MODE REJECTION (dB)
2488 F16
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 fN
0 2fN3fN4fN5fN6fN7fN8fN
fN = fEOSC/5120
Figure 16. Input Normal Mode Rejection at DC
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APPLICATIONS INFORMATION
proprietary architecture used for the LTC2488 third order
modulator resolves this problem and guarantees stability
with input signals 150% of full-scale. In many industrial
applications, it is not uncommon to have microvolt level
signals superimposed over unwanted error sources with
several volts of peak-to-peak noise. Figure 19 shows mea-
surement results for the rejection of a 7.5V peak-to-peak
noise source (150% of full scale) applied to the LTC2488.
From this curve, it is shown that the rejection performance
is maintained even in extremely noisy environments.
Output Data Rate
When using its internal oscillator, the LTC2488 produces up
to 6.9 samples per second (sps) with a notch frequency of
55Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
by the user and can be made insignificantly short. When
operating with an external conversion clock (FO connected
to an external oscillator), the LTC2488 output data rate
can be increased. The duration of the conversion cycle is
41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves
as if the internal oscillator is used.
An increase in fEOSC over the nominal 307.2kHz will translate
into a proportional increase in the maximum output data
rate (up to a maximum of 100sps). The increase in output
rate leads to degradation in offset, full-scale error, and ef-
fective resolution as well as a shift in frequency rejection.
A change in fEOSC results in a proportional change in the
internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
rejection of line frequencies remains unchanged, thus fully
differential input signals with a high degree of symmetry
on both the IN+ and IN– pins will continue to reject line
frequency noise.
An increase in fEOSC also increases the effective dynamic
input and reference current. External RC networks will
continue to have zero differential input current, but the
time required for complete settling (580ns for fEOSC =
307.2kHz) is reduced, proportionally.
Once the external oscillator frequency is increased above
1MHz (a more than 3x increase in output rate) the ef-
fectiveness of internal auto calibration circuits begins
INPUT SIGNAL FREQUENCY (Hz)
250fN252fN254fN256fN258fN260fN262fN
INPUT NORMAL MODE REJECTION (dB)
2488 F17
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
Figure 17. Input Normal Mode Rejection at fS = 256 • fN
INPUT FREQUENCY (Hz)
0
NORMAL MODE REJECTION (dB)
2488 F18
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5
200
Figure 18. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz/60Hz Notch)
INPUT FREQUENCY (Hz)
012.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5
200
NORMAL MODE REJECTION (dB)
2488 F19
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
MEASURED DATA
CALCULATED DATA
Figure 19. Measure Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 150% (60Hz Notch)
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APPLICATIONS INFORMATION
to degrade. This results in larger offset errors, full scale
errors, and decreased resolution (see Figures 20 to 27).
Easy Drive ADCs Simplify Measurement of High
Impedance Sensors
Delta-Sigma ADCs, with their high accuracy and high noise
immunity, are ideal for directly measuring many types
of sensors. Nevertheless, input sampling currents can
overwhelm high source impedances or low-bandwidth,
micropower signal conditioning circuits. The LTC2488
solves this problem by balancing the input currents, thus
simplifying or eliminating the need for signal conditioning
circuits.
A common application for a delta-sigma ADC is thermistor
measurement. Figure 29 shows two examples of thermis-
tor digitization benefiting from the Easy Drive technology.
The first circuit (applied to input channels CH0 and CH1)
uses balanced reference resistors in order to balance the
common mode input/reference voltage and balance the
differential input source resistance. If reference resistors
R1 and R4 are exactly equal, the input current is zero and
no errors result. If these resistors have a 1% tolerance,
the maximum error in measured resistance is 1.6Ω due
to a shift in common mode voltage; far less than the 1%
error of the reference resistors themselves. No amplifier
is required, making this an ideal solution in micropower
applications.
Easy Drive also enables very low power, low bandwidth
amplifiers to drive the input to the LTC2488. As shown
in Figure 29, CH2 is driven by the LT1494. The LT1494
has excellent DC specs for an amplifier with 1.5µA supply
current (the maximum offset voltage is 150µV and the
open loop gain is 100,000). Its 2kHz bandwidth makes it
unsuitable for driving conventional delta sigma ADCs. Add-
ing a 1kΩ, 0.1µF filter solves this problem by providing a
charge reservoir that supplies the LTC2488 instantaneous
current, while the 1k resistor isolates the capacitive load
from the LT1494.
Conventional delta sigma ADCs input sampling current
lead to DC errors as a result of incomplete settling in the
external RC network.
The Easy Drive technology cancels the differential input
current. By balancing the negative input (CH3) with a 1kΩ,
0.1µF network errors due to the common mode input
current are cancelled.
LTC2488
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20 30100
TA = 85°C
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
–10
OFFSET ERROR (ppm OF VREF)
10
30
50
0
20
40
2488 F20
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
FO = EXT CLOCK
OUTPUT DATA RATE (READINGS/SEC)
–3500
–FS ERROR (ppm OF VREF)
–3000
–2000
–1500
–1000
0
2488 F22
–2500
–500
VIN(CM) = VREF(CM)
VCC = VREF = 5V
FO = EXT CLOCK
TA = 85°C
TA = 25°C
010 30
20
OUTPUT DATA RATE (READINGS/SEC)
0
+FS ERROR (ppm OF VREF)
500
1500
2000
2500
3500
2488 F21
1000
3000
VIN(CM) = VREF(CM)
VCC = VREF = 5V
FO = EXT CLOCK
010 30
20
TA = 85°C
TA = 25°C
TA = 25°C, 85°C
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION (BITS)
12
16
18
2488 F23
14
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
FO = EXT CLOCK
RES = LOG 2 (VREF/NOISERMS)
010 30
20
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION (BITS)
12
16
18
14
VIN(CM) = VREF(CM)
VCC = VREF = 5V
FO = EXT CLOCK
RES = LOG 2 (VREF/INLMAX)
2488 F24
TA = 25°C, 85°C
010 30
20
APPLICATIONS INFORMATION
Figure 20. Offset Error vs Output Data
Rate and Temperature
Figure 21. +FS Error vs Output Data
Rate and Temperature
Figure 22.–FS Error vs Output Data Rate
and Temperature
Figure 23. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 24. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 26. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference
Voltage
Figure 27. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference
Voltage
OUTPUT DATA RATE (READINGS/SEC)
–10
OFFSET ERROR (ppm OF VREF)
–5
5
10
20
2488 F25
0
15
VIN(CM) = VREF(CM)
VIN = 0V
FO = EXT CLOCK
TA = 25°C
010 30
20
VCC = 5V, VREF = 2.5V
VCC = VREF = 5V
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION (BITS)
12
16
18
2488 F26
14
VIN(CM) = VREF(CM)
VIN = 0V
FO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/NOISERMS)
010 30
20
VCC = 5V, VREF = 2.5V, 5V
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION (BITS)
12
16
18
14
VIN(CM) = VREF(CM)
VIN = 0V
REF– = GND
FO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/INLMAX)
2488 F27
010 30
20
VCC = 5V, VREF = 2.5V, 5V
Figure 25. Offset Error vs Output Data
Rate and Reference Voltage
LTC2488
28
2488fb
For more information www.linear.com/LTC2488
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
3.00 ±0.10
(2 SIDES)
4.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ± 0.10
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
3.00 REF
1.70 ± 0.05
17
148
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DE14) DFN 0806 REV B
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 ±0.05
0.70 ±0.05
3.60 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05 0.25 ± 0.05
0.50 BSC
3.30 ±0.05 3.30 ±0.10
0.50 BSC
APPLICATIONS INFORMATION
V
CC + 0.3V
GND GND
GND
–0.3V
GND
–0.3V
–0.3V
(a) Arbitrary (b) Fully Differential
(d) Pseudo-Differential Unipolar
IN– or COM Grounded
(c) Pseudo Differential Bipolar
IN– or COM Biased
VREF
2
VREF
2
VREF
2
VREF
2
VREF
2
–VREF
2
–VREF
2
–VREF
2
Selected IN+ Ch
Selected IN
–
Ch or COM
VCC
VCC
2488 F28
VCC
VCC
Figure 28. Input Range
LTC2488
29
2488fb
For more information www.linear.com/LTC2488
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 7/10 Revised Typical Application drawing
Added Note 18
1
4, 5
B 11/14 Clarify performance vs fO frequency, reduced external oscillator max frequency to 1MHz
Clarify input voltage range
5, 7, 27
3, 12, 28
LTC2488
30
2488fb
For more information www.linear.com/LTC2488
LINEAR TECHNOLOGY CORPORATION 2006
LT 1114 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2488
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LT1460 Micropower Series Reference 0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LT1790 Micropower SOT-23 Low Dropout Reference Family 0.05% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400 24-Bit, No Latency ΔS ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410 24-Bit, No Latency ΔS ADC with Differential Inputs 0.8µVRMS Noise, 2ppm INL
LTC2411/LTC2411-1 24-Bit, No Latency ΔS ADCs with Differential Inputs in MSOP 1.45µVRMS Noise, 2ppm INL, Simultaneous 50Hz/60Hz
Rejection (LTC2411-1)
LTC2413 24-Bit, No Latency ΔS ADC with Differential Inputs Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
LTC2440 High Speed, Low Noise 24-Bit ΔS ADC 3.5kHz Output Rate, 200nVRMS Noise, 24.6 ENOBs
LTC2442 24-Bit, High Speed, 4-Channel/2-Channel ΔS ADC with Integrated
Amplifier
8kHz Output Rate, 220nVRMS Noise, Simultaneous 50Hz/60Hz
Rejection
LTC2449 24-Bit, High Speed, 8-Channel/16-Channel ΔS ADC 8kHz Output Rate, 200nVRMS Noise, Simultaneous 50Hz/60Hz
Rejection
LTC2480/LTC2482/
LTC2484
16-Bit/24-Bit ΔS ADCs with Easy Drive Inputs, 600nVRMS Noise,
Programmable Gain, and Temperature Sensor
Pin Compatible with 16-Bit and 24-Bit Versions
LTC2481/LTC2483/
LTC2485
16-Bit/24-Bit ΔS ADCs with Easy Drive Inputs, 600nVRMS Noise,
I2C Interface, Programmable Gain, and Temperature Sensor
Pin Compatible with 16-Bit and 24-Bit Versions
LTC2492 2-Channel, 14-Channel 24-Bit ΔS ADC with Easy Drive Inputs and
Temperature Sensor
Pin Compatible with LTC2488
LTC2496/LTC2498 16-Channel/8-Channel 16-Bit/24-Bit ΔS ADC with Easy Drive
Inputs and SPI Interface
Timing Compatible with LTC2492
LTC2449 High Speed 16 Input, ΔS ADC 8kHz Output Rate, Variable Speed Resolution
TYPICAL APPLICATION
VCC FO
SCK
SDI
GND
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2492
3-WIRE
SPI INTERFACE
2488 F29
SDO
12 1
REF+
13
REF–
14
CH0
8
CH1
9
CH2
10
CH3
11
COM
7
3
5
6
4
2
5V
0.1µF
10µF
CS
5V
IIN+ = 0
IIN– = 0
R1
51.1k
R4
51.1k
C4
0.1µF
C3
0.1µF
R3
10k TO 100k
–
+
102k
5V
5V
LT1494
0.1µF
0.1µF
0.1µF
1k
1k
10k TO 100k
Figure 29. Easy Drive ADCs Simplify Measurement of High Impedance Sensors