ANALOG DEVICES CMOS Latched 8/16 Channel Analog Multiplexers ADG526A/ADG527A FEATURES 44V Supply Maximum Rating Vss to Vpp Analog Signal Range Single/Dual Supply Specifications Wide Supply Ranges (10.8V to 16.5V) Microprocessor Compatible (100ns WR Pulse) Extended Plastic Temperature Range (-40C to + 85C) Low Leakage (20pA typ) Low Power Dissipation (28mW max) Available in DIP, SOIC, PLCC and LCCC Packages Superior Alternative to: DG526 DG527 GENERAL DESCRIPTION The ADGS26A and ADG527A are CMOS monolithic analog multiplexers with 16 channels and dual 8 channels respectively. On-chip latches facilitate microprocessor interfacing. The ADG526A switches one of 16 inputs to a common output de- pending on the state of four binary addresses and an enable input. The ADG527A switches one of 8 differential inputs to a common differential output depending on the state of three binary addresses and an enable input. Both devices have TTL and 5V CMOS logic compatible digital inputs. The ADG526A and ADGS527A are designed on an enhanced LC?MOS process which gives an increased signal capability of Vsg to Vpp and enables operation over a wide range of supply voltages. The devices can comfortably operate anywhere in the 10.8V to 16.5V single or dual supply range. These multiplexers also feature high switching speeds and low Ron. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may resuit from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAMS ADG526A ADG527A DECODER/ LATCHES OO-O-O-0-O AO A1 A2 A3 ENRS AO Al A2 EN RS PRODUCT HIGHLIGHTS 1. Single/Dual Supply Specifications with a Wide Tolerance: The devices are specified in the 10.8V to 16.5V range for both single and dual supplies. 2. Easily Interfaced: The ADGS26A and ADG527A can be easily interfaced with microprocessors. The WR signal latches the state of the Address control lines and the Enable line. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off). RS can be tied to the micro- processor reset pin. 3. Extended Signal Range: The enhanced LC2MOS processing results in a high breakdown and an increased analog signal range of Vss to Vpp. 4, Break-Before-Make Switching: Switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 5. Low Leakage: Leakage currents in the range of 20pA make these multiplexers suitable for high precision circuits. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 Telex: 924491 Cable: ANALOG NORWOODMASSADGS26A/ADG527A SPECIFICATIONS Dual Supply v,, = +10.28v to +16.5v, V.s = 10.8V to 16.5V unless otherwise noted.) ADGS26A ADG526A ADG526A ADG527A ADGS527A ADGS27A K Version B Version T Version 40C to 40C to -55Cto Parameter 425C +85C +25C + 85C 425C +125C_|_ Units Comments ANALOG SWITCH Analog Signal Range Vss Vss Vsg Vsg Voss Vss Vmin Vpp Vpp Vpp Vop Vpp = Vop Vmax Ron 280 280 280 Otyp 10V<Vs< + 10V, Ips= 1mA; Test Circuit 1 450 600 450 600 450 600 OQ max 300 400 300 400 2 max Vpp = 15V(+ 10%), Vsg= 15V(+ 10%) 300 400 O max Vpp = 15V( 5%), Vss= 15V( + 5%) Ron Drift 0.6 0.6 0.6 %/C typ -10VSVs5s + 10V, Ips = 1mA Ron Match 5 5 5 % typ -10V<Vs< + 10V, Ips = 1mA 1; (OFF), Off Input Leakage 0.02 0.02 0.02 nAtyp V1= + 10V, V2 = + 10V; Test Circuit 2 1 50 1 50 1 50 nA max Ip (OFF), Off Output Leakage 0.04 0.04 0.04 nA typ V1=+10V, V2= + 10V; Test Circuit 3 ADG526A 1 200 1 200 1 200 nA max ADG527A 1 100 1 100 1 100 nA max Ip (ON), On Channel Leakage 0.04 0.04 0.04 nAtyp V1= +10V, V2= + 10V; Test Circuit 4 ADG526A 1 200 1 200 1 200 nA max ADG527A 1 100 1 100 1 100 nA max Ipirr; Differential Off Output Leakage (ADG527A only) 25 25 25 nA max V1= + 10V, V2= +10V; Test Circuit 5 DIGITAL CONTROL Vinn; Input High Voltage 2.4 2.4 2.4 Vmin Vin, Input Low Voltage 0.8 0.8 0.8 V max Tp or Ip 1 1 ] pA max Vin=0to Vpp Cy Digital Input Capacitance 8 8 8 pF max DYNAMIC CHARACTERISTICS! UPRANSITION 200 200 200 ns typ V1= = 10V, V2= + 10V; Test Circuit 6 300 400 300 400 300 400 ns max lopEN 50 50 50 ns typ Test Circuit 7 25 10 25 10 25 10 ns min ton (EN, WR) 200 200 200 ns typ Test Circuits 8 and 9 300 400 300 400 300 400 ns max torr (EN, RS) 200 200 200 ns typ Test Circuits 8 and 10 300 400 300 400 300 400 ns max ty Write Pulse Width 100 120 100 120 100 130 ns min See Figure i ts Address, Enable Setup Time 100 100 100 ns min See Figure 1 try Address, Enable Hold Time 10 10 10 ns min See Figure | trs Reset Pulse Width 100 100 100 ns min See Figure 2 OFF Isolation 68 68 68 dB typ Ven = 0.8V, Ry = 1k, C, = 15pF, 50 50 50 dB min Vs=7V rms, f= 100kHz Cs (OFF) 5 5 5 pF typ Ven = 0.8V Cp (OFF) ADG526A 44 44 44 pF typ Ven =0.8V ADG527A 22 22 22 pF typ Quy, Charge Injection 4 4 4 pCtyp Rs =02, Vs = 0V; Test Circuit 11 POWER SUPPLY Ipp 0.6 0.6 0.6 mA typ Vin = Vint or Ving 15 1.5 15 mA max Iss 20 20 - 20 pA typ Vin= Vin. or Vint 0.2 0.2 0.2 mA max Power Dissipation 10 10 10 mW typ 28 28 28 mW max NOTE Sample tested at + 25C to ensure compliance. Specifications subject to change without notice. -2- REV. ASingle Supply (v,, = +10.8v to +16.5v, Ve = GND = OV unless otherwise noted.) ADGS2GA/ADG527A ADGS26A ADG526A ADG526A ADGS527A ADG527A ADG527A K Version B Version T Version - 40C to -40C to -55Cto Parameter +25C = +85C +25C = +85C 425C = +125C Units Comments ANALOG SWITCH Analog Signal Range Vss Vss Vss Vss Vss Vss V min Vpp Vpp Vpp Vpp Vpp Vpp Vmax Ron 500 500 500 Otyp OV<V5< + 10V, Ips =0.5mA; Test Circuit 1 700 1000 700 1000 700 1000 max Ron Drift 0.6 0.6 0.6 %PCtyp | OV<Vs<+ 10V, Ips=0.5mA Ron Match 5 5 5 % typ OV<Vss + 10V, Ips =0.5mA Is (OFF), Off Input Leakage 0.02 0.02 0.02 nA typ V1= + 1OV/0V, V2 =0V/+ 10V; 1 50 1 50 1 50 nA max Test Circuit 2 Ip (OFF), Off Output Leakage 0.04 0.04 0.04 nA typ V1= + 10V/0V, V2 =0V/+ 10V; ADG526A 1 200 1 200 1 200 nA max Test Circuit 3 ADG527A 1 100 1 100 1 100 nA max Ip (ON), On Channel Leakage 0.04 0.04 0.04 nA typ V1l= + 10V/0V, V2 =0V/+ 10V; ADG526A 1 200 1 200 1 200 nA max Test Circuit 4 ADG527A 1 100 1 100 1 100 nA max Iprer, Differential Off Output VI= + 1OV/0V, V2 =0V/+ 10V; Leakage (ADG527A only) 25 25 25 nA max Test Circuit 5 DIGITALCONTROL Vint Input High Voltage 2.4 2.4 2.4 Vmin Vin, Input Low Voltage 0.8 0.8 0.8 Vmax tint or linn 1 1 1 pA max Vin=0to Vpp Cyy Digital Input Capacitance 8 8 8 pF max DYNAMIC CHARACTERISTICS! UPRANSITION 300 300 300 nstyp V1= + LOV/OV, V2=0V/+ 10V; 450 600 450 600 450 600 ns max Test Circuit 6 lopeN 50 50 50 ns typ Test Circuit 7 25 10 25 10 25 10 ns min ton (EN, WR) 250 250 250 ns typ Test Circuits 8 and 9 450 600 450 600 450 600 ns max torr (EN, RS) 250 250 250 ns typ Test Circuits 8 and 10 450 600 450 600 450 600 ns max tw Write Pulse Width 100 120 100 120 100 130 ns min See Figure | ts Address, Enable Setup Time 100 100 100 ns min See Figure 1 try Address, Enable Hold Time 10 10 10 ns min See Figure 1 ters Reset Pulse Width 100 100 100 ns min See Figure 2 OFF Isolation 68 68 68 dBtyp Ven = 0.8V, Ry = 1kO, Cy = 15pF, 50 50 50 dB min Vs =3.5V rms, f= 100kHz Cs (OFF) 5 5 5 pF typ Ven =0.8V Cp (OFF) ADG526A 44 44 44 pF typ Ven =0.8V ADG527A 22 22 22 pF typ Qiny, Charge Injection 4 4 4 pCtyp Rs =00,Vs5 =0V; Test Circuit 11 POWER SUPPLY Ipp 0.6 0.6 0.6 mA typ Vin= Vint or Vinu 1.5 15 1.5 mA max Power Dissipation ll ll 11 mW typ 25 25 25 mW max NOTE Sample tested at + 25C to ensure compliance. Specifications subject to change without notice. REV. A -3-ADGS26A/ADG527A TIMING DIAGRAMS meal fe av 2.0V EN, AO, At, Az, (A3 ogy | | Figure 1. Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR. aS 1.5V eS pt#_ torr (RS) | Vo SWITCH OUTPUT 0.8 Vo K ov Figure 2. Figure 2 shows the Reset Pulse Width, tgs, and Reset Turn-off Time, torr (RS). Note: All digital input signals rise and fall times measured from 10% to 90% of 3V. tr=te=20ns. ABSOLUTE MAXIMUM RATINGS* (Ta = + 25C unless otherwise noted) Vpp to Vsgs 6 we es 44V Vpp toGND ......... 0.000 ee ee eee 25V Vss to GND... 0. tt es 25V Analog Inputs! Voltage atS,;D .. 2... ee ee ee ee Vss 2V to Vpp +2Vor 20mA, Whichever Occurs First Continuous Current, SorD ............. 20mA Pulsed Current $ or D lms Duration, 10% Duty Cycle .......... 40mA Digital Inputs! Voltage at A, EN, WR,RS........... Vss 4V to Vop +4V or 20mA, Whichever Occurs First Power Dissipation (Any Package) Upto +75 2. ee ee Derates above +75C by... 2... ee ee Operating Temperature Commerical (K Version) - 40C to + 85C Industrial (B Version)... ........ 40C to + 85C Extended (T Version). .......... 55C to +125C Storage Temperature Range. ........ 65C to +150C Lead Temperature (Soldering, 10sec)... ....... + 300C NOTE 1Overvoltage at A, EN, WR, RS, S or D will be clamped by diodes. Current should be limited to the maximum rating above. *COMMENT: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION: ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electro- static fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are inserted. ETT eE sr ESD SENSITIVE DEVICE ORDERING GUIDE Temperature Package NOTES 1 +2 Model Range Option 'To order MIL-STD-883, Class B processed parts, add ADG526AKN -40Cto +85C | N-28 /883B to part number. See Analog Devices Military 4n> 9 . Products Databook (1990) for military data. ADGS26AKR 40C to + 85C R-28 ?E = Leadless Ceramic Chip Carrier; N = Narrow Plastic ADGS26AKP | 40Cto + 85C | P-28A DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; ADG526ABQ 40C to + 85C | Q-28 R = 0.3 Small Outline IC (SOIC). ADG526ATQ? | 55Cto + 125C | Q-28 Standard Military Drawing (SMD) assigned by DESC. ADGS26ATE? | 55Cto +125C | E-28A SMD numbers are 6 5962-89710013X (ADG526ATE/883B) ADG5S27AKN | 40Cto +85C | N-28 $962-8971001XX (ADG526ATQ/883B) ADG527AKR 40Cto +85C | R-28 962-89710023X (ADG527ATE/883B) ADG527AKP ~40Cto +85C | P-28A 5962-897 1002XX (ADG527ATQ/883B) ADG527ABQ 40Cto + 85C | Q-28 ADG527ATQ? | 55Cto + 125C | Q-28 ADG527ATE? 55C to + 125C | E-28A -4- REV. AADGS26A/ADG527A TRUTH TABLES A3|A2{A1]A0|EN|WR {RS | ONSWITCH XPXUTXTX XI $1 Retains Previous Switch Condition X |X IXTX | X[X 0 NONE (Address and Enable Latches Cleared) A2 [Al] Ao | EN | WR| RS | ONSWITCHPAIR XIX TXIX10]0 1 NONE x xX x xX Fil Retains Previous Switch Condition Qo {o fo jo [1] 0 1 1 xX [XIX fx b NONE (Address and Enable 010 fO J1 J1 {0 1 2 Latches Cleared) 0 70 {! JO FIO 1 3 x x x 0 0 1 NONE o 10 {1 71 11/90 1 4 0 0 6 1 0 1 1 Oo f1 $0 JO F140 1 5 0 0 1 1 0 1 2 Oo {1 70 71 1] 0 1 6 0 1 0 1 0 1 3 0 11 71 0 1/0 1 7 0 1 1 1 0 1 4 Oo yl ql fl 170 1 8 1 0 0 1 0 1 5 1 10 70 [0 1] 0 1 9 1 0 1 1 0 1 6 1 40 [oO 71 1] 0 1 10 1 1 0 1 0 1 7 170 {1 70 Jl fo 1 1] 1 1 1 1 0 1 8 1/0 $1 4) 170 1 12 1 Jl JO [0 Figo 1 13 X = Dont Care i 140 71 170 1 14 1 1 $1 1/0 1] 0 1 15 ADG527A 1 $1 9) q1 1] 0 1 16 = Dont Care ADG526A PIN CONFIGURATIONS DIP, SOIC \/ Voo [1 | e 23/0 PLCC we] = seg ios RS| 3 26| $8 (| 4 3 2 1 28 27 26 s [4 | [25] 87 ms s5[s | 24 | s sis 5 sa [C5 | 23| s5 814 6 suf] ADG526A a2] sa ADG526A 513 7 TOP VIEW TOP VIEW ADG526A si2[a | (Not to Scale} [21] $3 (Not to Scale} S12 8 TOP VIEW su 9 (Not to Scate) su[s | 20] S2 $10 10 $10 | 10 19/81 s911 sola 18] EN GND | 12 17] Ao 1213 14 15 16 17 18 wr [13 16] AI ge 22285 A3 [14 15 | Az NC = NO CONNECT NC = NO CONNECT NS vi tle 281 DA aa Bee is 2g B oa[2 | 27) Ves 4 3 2 1 28 27 26 as [a | 26) S8A Mi sea [4 | 25 | S7A S7B 5 S7A s7e [6s | 24] SGA , SEB 6 S6A ADG527A SSB 7 S5A S6B S5A (e| ADG527A 2 TOP VIEW ADG527A S4B 8 S4a ss8[7 | 22] S4a (Not to Scale) TOP VIEW TOP VIEW S38 $ (Not to Scale) S3A saps | (Not to Scale) 21] S3A S2B 10 S2A s3B| 9 20] S2A [2] S1B 11 S1A $28 | 10 19] S1A $1B] 11 18] EN 1213: 14 15 16 17 18 ono [12 17] a0 2 2222 % wa laa telat NC = NOCONNECT NC =NO CONNECT ne [14] 15 | a2 NC = NOCONNECT REV. A -5-ADG526A/ADG527A Typical Performance Characteristics The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5V. 700 600 Vop = +10.8V Vss = OV 500 NI 400 G y Voo = +15V ! L Vss = 0 300 JN DE 200 100 0 20 -15 -5 5 10 15 20 VolVs] - Volts Ron as a Function of Vp(Vs): Dual Supply Voltage, Ta = +25C -10 100 te: t68v 10 a & woe a) = 4 A a on | a aa Is (OFF) re va 25 (35 45 55 65 7 85 95 105 115 125 TEMPERATURE - C Leakage Current as a Function of Temperature (Note: Leakage Currents Reduce as the Supply Voltages Reduce) 800 = 700 500 SINGLE SUPPLY 400 tyRANSITION ~ ns DUAL SUPPLY 300 200 100 5 6 7 8 9 10 11 12 13 14 15 SUPPLY VOLTAGE- Volts transition VS. Supply Voltage: Dual and Single Supplies, Ta = 425C (Note: For Vop and {Vss/ < 10V; V1 = Vop/Vss, V2 = Vss/Vpp. See Test Circuit 6) 700 600 Vop = +5V Vss = -5V a 400 3 \ Vop = +10.8V * 300 Veo = 10.8V wt Tot LAL Vop = +15V " Vss = 15V 100 0 -20 -15 -10 -5 Q 5 10 15 20 Vo(Vs}- Volts Ron as a Function of Vp{Vs): Single Supply Voltage, Ta = +25C 1g 1.8 > 17 = ~ w 9 8 Pp] E 1.6 15 l __1 ! ! ! 6 7 8 9 10 11 12 13 14 15 SUPPLY VOLTAGE - Volts Trigger Levels vs. Power Supply Voltage, Dual or Single Sup- ply, Ta = +25C 08 0.6 lop-mA 0.4 0.2 l 1 i l 1 5 6 7 8 9 10 #11 #12 #13014~15 ~=16 = 17 SUPPLY VOLTAGE - Volts lpp vs. Supply Voltage: Dual or Single Supply, Ta, = +25C REV. ATest CircuitsADG526A/ADG527A Js (OFF) ( A v1 TEST CIRCUIT Ron los _ Vs Row -4 TEST CIRCUIT 2 TEST CIRCUIT 3 EN Is (OFF) +0.8V Ip (OFF) +0.8V A } Ip (OFF) VI t V2 TEST CIRCUIT4 Ip(ON) Voo Vss Voo Vss t I D - o EN 2.4V Ip (ON) vi GND Vv t v2 TEST CIRCUITS = Ipirr Vpp Vs Vop Vss EN [} 0.8V TO e DA (A) ADG527A Oo o4 DB (A) GND vt v 4 lowe = toa (OFF) log (OFF) TEST CIRCUIT6 SWITCHING TIME OF MULTIPLEXER, trransrrion Voo Vss 3v | | ADDRESS Tt T ov | \ A3 Veo Vs | | A2 s1 --vI1 | | Vv Al | | ' 30% IN @ von $2 THRU $15 i, 'f) output I "0 S16 v2 | ADG526A* 1 \ 90% V 24v 1 EN p [OUTPUT a he RE GND WA mma = 35pF transition transition o *SIMILAR CONNECTION FOR ADG527A TEST CIRCUIT7 BREAK-BEFORE-MAKE DELAY, topen Vop Vss A3 Voo Vss 3v ADDRESS $1 +5V DRIVE (Vin) a2 ov | | $2 THRU $15 = @ me ry Ao $16 . ADG526A* Ii 50% guTPUT aay 7 EN LourPeT 1 < >| oe RS GND Wal 2 topen = *SIMILAR CONNECTION FOR ADG527A ; ka r 35pF TEST CIRCUIT8 ENABLE DELAY, ton (EN), torr (EN) Voo Vss wT ENABLE T T _ frox-\ ae (Vin) 2.4V RS Vop Vsg ov 130% I a3 $1 - +5V | | | A2 2 THRU S16 | 90% ourput AI Tw | \ 10% ag ADGS26A* | tou _ lore | EN OUTPUT (EN) e __ < Vw 500 GND WR fue = 35pF SIMILAR CONNECTION FOR ADG527A TEST CIRCUIT9 WRITE TURN-ON TIME, ton Voor = Vss av wa Voo Vss ks of DRIVE (Vin) 2.4v J] EN $1 ov 1 Ag (WR) P +8V OUTPUT ' $2 THRU S16 : ry 1 I OUTPUT Al ADG526A* ' 20% | AO D he ton (VR) | 4 wR GND = 500. VW NOTE: DEVICE MUST BE RESET PRIOR TO Vin APPLYING WR PULSE 2 1ka 3 35pF *SIMILAR CONNECTION FOR ADG527A TEST CIRCUIT 10 RESET TURN-OFF TIME, torr (RS) Voo Vss 3v RS DRIVE [V, Yoo Vss ks of (uu) 2av J en SI} +5V ov 4 A3 \ A? S2 THRU S16 ry 80% ax ADG526A* i OUTPUT OUTPUT \ ' AO D| fe tore (RS) WR 1k2 RS GND T35eF NOTE: WR MUST BE PULSED LOW PRIOR TO APPLYING RS PULSE. Vin *SIMILAR CONNECTION FOR ADG527AADG526A/ADG527A TEST CIRCUIT 11 CHARGEINJECTION Voo Vss y TT y \ / Ao Yoo = Vss iN a RS f-24V " 4 Vo AVo ron ae4 ag ADG526A* nt = = + Vo va EN Fa | | n Ny = CL Xx AVo t- nT 2 500 GND WA b *SIMILAR CONNECTION FOR ADGS527A TERMINOLOGY torr (EN) Delay time between the 50% and 10% points of Ron Ohmic resistance between terminals D and $ the digital input and switch OFF condition Ron Match Difference between the Roy of any two channels trransition Delay time between the 50% and 90% points of Ron Drift Change in Ron versus temperature the digital inputs and switch ON condition Is (OFF) Source terminal leakage current when the switch when switching from one address state to is off another Ip (OFF) Drain terminal leakage current when the switch lOPEN OFF time measur ed between 50% points of is off both switches when switching from one address Ip (ON) Leakage current that flows from the closed switch state to another - censs into the body Vin Maximum input voltage for Logic 0 Vs (Vp) Analog voltage on terminal or D Vinu Minimum input voltage for Logic sy Cs (OFF) Channel input capacitance for OFF condition lint (ine) Input current of the digital input Cp (OFF) Channel output capacitance for OFF condition Vpp Most positive voltage supply rome Digital input capacitance Vss Most negative voltage supply ton (EN) Delay time between the 50% and 90% points of !pD Positive supply current Isg Negative supply current the digital input and switch ON condition MECHANICAL INFORMATION OUTLINE DIMENSIONS Dimension shown in inches and (mm). 28-Pin Plastic DIP (Suffix N) 0.2 eo PVE EUV 0.16 (4.07) 1.45 (36.83) 0.608 115.4) 0.14 (3.66) 1.44 (36.58) fc 0.594 (15.09) (5.08) MAX Y tT 0.012 (0.305) j 0.008 10.203) cca 7 >| be 0.176 (4.45) 0.065 0.66) 0.02 (0.508) 0.105 (2.67) 012 13.06) 0.048 (1.15) 0.015 (0.381) 0.095 (2.42) 28-Terminal Leadless Ceramic Chip Carrier LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TiN PLATED KOVAR OR ALLOY 42 28-Pin SOIC (R) Package 28-Pin Cerdip (Suffix Q) eoonooooonnoon > ose 13.33) | UUUDUUUNUUUUUUU 0.22 (5.69) GLASS 0.06 (1.52) wax SEALANT . o_o COSTE ml i Jor jf (3.1751 MIN i 0.012 (0.3051 } 6.008 (0.203) 9.02 (0.5). 0.076 (0.406) aa LEAO NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42 0.18 {4.579 0.62 (15.74) MAX - OSS toa w 0.11 (2.79 0,099 (2.28) arr 28-Terminal Plastic Leaded Chip Carrier (Suffix E) (Suffix P) rows pssst RAARAARAAAAA AR Aff 9.06411.63) 0.045 (1.14) 0.075 (1.91) REF 8 8 , 0.300 (7.60) 2 4 0.292 (7.40) Oo or 0 0.080 = 2.008 0.419 (10.68) O ~ 3 0.318(90.00) 4 0.430 (105 , Ta q Top 0 0.390 (9.9) P view 4 9.021 (0.5331 HHHHHHHUHHHYYHEHEY q H FF tors teat 0.512 (13.00) q H o.032 (0.8121 0.496 (12.60) q O oa anne toesH ane 85) Oooous .093 (2.95) 0.458 (11.63)? (11,682) = ; 0.040 debe o.4a2 (11.23) ee ee aso St 0.180 44.51 Dawoiez ets 0.050 (1.27) BSG 0.019 (0.49) 0.012 (0.3) 0.495 (12.87 0.165 (4.20) ores 0.014 (0.35) 0.004 (0.1) gags 12 37 sa. HON, CONTROLS THE OVERALL PACKAGE THICKNESS. 1 THIS DIMENS! 2 APPLIES TO ALL FOUR SIDES. ALL TERMINALS ARE GOLD PLATED ; 0.013 (0.32) 0.009 (0.23) t eh 0.005 (1.27) 0.016 (0.40) REV. A C1153a92/88 PRINTED IN U.S.A.