1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE Features * Programmable Operation: - Device Latency: 4 - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 13/10/1 Addressing (row/column/bank) - M1Y25664TUH4A2F * 14/10/1 Addressing (row/column/bank) - M1Y51264TU88A2B * 14/10/2 Addressing (row/column/bank) - M1Y1G64TU8HA2B * 7.8s Max. Average Periodic Refresh Interval * Serial Presence Detect * Gold contacts * M1Y25664TUH4A2F in 84-ball FBGA Package * M1Y51264TU88A2B and M1Y1G64TU8HA2B in 60-ball FBGA Package * RoHS Compliance * JEDEC Standard 240-pin Dual In-Line Memory Module * 32Mx64 DDR2 UDIMM based on 32Mx16 DDR2 SDRAM * 128Mx64 and 64Mx64 DDR2 UDIMM based on 64Mx8 DDR2 SDRAM * Performance: PC2-4200 Speed Sort DIMM Latency* 37B Unit 4 f CK Clock Frequency 266 t CK Clock Cycle 3.7 MHz ns f DQ DQ Burst Frequency 533 MHz * Intended for 266MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = VDDQ = 1.8Volt 0.1 * SDRAMs have 4 internal banks for concurrent operation * Differential clock inputs * Data is read or written on both clock edges * Bi-directional data strobe with one clock cycle preamble and one-half clock post-amble * Address and control signals are fully synchronous to positive clock edge Description M1Y25664TUH4A2F, M1Y51264TU88A2B and M1Y1G64TU8HA2B are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as a one-rank 32M x 64, 64Mx64 and two ranks 128Mx64 high-speed memory array. Modules use four 32Mx16 DDR2 SDRAMs (M1Y25664TUH4A2F), eight 64Mx8 (M1Y51264TU88A2B) and sixteen 64Mx8 (M1Y1G64TU8HA2B) DDR2 SDRAMs in FBGA packages. These DIMMs manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All Super Elixir DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 266MHz clock speeds and achieves high-speed data transfer rates of up to 533MHz. Prior to any access operation, the device latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 (M1Y25664TUH4A2F), A0-A13 (M1Y51264TU88A2B and M1Y1G64TU8HA2B) and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. Ordering Information (Green) Part Number REV 1.0 06/2006 Speed Organization Leads Power Note 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM M1Y25664TUH4A2F -37B M1Y51264TU88A2B -37B 32Mx64 266MHz (3.7ns @ CL = 4) DDR2-533 M1Y1G64TU8HA2B -37B REV 1.0 06/2006 PC2-4200 64Mx64 128Mx64 84 Ball Gold 1.8V 60 Ball 60 Ball 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Pin Description CK0, CKE0, CKE1 Differential Clock Inputs DQ0-DQ63 Clock Enable CB0-CB7 Row Address Strobe DQS0-DQS8 Column Address Strobe , A0-A9, A11-A13 A10/AP BA0, BA1 ODT0, ODT1 NC REV 1.0 06/2006 Data input/output ECC Check Bit Data Input/Output Bidirectional data strobes DM0-DM8/DQS9-17 Input Data Mask/High Data Strobes Write Enable - Chip Selects VDD Power (1.8V) VREF Ref. Voltage for SSTL_18 inputs Address Inputs Column Address Input/Auto-precharge VDDSPD SDRAM Bank Address Inputs Differential data strobes Serial EEPROM positive power supply VSS Ground Reset pin SCL Serial Presence Detect Clock Input Active termination control lines SDA No Connect SA0-2 Serial Presence Detect Data input/output Serial Presence Detect Address Inputs 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Pinout Pin Front Pin Front Pin Front Pin 1 VREF 42 NC 82 VSS 121 VSS 2 VSS 43 NC 83 122 DQ4 3 DQ0 44 VSS 84 DQS4 123 DQ5 4 DQ1 45 NC 85 VSS 124 5 VSS 46 NC 86 DQ34 125 47 VSS 87 DQ35 126 DQS0 48 NC 88 VSS 127 8 VSS 49 NC 89 DQ40 9 DQ2 50 VSS 90 DQ41 10 DQ3 51 VDDQ 91 VSS 130 11 VSS 52 CKE0 92 131 12 DQ8 53 VDD 93 DQS5 132 13 DQ9 54 NC 94 VSS 14 VSS 55 NC 95 56 VDDQ 96 A11 97 VSS 136 VSS CK1 6 7 15 Back Pin Back Pin Back 162 NC 202 DM4 163 VSS 203 NC 164 NC 204 VSS VSS 165 NC 205 DQ38 DM0, DQS9 166 VSS 206 DQ39 167 NC 207 VSS VSS 168 NC 208 DQ44 128 DQ6 169 VSS 209 DQ45 129 DQ7 170 VDDQ 210 VSS VSS 171 CKE1 211 DM5 DQ12 172 VDD 212 NC DQ13 173 NC 213 VSS 133 VSS 174 NC 214 DQ46 DQ42 134 DM1, DQS10 DQ47 DQ43 135 175 VDDQ 215 176 A12 216 VSS 177 A9 217 DQ52 178 VDD 218 DQ53 179 A8 219 VSS CK2 16 DQS1 57 17 VSS 58 A7 98 DQ48 137 18 NC 59 VDD 99 DQ49 138 19 NC 60 A5 100 VSS 139 VSS 180 A6 220 20 VSS 61 A4 101 SA2 140 DQ14 181 VDDQ 221 21 DQ10 62 VDDQ 102 NC 141 DQ15 182 A3 222 VSS 22 DQ11 63 A2 103 VSS 142 VSS 183 A1 223 DM6 23 VSS 64 VDD 104 143 DQ20 184 VDD 224 NC 24 DQ16 144 DQ21 225 VSS 25 DQ17 65 VSS 106 VSS 145 VSS 185 226 DQ54 26 VSS 66 VSS 107 DQ50 146 DM2 186 227 DQ55 67 VDD 108 DQ51 147 NC 187 VDD 228 VSS 27 KEY 105 DQS6 KEY CK0 28 DQS2 68 NC 109 VSS 148 VSS 188 A0 229 DQ60 29 VSS 69 VDD 110 DQ56 149 DQ22 189 VDD 230 DQ61 30 DQ18 70 A10/AP 111 DQ57 150 DQ23 190 BA1 231 VSS 31 DQ19 71 BA0 112 VSS 151 VSS 191 VDDQ 232 DM7 32 VSS 72 VDDQ 113 152 DQ28 192 233 NC 33 DQ24 73 153 DQ29 193 234 VSS 34 DQ25 74 35 VSS 75 36 114 VDDQ 76 DQS7 115 VSS 154 VSS 194 VDDQ 235 DQ62 116 DQ58 155 DM3 195 ODT0 236 DQ63 117 DQ59 156 NC 196 A13 237 VSS 37 DQS3 77 ODT1 118 VSS 157 VSS 197 VDD 238 VDDSPD 38 VSS 78 VDDQ 119 SDA 158 DQ30 198 VSS 239 SA0 39 DQ26 79 VSS 120 SCL 159 DQ31 199 DQ36 240 SA1 40 DQ27 80 DQ32 160 VSS 200 DQ37 41 VSS 81 DQ33 161 NC 201 VSS REV 1.0 06/2006 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Input/Output Functional Description Symbol Type CK0, CK1, CK2 (SSTL) The positive line of the differential pair of system clock inputs which drives the input to Positive the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the Edge rising edge of their associated clocks. (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to Edge the on-DIMM PLL. , , Polarity Function CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. , (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. (SSTL) Active Low When sampled at the positive rising edge of the clock, operation to be executed by the SDRAM. , , , , define the VREF Supply Reference voltage for SSTL-18 inputs VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, for A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge, Row Address A13 used on X4 and X8 component only. A0 - A9 A10/AP A11 - A13 (SSTL) - DQ0 - DQ63 (SSTL) Active High VDD, VSS Supply DQS0-DQS8 - (SSTL) DM0-DM8 Input On-Die Termination control signals Data and Check Bit Input/Output pins. Power and ground for the DDR SDRAM input buffers and core logic Negative and Data strobe for input and output data; Positive Edge Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. VDDSPD REV 1.0 06/2006 Supply Serial EEPROM positive power supply. 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) DQS0 DQS4 LDQS DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 D0 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BA0-BA1 A0-A12 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 D1 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D3 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 BA0-BA1 : SDRAMs D0-D3 VDDSPD VDD/VDDQ VREF VSS VDDID : SDRAMs D0-D3 06/2006 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 A0-A12 : SDRAMs D0-D3 : SDRAMs D0-D3 REV 1.0 D2 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS6 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 : SDRAMs D0-D3 CKE0 CKE : SDRAMs D0-D3 ODT0 ODT : SDRAMs D0-D3 Notes : LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/CS relationships are maintained as shown. 3. DQ/DQS/ resistors are 22 Ohms +/- 5% 4. BAx, Ax, , , resistors are 5.1 Ohms +/- 5% 5. Address and control resistors are 22 Ohms +/- 5% SPD D0-D3 D0-D3 D0-D3 Serial PD SCL WP A0 A1 A2 SA0 SA1 SA2 SDA 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) REV 1.0 06/2006 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (1GB, 1 Rank, 64Mx8 DDR2 SDRAMs) REV 1.0 06/2006 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (256MB) 32Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 32Mx16, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description 0 Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 4 SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2-533 (-37B) DDR2-533 (-37B) 128 80 256 08 DDR2-SDRAM 08 Number of Row Addresses on Assembly 13 0D Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Bank, Package, and Height 1 rank, Height=30mm 60 6 Data Width of this Assembly X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 9 DDR2 SDRAM Device Cycle Time at CL=5 3.75ns 3D 10 DDR2 SDRAM Device Access Time from Clock at CL=5 0.5ns 50 11 DIMM Configuration Type Non - ECC 00 12 Refresh Rate/Type 7.8 s/self 82 13 Primary DDR2 SDRAM Width X16 10 14 Error Checking DDR2 SDRAM Device Width N/A 00 15 Reserved Undefined 00 16 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 18 DDR2 SDRAM Device Attributes: Supported 3/4/5 38 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 24 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time (tac) from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 10ns 28 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 31 Module Bank Density 256MB 40 32 Address and Command Setup Time Before Clock (tIS) 0.25ns 25 33 Address and Command Hold Time After Clock (tIH) 0.375ns 37 34 Data Input Setup Time Before Clock (tDS) 0.1ns 10 35 Data Input Hold Time After Clock (tDH) 36 Latencies < 4.1mm 01 Regular UDIMM (133/35mm) 02 Normal DIMM 00 Support weak driver 01 Minimum Clock Cycle at CL=4 3.75ns 3D Maximum Data Access Time (tac) from Clock at CL=4 0.5ns 50 5ns 50 0.225ns 22 Write Recovery Time (tWR) 15ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Memory Analysis Probe Characteristics Undefined 00 The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 60ns 3C 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) REV 1.0 06/2006 Note 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 32Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 32Mx16, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2-533 (-37B) DDR2-533 (-37B) 105ns 69 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 8ns 80 44 Max. DQS-DQ Skew Factor (tDQS) 0.3ns 1E 45 Read Data Hold Skew Factor (tQHS) 0.4ns 28 46 PLL Relock Time N/A 00 47 Tcasemax 0C 50 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 118C/W 76 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 21C 57 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 45C 2D 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 37C 25 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 31C 1F 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 36C 24 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 22C 16 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 37C 4A 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 34C 22 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 49C 31 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Reversion 63 Checksum for byte 0-62 64-255 Reserved REV 1.0 06/2006 1.2 12 Checksum data E9 Undefined -- Note 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect - Part 1 of 2 (512MB) 64Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2-533 (-37B) DDR2-533 (-37B) 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type DDR2-SDRAM 08 3 Number of Row Addresses on Assembly 14 0E 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Bank, Package, and Height 1 rank, Height=30mm 60 6 Data Width of this Assembly 7 X64 40 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 9 DDR2 SDRAM Device Cycle Time at Maximum Support Latency CL=5 3.7ns 3D 10 DDR2 SDRAM Device Access Time (tac) from Clock at CL=5 0.5ns 50 11 DIMM Configuration Type Non - ECC 00 12 Refresh Rate/Type 13 Primary DDRII SDRAM Width 14 Error Checking DDRII SDRAM Device Width 15 Reserved 16 17 18 DDR2 SDRAM Device Attributes: 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 24 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time (tac) from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 7.5ns 1E 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum Active to Precharge Time (tRAS) 45ns 2D 31 Module Bank Density 512MB 80 32 Address and Command Input Setup Time Before Clock (tIS) 0.25ns 25 33 Address and Command Input Hold Time After Clock (tIH) 0.375ns 37 34 Data Input Setup Time Before Clock (tDS) 0.1ns 10 35 Data Input Hold Time After Clock (tDH) 36 7.8 s/self 82 X8 08 N/A 00 Undefined 00 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 3/4/5 38 X <= 4.1mm 01 Regular UDIMM (133.35mm) 02 Latencies Supported Normal DIMM 00 Support weak driver 01 Minimum Clock Cycle at CL=4 3.75ns 3D Maximum Data Access Time (tac) from Clock at CL=4 0.5ns 50 5ns 50 0.225ns 22 Write Recovery Time (tWR) 15ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge Command delay (tRTP) 39 Memory Analysis Probe Characteristics 40 Extension of Byte 41 tRC and Byte 42 tRFC REV 1.0 06/2006 7.5ns 1E Undefined 00 The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 Note 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect - Part 2 of 2 (512MB) 64Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2-533 (-37B) DDR2-533 (-37B) 3C 41 Minimum Core Cycle Time (tRC) 60ns 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69 43 Maximum Clock Cycle Time (tCK max) 8ns 80 44 Max. DQS-DQ Skew Factor (tQHS) 0.3ns 1E 45 Read Data Hold Skew Factor (tQHS) 0.4ns 28 46 PLL Relock Time N/A 00 47 Tcasemax 1C 51 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 122C/W 7A 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 18C 4B 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 47C 2E 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 39C 27 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 33C 21 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 37C 25 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 23C 17 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 26C 34 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 35C 23 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 37C 25 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Revision 63 Checksum Data 64-255 Reserved REV 1.0 06/2006 1.2 12 Checksum Data F7 Undefined -- Note 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (1GB) 128Mx64 2 BANKS UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2-533 (-37B) DDR2-533 (-37B) 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 5 6 Data Width of this Assembly 7 DDR2-SDRAM 08 14 0E Number of Column Addresses on Assembly 10 0A Number of DIMM Bank, Package, and Height 2 rank, Height=30mm 61 X64 40 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 9 DDR2 SDRAM Device Cycle Time at Maximum Support Latency CL=5 3.75ns 3D 10 DDR2 SDRAM Device Access Time (tac) from Clock at CL=5 0.5ns 50 11 DIMM Configuration Type Non - ECC 00 12 Refresh Rate/Type 7.8 s/self 82 13 Primary DDRII SDRAM Width X8 08 14 Error Checking DDRII SDRAM Device Width N/A 00 15 Reserved Undefined 00 16 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 18 DDR2 SDRAM Device Attributes: 3/4/5 38 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General Support weak driver 01 23 Minimum Clock Cycle at CL=4 3.7ns 3D 24 Maximum Data Access Time (tac) from Clock at CL=4 0.5ns 50 25 Minimum Clock Cycle Time at CL=3 5ns 50 26 Maximum Data Access Time (tac) from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 7.5ns 1E 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum Active to Precharge Time (tRAS) 45ns 2D 31 Module Bank Density 512MB 80 32 Address and Command Input Setup Time Before Clock (tIS) 0.25ns 25 33 Address and Command Input Hold Time After Clock (tIH) 0.375ns 37 34 Data Input Setup Time Before Clock (tDS) 0.1ns 10 35 Data Input Hold Time After Clock (tDH) 0.225ns 22 36 Write Recovery Time (tWR) 15ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge Command delay (tRTP) 7.5ns 1E The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 Undefined 00 Latencies Supported 40 Extension of Byte 41 tRC and Byte 42 tRFC 39 Memory Analysis Probe Characteristics REV 1.0 06/2006 X < 4.1mm 01 Regular UDIMM (133.35mm) 02 Normal DIMM 00 Note 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (1GB) 128Mx64 2 BANKS UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2-533 (-37B) DDR2-533 (-37B) 3C 41 Minimum Core Cycle Time (tRC) 60ns 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69 43 Maximum Clock Cycle Time (tCK max) 8ns 80 44 Max. DQS-DQ Skew Factor (tDQs) 0.3ns 1E 45 Read Data Hold Skew Factor (tQHS) 0.4ns 28 46 PLL Relock Time N/A 00 47 Tcasemax 1C 51 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 122C/W 7A 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 18C 4B 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 47C 2E 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 39C 27 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 33C 21 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 37C 25 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 23C 17 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 26C 34 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 35C 23 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 37C 25 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Revision 63 Checksum Data 64-255 Reserved REV 1.0 06/2006 1.2 12 Checksum data F8 Undefined -- Note 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Absolute Maximum Ratings Symbol Rating Units Voltage on I/O pins relative to Vss -0.5 to 2.3 V Voltage on VDD supply relative to Vss -1.0 to +2.3 V VDDQ Voltage on VDDQ supply relative to Vss -0.5 to +2.3 V HSTG Storage Humidity (without condensation) 5 to 95 % Operating Temperature (Ambient) 0 to +70 C -55 to +100 C VIN, VOUT VDD TA TSTG Parameter Storage Temperature (Plastic) Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating temperature Conditions Symbol TCASE Note: Parameter Operating Temperature (Ambient) Rating Units Note 0 to 95 C 1 1. Case temperature is measured at top and center side of any DRAMs. DC Electrical Characteristics and Operating Conditions (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) Symbol VDD VDDQ VSS, VSSQ VREF Parameter Min Max Units Notes Supply Voltage 1.7 1.9 V 1 I/O Supply Voltage 1.7 1.9 V 1 0 0 V Supply Voltage, I/O Supply Voltage I/O Reference Voltage VTT Termination Voltage 0.49VDDQ 0.51VDDQ V 1, 2 VREF - 0.04 VREF + 0.04 V 3 Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT of transmitting device must track VREF of receiving device Input AC/DC logic level Symbol Parameter Min Max Units Notes VIH (AC) Input High (Logic1) Voltage VREF + 0.250 - V 1 VIL (AC) Input Low (Logic0) Voltage - VREF - 0.250 V 1 VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1 On Die Termination (ODT) Current Symbol Parameter IODTO Enabled ODT current per DQ ODT is HIGH; Data Bus inputs are FLOATING IODTT Active ODT current per DQ ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING REV 1.0 06/2006 Min Max Units EMRS(1) State 5 7.5 mA/DQ A6=0, A2=1 2.5 3.75 mA/DQ A6=1, A2=0 10 15 mA/DQ A6=0, A2=1 5 7.5 mA/DQ A6=1, A2=0 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) PC2-4200 (-37B) Unit I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 330 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 360 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 20 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 170 mA I DD3P Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 70 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 170 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 400 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 450 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 520 mA I DD6 Self-Refresh Current: CKE 0.2V 18 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 900 mA Symbol Note: REV 1.0 06/2006 Parameter/Condition Notes Module IDD was calculated from component IDD. It may different from the actual measurement. 16 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) PC2-4200 (-37B) Unit I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 560 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 640 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 40 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 320 mA I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 128 mA I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 40 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 336 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 720 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 760 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 1200 mA I DD6 Self-Refresh Current: CKE 0.2V 40 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1280 mA Symbol Note: REV 1.0 06/2006 Parameter/Condition Notes Module IDD was calculated from component IDD. It may different from the actual measurement. 17 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs) Symbol 06/2006 PC2-4200 (-37B) Unit I DD0 (MIN); Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 880 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 960 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 80 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 640 mA I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 256 mA I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 80 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 656 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 1040 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 1080 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 1520 mA I DD6 Self-Refresh Current: CKE 0.2V 80 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1600 mA Note: REV 1.0 Parameter/Condition Notes Module IDD was calculated from component IDD. It may different from the actual measurement. 18 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol tAC -37B Parameter Min. Unit Max. DQ output access time from CK/ -0.5 +0.5 ns DQS output access time from CK/ -0.45 +0.45 ns tCH CK high-level width 0.45 0.55 tCK tCL CK low-level width 0.45 0.55 tCK tDQSCK tCH or tCL tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tCK Clock cycle time tDH DQ and DM input hold time 0.225 ns tDS DQ and DM input setup time 0.1 ns tIPW Input pulse width 0.6 ns tDIPW DQ and DM input pulse width (each input) 0.35 ns CL=4 tHZ Data-out high-impedance time from CK/ tLZ Data-out low-impedance time from CK/ tCK 3.75 8 2 tAC (min) ns tAC (max) ns tAC (max) ns tDQSQ DQS-DQ skew (DQS & associated DQ signals) 0.3 ns tQHS Data hold Skew Factor 0.4 ns tQH tDQSS Data output hold time from DQS tHP tQHS tCK Write command to 1st DQS latching transition -0.25 DQS input low (high) pulse width (write cycle) 0.35 tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 tCK tDQSL,(H) +0.25 tMRD Mode register set command cycle time tWPST Write postamble 0.4 tWPRE Write preamble 0.35 tCK 0.375 ns tIH tIS Address and control input hold time 2 tCK tCK 0.6 tCK Address and control input setup time 0.25 tRPRE Read preamble 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 tCK tRRD Active bank A to Active bank B command 7.5 ns tIS+tCK+ tIH ns tDelay tREFI Minimum time clocks remains ON after CKE asynchronously drops Low Average Periodic Refresh Interval (85C < TCASE 95C) 7.8 s Average Periodic Refresh Interval (0C TCASE 85C) 3.9 s tOIT OCD drive mode output delay tRFC Auto-Refresh to Active/Auto-Refresh command period tCCD REV 1.0 06/2006 ns 0 12 105 to 2 ns ns tCK 19 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol -37B Parameter Min. Max. 15 Unit tWR Write recovery time WR Write recovery time with Auto-Precharge ns tWR/tCK tDAL Auto precharge write recovery + precharge time WR+tRP tCK tWTR Internal write to read command delay 7.5 tCK tRTP Internal read to precharge command delay 7.5 ns tXSNR Exit self refresh to a Non-read command tXSRD Exit self refresh to a Read command tRFC +10 ns 200 tCK Exit precharge power down to any Non- read command 2 tCK tXARD Exit active power down to read command 2 tCK tXARDS Exit active power down to read command 6-AL tCK 3 tCK tXP tCKE CKE minimum pulse width ODT tAOND ODT turn-on delay 2 2 tCK tAON ODT turn-on tAC (min) tAC (max) tCK tAONPD ODT turn-on (Power down mode) tAC (min) 2tCK + tAC +2 (max) +1 tCK tAOFD ODT turn-off delay +1 2.5 2.5 tCK ODT turn-off tAC (min) tAC (max) +0.6 ns tAOFPD ODT turn-off (Power down mode) tAC (min)+2 2.5tCK + tAC (max) +1 ns tANPD ODT to power down entry latency 3 tCK tAXPD ODT power down exit latency 8 tCK tAOF Speed Grade Definition tRAS Row Active Time 45 tRC Row Cycle Time 60 ns tRCD Active to Read or Write delay 15 ns tRP Precharge command period 15 ns REV 1.0 06/2006 70000 ns 20 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) FRONT 133.35 5.250 131.35 5.171 128.95 5.077 2.47 0 .097 Detail A 2.5 0.098 Detail B BACK 63.00 1.27 +0.10/-0 .10 0. 050 +0.004/-0. 004 55.00 2.17 2.48 Detail B 2.50 0.098 4. 00 0.157 Detail A 3. 80 0. 15 2.30 0.091 17.80 0.700 10.0 0.394 30.00 1. 180 (2X) 4.00 0.157 SIDE 5.00 0.197 0.8 +/- 0.5 Width 0.003 +/- 0.020 1.00 Pitch 0.039 1.50 +/- 0.1 0.05 +/- 0.04 Note: All dimensions are typical with tolerances of+/- 0.15 (0.006) unless otherwise stated. Units: Millimeters(Inches) * Device position is only for reference. REV 1.0 06/2006 21 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) FRONT 133.35 5.250 131.35 5.171 128.95 5.077 2.47 0.097 Detail A 2.5 0.098 Detail B BACK 63.00 Detail B 2.50 0.098 4. 00 0.157 3. 80 0. 15 1.27 +0. 10/-0 .10 0. 050 +0. 004/-0. 004 55.00 2.17 2.48 Detail A 2.30 0.091 17.80 0.700 10.0 0. 394 30.00 1. 180 (2X) 4.00 0.157 SIDE 5.00 0.197 0 .8 +/- 0.5 Width 0 .003 +/- 0.020 1.00 Pitch 0.039 1 .50 +/- 0.1 0 .05 +/- 0.04 Note: All dimensions are typical with tolerances of+/- 0.15 (0.006) unless otherwise stated. Units: Millimeters(Inches) * Device position is only for reference. REV 1.0 06/2006 22 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs) FRONT 133.35 5.250 131.35 5.171 128.95 5.077 4.00 0.157 Detail A 2.5 0.098 63.00 1.27 +0.10/-0.10 0.050 +0.004/-0.004 55.00 2.17 2.48 Detail B 2.50 0.098 4. 00 0.157 Detail A 3. 80 0. 15 Detail B BACK 2. 30 0.091 17.80 0.700 10.0 0. 394 30.00 1. 180 (2X) 4.00 0.157 SIDE 5.00 0.197 0.8 +/- 0.5 Width 0.003 +/- 0.020 1.00 Pitch 0.039 1.50 +/- 0.1 0.05 +/- 0.04 Note: All dimensions are typical with tolerances of+/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches) * Device position is only for reference. REV 1.0 06/2006 23 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1GB: 128M x 64 / 512MB: 64M x 64 / 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Revision Log Rev Date 1.0 08/2006 REV 1.0 06/2006 Modification Preliminary Release 24 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.