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MX29L1611G
16M-BIT [2M x 8/1M x 16] CMOS
SINGLE VOLTAGE FLASH EEPROM
ADVANCED INFORMATION
• Status Register feature for detection of program or
erase cycle completion
• Low VCC write inhibit is equal to or less than 1.8V
• Software data protection
• Page program operation
- Internal address and data latches for 64 words per
page
- Page programming time: 5ms typical
• Low power dissipation
- 50mA active current
- 20uA standby current
• Two independently Protected sectors
• Package type
- 42 pin plastic DIP
GENERAL DESCRIPTION
The MX29L1611G is a 16-mega bit Flash memory orga-
nized as either 1M wordx16 or 2M bytex8. The
MX29L1611G includes 32 sectors of 64KB(65,536 Bytes
or 32,768 words). MXIC's Flash memories offer the most
cost-effective and reliable read/write non-volatile random
access memory. The MX29L1611G is packaged in 42
pin PDIP.
The standard MX29L1611G offers access times as fast
as 100ns, allowing operation of high-speed microproces-
sors without wait. To eliminate bus contention, the
MX29L1611G has separate chip enable CE and, output
enable (OE).
MXIC's Flash memories augment EPROM functionality
with electrical erasure and programming. The
MX29L1611G uses a command register to manage this
functionality.
MX29L1611G does require high input voltages for pro-
gramming. Commands require 11V input to determine
the operation of the device. Reading data out of the
device is similar to reading from an EPROM.
MXIC Flash technology reliably stores memory contents
even after 100 cycles. The MXIC's cell is designed to
optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide pro-
cessing and low internal electric fields for erase and pro-
gramming operations produces reliable cycling. The
MX29L1611G uses a 11V Vpp supply to perform the
Auto Erase and Auto Program algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC +1V.
FEATURES
• 3.3V ± 10% for write and read operation
• 11V Vpp erase/programming operation
• Endurance: 100 cycles
• Fast random access time: 90ns/100ns/120ns
• Fast page access time: 30ns
• Sector erase architecture
- 32 equal sectors of 64k bytes each
- Sector erase time: 200ms typical
• Auto Erase and Auto Program Algorithms
- Automatically erases any one of the sectors or the
whole chip
- Automatically programs and verifies data at specified
addresses
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MX29L1611G
PIN CONFIGURATIONS
42 PDIP
PIN DESCRIPTION
SYMBOL PIN NAME
A0 - A19 Address Input
Q0 - Q14 Data Input/Output
Q15/A-1 Q15(Word mode)/LSB addr.(Byte
mode, for read mode only)
CE Chip Enable Input
OE Output Enable Input
BYTE/VPP Word/Byte Selection Input, Erase/Pro-
gram supply voltage
VCC P ower Supply
GND Ground Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE/VPP
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
MX29L1611G
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MX29L1611G
BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH V OLTAGE
WRITE
STATE
MACHINE
(WSM)
COMMAND
INTERFACE
REGISTER
(CIR)
MX29L1611G
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Y-select
Q0-Q15/A-1
Q15/A-1
A0-A19
CE
OE
BYTE / VPP
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MX29L1611G
Table1. PIN DESCRIPTIONS
SYMBOL TYPE NAME AND FUNCTION
A0 - A19 INPUT ADDRESS INPUTS: for memory addresses. Addresses are internally latched
during a write cycle.
Q0 - Q7 INPUT/OUTPUT LOW-BYTE DATA BUS: Input data and commands during Command Inter-
f ace Register (CIR) write cycles. Outputs arr a y, status and identifier data in
the appropriate read mode. Floated when the chip is de-selected or the out-
puts are disabled.
Q8 - Q14 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations. Out-
puts array, identifier data in the appropriate read mode; not used f or status
register reads. Floated when the chip is de-selected or the outputs are dis-
abled
Q15/A -1 INPUT/OUTPUT Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB
ADDRESS(BYTE = LOW) for read operation.
CE INPUT CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,
decoders and sense amplifiers. With CE high, the de vice is deselected and
power consumption reduces to Standby level upon completion of any current
program or erase operations. CE must be low to select the device.
OE INPUT OUTPUT ENABLES: Gates the device's data through the output buffers dur-
ing a read cycle OE is active low.
BYTE/VPP INPUT BYTE ENABLE: While operating read mode , BYTE Low places de vice in x8
mode. All data is then input or output on Q0-7 and Q8-14 float. Address Q15/
A-1 selects between the high and low byte. While operating read mode, BYTE
high places the device in x16 mode, and turns off the Q15/A-1 input buffer.
Address A0, then becomes the lowest order address.
ERASE/PROGRAM ENABLE:When BYTE/VPP=11V would place this de-
vice into ERASE/PROGRAM mode.
V CC DEVICE POWER SUPPLY(3.3V ± 10%)
GND GROUND
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MX29L1611G
Table 2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)
Mode Notes CE OE BYTE/VPP A0 A1 A9 Q0-Q7 Q8-Q14 Q15/A-1
Read 1 VIL VIL VIL X X X DOUT HighZ VIL/VIH
Output Disable 1 VIL VIH VIL X X X High Z High Z X
Standby 1 VIH X H/L X X X High Z HIgh Z X
Manufacturer ID 2,4 VIL VIL VIL VIL VIL VID C 2H High Z VIL
Device ID 2, 4 VIL VIL VIL VIH VIL VID F 6 H High Z VIL
Write 1,3,5 VIL VIH VPP X X X DIN DIN DIN
Table 2.1 Bus Operations for Word-Wide Mode (BYTE/VPP = VIH)
Mode Notes CE OE BYTE/VPP A0 A1 A9 Q0-Q7 Q8-Q14 Q15/A-1
Read 1 VIL VIL VIH X X X DOUT DOUT DOUT
Output Disable 1 VIL VIH VIH X X X High Z High Z HighZ
Standby 1 VIH X H/L X X X High Z HIgh Z HighZ
Manufacturer ID 2,4 VIL VIL VIH VIL VIL VID C 2H 00H 0B
Device ID 2, 4 VIL VIL VIH VIH VIL VID F 6H 0 0 H 0B
Write 1,3,5 VIL VIH VPP X X X DIN DIN DIN
BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
NO TES :
1. X can be VIH or VIL for address or control pins.
2. A0 and A1 at VIL provide manuf acturer ID codes . A0 at VIH and A1 at VIL pro vide device ID codes. A0 at VIL,
A1 at VIH and with appropriate sector addresses provide Sector Protect Code. (Refer to Table 4),A2~A19=Do not
care.
3. Commands for different Erase operations, Data program operations or Sector Protect operations can only be
successfully completed through proper command sequence.
4. VID = 11.5V- 12.5V
5. Word mode only for write operation VPP=10.5V~11.5V
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MX29L1611G
TABLE 3. COMMAND DEFINITIONS (BYTE/VPP=VHH)
WRITE OPERATIONS
Commands are written to the COMMAND INTERF ACE
REGISTER (CIR) using standard microprocessor write
timings. The CIR ser ves as the interface between the
microprocessor and the internal chip operation. The CIR
can decipher Read Array, Read Silicon ID, Erase and
Program command. In the event of a read command,
the CIR simply points the read path at either the array or
the silicon ID , depending on the specific read command
given. For a program or erase cycle, the CIR informs
the write state machine that a program or erase has been
requested. During a program cycle, the write state ma-
chine will control the program sequences and the CIR
will only respond to status reads. During a sector/chip
erase cycle, the CIR will respond to status reads. After
the write state machine has completed its task, it will
allow the CIR to respond to its full command set. The
CIR stays at read status register mode until the micro-
processor issues another valid command sequence.
Device operations are selected by writing commands
into the CIR. Table 3 belo w defines 16 Mbit flash family
command.
Command Read/ Silicon Page Chip Sector Read Clear
Sequence Reset ID Read Program Erase Erase Status Reg. Status Reg.
Bus Write 4 4 4 6 6 4 3
Cycles Req'd
First Bus Addr 5555H 5555H 5555H 5555H 5555H 5555H 5555H
Write Cycle Data AAH AAH AAH AAH AAH AAH AAH
Second Bus Addr 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH
Write Cycle Data 55H 55H 55H 55H 55H 55H 55H
Third Bus Addr 5555H 5555H 5555H 5555H 5555H 5555H 5555H
Write Cycle Data F0H 90H A0H 80H 80H 70H 50H
Fourth Bus Addr RA 00H/01H PA 5555H 5555H X
Read/Write Cycle Data RD C2H/F6H PD AAH AAH SRD
Fifth Bus Addr 2AAAH 2AAAH
Write Cycle Data 55H 55H
Sixth Bus Addr 5555H SA
Write Cycle Data 10H 30H
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MX29L1611G
Notes:
1. Address bit A15 -- A19 = X = Don't care f or all address commands e xcept f or Prog ram Address(PA) and Sector
Address(SA).
5555H and 2AAAH address command codes stand f or He x number starting from A0 to A14.
2 . Bus operations are defined in Table 2.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be progr ammed. Addresses are latched on the f alling edge of the CE
pulse.
SA = Address of the sector to be erased. The combination of A15 -- A19 will uniquely select an y sector.
4 . RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of CE.
SRD = Data read from status register .
5. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care.
* Ref er to Table 4, Figure 11.
** Only the top and the bottom sectors have protect- bit feature. SA = (A19,A18,A17,A16,A15) = 00000B or
11111B is valid.
TABLE 3. COMMAND DEFINITIONS
Command Sector Sector V erify Sector Abort
Sequence Protection Unprotect Protect
Bus Write 6 6 4 3
Cycles Req'd
First Bus Addr 5555H 5555H 5555H 5555H
Write Cycle Data AAH AAH AAH AAH
Second Bus Addr 2AAAH 2AAAH 2AAAH 2AAAH
Write Cycle Data 55H 55H 55H 55H
Third Bus Addr 5555H 5555H 5555H 5555H
Write Cycle Data 60H 60H 90H E0H
Fourth Bus Addr 5555H 5555H SA**
Read/Write Cycle Data AAH AAH C2H*
Fifth Bus Addr 2AAAH 2AAAH
Write Cycle Data 55H 55H
Sixth Bus Addr SA** SA**
Write Cycle Data 20H 40H
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MX29L1611G
Table 4. MX29L1611G Silicon ID Codes and Verify Sector Protect Code
Type A19 A18 A17 A16 A15 A1A0Code(HEX) Q7Q6Q5Q4Q3Q2Q1Q0
Manufacturer Code XXXXXVILVILC2H* 11000010
Device Code XXXXXVILVIHF6H* 11110110
Verify Sector Protect Sector Address*** VI H VIL C2H** 11000010
* MX29L1611G Manuf acturer Code = C2H, Device Code = F6H when BYTE/VPP = VIL
MX29L1611G Manufacturer Code = 00C2H, Device Code = 00F6H when BYTE/VPP = VIH
** Outputs C2H at protected sector address, 00H at unprotected sector address.
*** Only the top and the bottom sectors have protect-bit feature. Sector address = (A19, A18,A17,A16,A15) =
00000B or 11111B
DEVICE OPERATION
SILICON ID READ
The Silicon ID Read mode allows the reading out of a
binary code from the device and will identify its manu-
facturer and type. This mode is intended for use by pro-
gramming equipment for the purpose of automatically
matching the device to be programmed with its corre-
sponding programming algorithm. This mode is func-
tional over the entire temperature range of the device.
To activate this mode, the programming equipment must
force VID (11.5V~12.5V) on address pin A9. T wo identi-
fier bytes may then be sequenced from the device out-
puts by toggling address A0 from VIL to VIH. All ad-
dresses are don't cares except A0 and A1.
The manufacturer and device codes may also be read
via the command register, for instances when the
MX29L1611G is erased or programmed in a system with-
out access to high voltage on the A9 pin. The command
sequence is illustrated in Table 3.
Byte 0 (A0=VIL) represents the manufacturer's code
(MXIC=C2H) and byte 1 (A0=VIH) the device identifier
code (MX29L1611G=F6H).
To ter minate the operation, it is necessar y to write the
read/reset command sequence into the CIR.
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MX29L1611G
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command regis-
ter . Microprocessor read cycles retrieve array data from
the memory. The device remains enabled for reads until
the CIR contents are altered by a valid command se-
quence.
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not re-
quired for "read operation". Standard microprocessor
read cycles will retrieve array data. This default value
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. Refer to the AC
Read Characteristics and Waveforms for the specific tim-
ing parameters.
The MX29L1611G is accessed like an EPR OM. When
CE and OE are low the data stored at the memory loca-
tion determined by the address pins is asserted on the
outputs. The outputs are put in the high impedance state
whenev er CE or OE is high. This dual line control gives
designers flexibility in preventing bus contention.
Note that the read/reset command is not valid when pro-
gram or erase is in progress.
PAGE READ
The MX29L1611G offers "fast page mode read" func-
tion. The users can take the access time advantage if
keeping
CE, OE at low and the same page address (A3~A19
unchanged). Please refer to Figure 5-2 for detailed tim-
ing waveform. The system performance could be en-
hanced by initiating 1 normal read and 7 fast page
reads(for word mode A0~A2) or 15 fast page reads(for
byte mode altering A-1~A2).
PAGE PROGRAM
The device is set up in the programming mode when
VPP=11V is applied OE=VIH.
To initiate Page program mode, a three-cycle command
sequence is required. There are two "unlock" write cycles.
These are followed by writing the page program com-
mand-A0H.
Any attempt to write to the device without the three-
cycle command sequence will not start the internal Write
State Machine (WSM), no data will be written to the de-
vice.
After three-cycle command sequence is given, a
byte(word) load is performed by applying a low pulse on
the CE input with CE low and OE high. The address is
latched on the falling edge of CE. The data is latched by
the first rising edge of CE. Maximum of 64 words of
data may be loaded into each page by the same proce-
dure as outlined in the page program section below .
PROGRAM
Any page to be programmed should have the page in
the erased state first, i.e. performing sector erase is
suggested before page programming can be performed.
The device is programmed on a page basis. If a word of
data within a page is to be changed, data for the entire
page can be loaded into the device. Any word that is not
loaded during the programming of its page will be still in
the erased state (i.e. FFH). Once the words of a page
are loaded into the device, they are simultaneously pro-
grammed during the internal programming period. After
the first data word has been loaded into the device, suc-
cessive words are entered in the same manner. Each
new word to be programmed must have its high to low
transition on CE within 30us of the low to high transition
of CE of the preceding word. A6 to A19 specify the
page address, i.e., the device is page-aligned on 64 words
boundary. The page address must be valid during each
high to low transition of CE. A0 to A5 specify the word
address within the page. The word may be loaded in any
order; sequential loading is not required. If a high to low
transition of CE is not detected within 100us of the last
low to high transition, the load period will end and the
internal programming period will start. The Auto page
program terminates when status on Q7 is '1' at which
time the device stays at read status register mode until
the CIR contents are altered by a valid command se-
quence. (Refer to table 3,6 and Figure 1,7,8)
CHIP ERASE
The device is set up in the er ase mode when VPP=11V
is applied OE=VIH.
Chip erase is a six-bus cycle oper ation. There are two
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MX29L1611G
SECTOR ERASE
Sector erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed b y writing the
set-up command-80H. Two more "unloc k" write cycles
are then followed by the sector erase command-30H.
The sector address is latched on the falling edge of CE,
while the command (data) is latched on the rising edge
of CE.
Sector erase does not require the user to program the
device prior to erase. The system is not required to
provide any controls or timings during these operations.
The automatic sector erase begins on the rising edge of
the last CE pulse in the command sequence and termi-
nates when the status on Q7 is "1" at which time the
device stays at read status register mode. The device
remains enabled for read status register mode until the
CIR contents are altered by a valid command
sequence.(Refer to table 3,6 and Figure 3,4,6,8)
A19 A18 A17 A 16 A15 Address Range
[A19, -1]
SA0 0 0 0 0 0 000000H--00FFFFH
SA1 0 0 0 0 1 010000H--01FFFFH
SA2 0 0 0 1 0 020000H--02FFFFH
SA3 0 0 0 1 1 030000H--03FFFFH
SA4 0 0 1 0 0 040000H--04FFFFH
... ... ... ... ... ................................
SA31 1 1 1 1 1 1F0000H--1FFFFFH
Table 5. MX29L1611G Sector Address Table
(Byte-Wide Mode)
READ STATUS REGISTER
The MXIC's 16 Mbit flash family contains a status reg-
ister which may be read to determine when a program or
erase operation is complete, and whether that operation
completed successfully. The status register may be read
at any time by writing the Read Status command to the
CIR. After writing this command, all subsequent read
operations output data from the status register until an-
other valid command sequence is written to the CIR. A
Read Array command must be written to the CIR to re-
turn to the Read Array mode.
The status register bits are output on Q3 - Q7 (table 6)
whether the device is in the byte-wide (x8) or word-wide
(x16) mode for the MX29L1611G. In the word-wide mode
the upper byte, Q(8:15) is set to 00H during a Read Sta-
tus command. In the byte-wide mode, Q(8:14) are tri-
stated and Q15/A-1 retains the low order address func-
tion.
It should be noted that the contents of the status regis-
ter are latched on the falling edge of OE or CE which-
ever occurs last in the read cycle. This prevents pos-
sible bus errors which might occur if the contents of the
status register change while reading the status register .
CE or OE must be toggled with each subsequent status
read, or the completion of a program or erase operation
will not be evident.
The Status Register is the interface between the micro-
processor and the Write State Machine (WSM). When
the WSM is active, this register will indicate the status
of the WSM, and will also hold the bits indicating whether
or not the WSM was successful in perfor ming the de-
sired operation. The WSM sets status bits f our through
seven and clears bits six and seven, but cannot clear
status bits four and five. If Erase fail or Program fail
status bit is detected, the Status Register is not cleared
until the Clear Status Register command is written. The
MX29L1611G automatically outputs Status Register data
when read after Chip Erase, Sector Erase, Page Pro-
gram or Read Status Command write cycle. The default
state of the Status Register after power-up and return
from deep power-down mode is (Q7, Q6, Q5, Q4) =
1000B. Q3 = 0 or 1 depends on sector-protect status,
can not be changed by Clear Status Register Command
or Write State Machine.
"unlock" write cycles. These are follo wed b y writing the
"set-up" command-80H. Two more "unlock" write cycles
are then followed by the chip erase command-10H.
Chip erase does not require the user to program the de-
vice prior to erase.
The automatic erase begins on the rising edge of the
last CE pulse in the command sequence and terminates
when the status on Q7 is "1" at which time the device
sta ys at read status register mode. The device remains
enabled for read status register mode until the CIR con-
tents are altered by a valid command sequence. (Refer
to table 3,6 and Figure 2,6,8)
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MX29L1611G
CLEAR STATUS REGISTER
The Erase fail status bit (Q5) and Program fail status bit
(Q4) are set by the write state machine, and can only
be reset by the system software. These bits can indi-
cate various f ailure conditions (see Table 6). By allow-
ing the system software to control the resetting of these
bits, several operations may be performed (such as cu-
mulatively programming several pages or erasing mul-
tiple blocks in sequence). The status register may then
be read to determine if an error occurred during that pro-
gramming or erasure series. This adds fle xibility to the
way the device may be programmed or erased. Addi-
tionally, once the program(erase) fail bit happens, the
program (erase) operation can not be performed further.
The program(erase) fail bit must be reset by system
software before fur ther page program or sector (chip)
erase are attempted. To clear the status register, the
Clear Status Register command is written to the CIR.
Then, any other command may be issued to the CIR.
Note again that before a read cycle can be initiated, a
Read command must be written to the CIR to specify
whether the read data is to come from the Array, Status
Register or Silicon ID .
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TABLE 6. MX29L1611G STATUS REGISTER
STATUS NOTES Q7 Q6 Q5 Q4 Q3
IN PROGRESS PROGRAM 1,2,5 0 0 0 0 0/1
ERASE 1,3,5 0 0 0 0 0/1
COMPLETE PROGRAM 1,2,5 1 0 0 0 0/1
ERASE 1,3,5 1 0 0 0 0/1
FAIL PROGRAM 1,4,5 1 0 0 1 0/1
ERASE 1,4,5 1 0 1 0 0/1
AFTER CLEARING ST A TUS REGISTER 5 1 0 0 0 0/1
NOTES:
1. Q7 : WRITE STATE MA CHINE STATUS
1 = READY, 0 = BUSY
Q5 : ERASE FAIL STATUS
1 = FAIL IN ERASE, 0 = SUCCESSFUL ERASE
Q4 : PROGRAM FAIL STATUS
1 = FAIL IN PROGRAM, 0 = SUCCESSFUL PROGRAM
Q3 : SECT OR-PRO TECT STATUS
1 = SECT OR 0 OR/AND 15 PR O TECTED
0 = NONE OF SECT OR PRO TECTED
Q6,Q2 - 0 = RESER VED FOR FUTURE ENHANCEMENTS .
These bits are reserv ed for future use ; mask them out when polling the Status Register.
2. PROGRAM STATUS is f or the status during P age Programming or Sector Unprotect mode .
3. ERASE STATUS is f or the status during Sector/Chip Erase or Sector Protection mode .
4. F AIL STATUS bit(Q4 or Q5) is provided during P age Program or Sector/Chip Erase modes respectively.
5. Q3 = 0 or 1 depends on Sector-Protect Status.
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MX29L1611G
The device remains enabled for read status register mode
until the CIR contents are altered by a valid command
sequence.
ABORT MODE
To activate Abort mode, a three-bus cycle operation is
required. The E0H command (Refer to table 3) only stops
Page program or Sector /Chip erase operation currently
in progress and puts the device in Abort mode. So the
program or erase operation will not be completed. Since
the data in some page/sectors is no longer valid due to
an incomplete program or erase operation, the program
fail (Q4) or erase fail (Q5) bit will be set.
A read array command MUST be written to bring the
de vice out of the abort state without incurring an y wake
up latency. Note that once device is brought out, Clear
status register mode is required before a program or erase
operation can be executed.
SECTOR PROTECTION
To activate this mode, a six-bus cycle operation and
VPP=11V are required. There are two 'unlock' write
cycles. These are follow ed b y writing the 'set-up' com-
mand. Two more 'unlock' write cycles are then f ollowed
by the Lock Sector command - 20H. Sector address is
latched on the falling edge of CE of the sixth cycle of
the command sequence. The automatic Lock operation
begins on the rising edge of the last CE pulse in the
command sequence and terminates when the Status on
Q7 is '1' at which time the device stays at the read sta-
tus register mode.
The device remains enabled for read status register mode
until the CIR contents are altered by a valid command
sequence (Refer to table 3,6 and Figure 9,11).
VERIFY SECTOR PROTECT
To verify the Protect status of the Top and the Bottom
sector, operation is initiated by writing Silicon ID read
command into the command register. Following the
command write, a read cycle from address XX00H re-
trieves the Manufacturer code of C2H. A read cycle
from XX01H returns the Device code F8H. A read cycle
from appropriate address returns information as to which
sectors are protected. To terminate the operation, it is
necessary to write the read/reset command sequence
into the CIR.
(Refer to table 3,4 and Figure 11)
A few retries are required if Protect status can not be
verified successfully after each operation.
SECTOR UNPROTECT
It is also possible to unprotect the sector , same as the
first five write command cycles in activating sector pro-
tection mode followed by the Unprotect Sector com-
mand -40H, the automatic Unprotect operation begins
on the rising edge of the last CE pulse in the command
sequence and terminates when the Status on DQ7 is '1'
at which time the device stays at the read status regis-
ter mode.
(Refer to table 3,6 and Figure 10,11)
DATA PROTECTION
The MX29L1611G is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tions. During power up the device automatically resets
the internal state machine in the Read Array mode. Also,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent
inadvertent write cycles resulting from VCC power-up and
power-down transitions or system noise.
14
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
LOW VCC WRITE INHIBIT
To avoid initiation of a write cycle during VCC power-up
and power-down, a write cycle is locked out for VCC
less than VLKO(typically 1.8V). If VCC < VLKO, the
command register is disabled and all internal program/
erase circuits are disabled. Under this condition the
device will reset to the read mode. Subsequent writes
will be ignored until the VCC level is greater than VLKO.
It is the user's responsibility to ensure that the control
pins are logically correct to prevent unintentional write
when VCC is above VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 10ns (typical) on CE will not
initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE
= VIH. To initiate a write cycle, CE must be a logical
zero while OE is a logical one, and VPP=11V should be
applied.
15
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
Figure 1. AUTOMATIC PAGE PROGRAM FLOW CHART
START
Write Data A0H Address 5555H
NO
Write Data 55H Address 2AAAH
Write Data AAH Address 5555H
BYTE/VPP=VHH
Loading End?
Page Program Completed
YES
YES
NO
SR7 = 1
?
Wait 100us
Read Status Register
Write Program Data/Address
SR4 = 0
?
Program Error
YES
NO
YES To Continue Other Operations,
Do Clear S.R. Mode First
Program
another page?
Operation Done, Device Stays At Read S.R. Mode
Note : S.R. Stands for Status Register
NO
BYTE/VPP=VIH/VIL
16
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
Figure 2. AUTOMATIC CHIP ERASE FLOW CHART
START
Write Data 80H Address 5555H
NO
Write Data 55H Address 2AAAH
BYTE/VPP=VHH
Chip Erase Completed
YES
YES
NO
SR7 = 1
?
Write Data AAH Address 5555H
Read Status Register
SR5 = 0
?
Erase Error
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 10H Address 5555H
BYTE/VPP=VIH/VIL
Operation Done,
Device Stays at
Read S.R. Mode
To Continue Other
Operations, Do Clear
S.R. Mode First
17
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
Figure 3. AUTOMATIC SECTOR ERASE FLOW CHART
START
Write Data 80H Address 5555H
NO
Write Data 55H Address 2AAAH
BYTE/VPP=VHH
Sector Erase Completed
YES
YES
NO
SR7 = 1
?
Write Data AAH Address 5555H
Read Status Register
SR5 = 0
?
Erase Error
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
BYTE/VPP=VIH/VIL
Write Data 30H Sector Address
Operation Done,
Device Stays at
Read S.R. Mode
To Continue Other
Operations, Do Clear
S.R. Mode First
18
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING VALUE
Ambient Operating Temperature 0°C to 70°C
Storage T emperature -65°C to 125°C
Applied Input Voltage -0.5V to Vcc+0.5V
Applied Output Voltage -0.5V to Vcc+0.6V
VCC to Ground P otential -0.5V to 4.0V
A9 -0.5V to 12.5V
BYTE/VPP -0.5V to 11.5V
NOTICE:
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to
the de vice. This is stress rating only and functional op-
erational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
e xtended period may aff ect reliability.
NOTICE:
Specifications contained within the following tables are
subject to change.
CAPACITANCE TA = 25°°
°°
°C, f = 1.0 MHz
SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITIONS
CIN Input Capacitance 14 pF VIN = 0V
COUT Output Capacitance 16 pF V OUT = 0V
SWITCHING TEST CIRCUITS
SWITCHING TEST WAVEFORMS
2.0V
0.8V
2.4V
0.45V
TEST POINTS
INPUT
1.5V
OUTPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are < 5ns.
DEVICE
UNDER
TEST
DIODES = IN3064
OR EQUIVALENT
CL = 35 pF Including jig capacitance
6.2K
2.7K 3.3V
CL ohm
ohm
19
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
DC CHARACTERISTICS VCC = 3.3V ± ±
± ±
± 10%
SYMBOL PARAMETER NOTES MIN. TYP. MAX. UNITS TEST CONDITIONS
IIL Input Load 1 ±1 uA VCC=VCC Max
Current VIN=VCC or GND
ILO Output Leakage 1 ±10 uA VCC=VCC Max
Current VIN=VCC or GND
ISB1 VCC Standby 1 2 0 50 uA VCC=VCC Max
Current(CMOS) CE=VCC ± 0.2V
ISB2 VCC Standby 1 2 mA VCC=VCC Max
Current(TTL) CE=VIH
ICC1 VCC Read 1 50 80 mA VCC=VCC Max
Current f=10MHz, IOUT = 0 mA
ICC2 VCC Program 1 1 5 3 0 mA Program in Progress
Current
ICC3 VCC Erase Current 1 1 5 3 0 mA Erase in Progress
VIL Input Low V oltage 2 -0.3 0.6 V
VIH Input High V oltage 3 0.7xVCC VCC+0.3 V
V OL Output Low V oltage 0.45 V IOL=2.1mA, Vcc =Vcc Min
VOH Output High Voltage 2.4 V IOH=-100uA, Vcc=Vcc Min
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, T = 25°C . These currents are valid
for all product versions (package and speeds).
2. VIL min. = -1.0V for pulse width is equal to or less than 50ns.
VIL min. = -2.0V for pulse width is equal to or less than 20ns.
3. VIH max. = VCC + 1.5V f or pulse width is equal to or less than 20ns. If VIH is o ver the specified maxim um value,
read operation cannot be guaranteed.
20
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
AC CHARACTERISTICS -- READ OPERATIONS
29L1611G-90 29L1611G-10 29L1611G-12
SYMBOL DESCRIPTIONS MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS
tACC Address to Output Delay 9 0 1 0 0 1 2 0 ns CE=OE=VIL
tPA P age Mode Access Time 3 0 30 3 0 ns CE=OE=VIL
tCE CE to Output Delay 9 0 1 0 0 1 2 0 ns OE=VIL
tOE OE to Output Delay 3 0 30 30 ns CE=VIL
tD F OE High to Output Delay 0 2 0 0 2 0 0 2 0 ns CE=VIL
tO H Address to Output hold 0 0 0 ns CE=OE=VIL
tBACC BYTE to Output Delay 1 00 1 00 120 ns CE= OE=VIL
tBHZ BYTE Low to Output in High Z 20 20 20 ns CE=VIL
TEST CONDITIONS:
• Input pulse levels: 0.45V/2.4V
• Input rise and fall times: 5ns
• Output load: 1TTL gate + 35pF(Including scope and jig)
• Reference levels for measuring timing: 1.5V
NOTE:
1. tDF is defined as the time at which the output achieves
the open circuit condition and data is no longer driven.
21
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
Figure 4.1 NORMAL READ TIMING WAVEFORMS
ADDRESSES
tACC
tCE
tDF
tOH
tOE
ADDRESSES STABLE
Data out valid
Vcc
3.3V
GND
DATA OUT
CE
OE
Power-up Standby Device and
address selection Outputs Enabled Data valid Standby Power-down
Vcc
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
HIGH Z HIGH Z
VCC
1. For real world application, BYTE/VPP pin should be either static high(word mode) or static low(byte mode);
dynamic switching of BYTE/VPP pin is not recommended.
NOTE:
Figure 4.2 PAGE READ TIMING WAVEFORMS
VALID ADDRESS
A3-A19
(A-1), A0~A2
CE
OE
DATA OUT
tACC
tPA tPA tPA
tOE tOH tDF
22
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
Figure 5. BYTE TIMING WAVEFORMS
ADDRESSES
tACC
tCE
tDF
tOH
Data Output
tOE
ADDRESSES STABLE
DATA(Q0-Q7)
CE
OE
BYTE/VPP
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
HIGH Z HIGH Z
Data Output
Data Output
HIGH Z
tBACC
HIGH Z
tBHZ
DATA(Q8-Q15)
23
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
AC CHARACTERISTICS -- WRITE/ERASE/PROGRAM OPERATIONS
29L1611G-90 29L1611G-10 29L1611G-12
SYMBOL DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNIT
tWC Write Cycle Time 9 0 1 00 120 ns
tAS Address Setup Time 0 0 0 ns
tAH Address Hold Time 6 0 6 0 6 0 ns
tDS Data Setup Time 5 0 5 0 50 ns
tDH Data Hold Time 1 0 10 1 0 ns
tCES CE Setup Time 0 0 0 ns
tGHWL Read Recover Time Before Write 0 0 0
tWP Write Pulse Width 6 0 6 0 6 0 ns
tWPH Write Pulse Width High 4 0 4 0 4 0 ns
tBALC Byte(Word) Address Load Cycle 0.3 30 0.3 3 0 0.3 3 0 us
tBAL Byte(Word) Address Load Time 100 100 1 00 us
tSRA Status Register Access Time 120 12 0 1 20 ns
tCESR CE Setup before S.R. Read 100 100 1 00 ns
tVCS VCC Setup Time 2 2 2 us
tRA W Read Operation Set Up Time After Write 2 0 2 0 2 0 ns
tVPS VPP Setup Time 2 2 2 us
tVPH VPP Hold Time 2 2 2 us
24
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
Figure 6. COMMAND WRITE TIMING WAVEFORMS
tAS
tDS
tAH
DIN
tDH
tGHWL
VALID
ADDRESSES
OE
DATA
HIGH Z
CE
VCC
BYTE/VPP
tWPH
tWP
tWC
tVCS
11V
1. BYTE/VPP pin should be static at 11V is equal to or less than during write operation.
NOTE:
2. BYTE/VPP pin should be static at TTL or CMOS level during Read operation.
25
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
Figure 7. AUTOMATIC PAGE PROGRAM TIMING WAVEFORMS
tAS
tDS
tAH
tDH
tBALC
A15~A19
CE
OE
DATA
tVPS
tWPH
tWP
11V
tWC
BYTE/VPP
AAH 55H A0H SRD
55H
55H
AAH
2AH
55H
55H
Word offset
Address
Page Address
Page Address
A6~A14
A0~A5
tBAL
tCES
tRAW
tSRA
tVPH
Write
Data
Last Word
offset Address
Last Write
Data
26
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
Figure 8. AUTOMATIC SECTOR/CHIP ERASE TIMING WAVEFORMS
tAS
tDS
tAH
tDH
A15~A19
CE
OE
DATA
tWPH
tWP
AAH 55H 80H SRD
5555H 2AAAH 5555H
SA/*
tWC
A0~A14
tCESR
tCES
tSRA
NOTES:
5555H 2AAAH */5555H
AAH 55H 30H
1."*" means "don't care" in this diagram.
2."SA" means "Sector Adddress".
11V
BYTE/VPP
tRAW
27
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
Figure 9. SECTOR PROTECTION ALGORITHM
START,
PLSCNT=0
Write Data 60H Address 5555H
NO
Write Data 55H Address 2AAAH
BYTE/VPP=VHH
Increment PLSCNT,
To Protect Sector Again
YES
YES
NO
SR7 = 1
?
Write Data AAH Address 5555H
Read Status Register
To
Verify Protect
Status ? Data
= C2H ?
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 20H, Sector Address*
BYTE/VPP=VIH/VIL
Verify Protect Status Flow
(Figure 11)
Device Failed
YES
NO
Protect Sector
Operation Terminated
Sector Protected,Operation
Done, Device Stays at
Verify Sector Protect Mode
Device Stays at
Read S.R. Mode
YES
PLSCNT
= 25 ?
NO
NOTE :
*Only the Top or the Bottom Sector Address is vaild in this feature.
i.e. Sector Address = (A19,A18,A17,A16,A15) = 00000B or 11111B
28
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
Figure 10. SECTOR UNPROTECT ALGORITHM
START,
PLSCNT=0
Write Data 60H Address 5555H
NO
Write Data 55H Address 2AAAH
BYTE/VPP=VHH
Increment PLSCNT,
To Unprotect Sector Again
YES
YES
NO
SR7 = 1
?
Write Data AAH Address 5555H
Read Status Register
To
Verify Protect
Status ? Data
= 00H ?
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
BYTE/VPP=VIH/VIL
Write Data 40H, Sector Address*
Verify Protect Status Flow
(Figure 11)
Device Failed
YES
NO
Unprotect Sector
Operation Terminated
Sector Unprotected,Operation
Done, Device Stays at
Verify Sector Protect Mode
Device Stays at
Read S.R. Mode
YES
PLSCNT
= 25 ?
NO
NOTE :
*Only the Top or the Bottom Sector Address is vaild in this feature.
i.e. Sector Address = (A19,A18,A17,A16,A15) = 00000B or 11111B
29
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
Figure 11. VERIFY SECTOR PROTECT FLOW CHART
START
BYTE/VPP=VIH/VIL
Write Data 55H, Address 2AAAH
BYTE/VPP=VHH
Write Data AAH, Address 5555H
Write Data 90H, Address 5555H
Protect Status Read*
* 1. Protect Status:
Data Outputs C2H as Protected Sector Verified Code.
Data Outputs 00H as Unprotected Sector Verified Code.
2. Sepecified address will be either
(A19,A18,A17,A16,A15,A1,A0) = (0000010) or (1111110),
the rest of the address pins are don't care.
3. Silicon ID can be read via this Flow Chart.
Refer to Table 4.
30
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
LATCH-UP CHARACTERISTICS
MIN. MAX.
Input Voltage with respect to GND on all pins e xcept I/O pins -1.0V 6.6V
Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V
Current -100mA +100mA
Includes all pins except Vcc. Test conditions: Vcc = 3.3V, one pin at a time.
ERASE AND PROGRAMMING PERFORMANCE (1)
LIMITS
PARAMETER MIN. TYP.(2) MAX. UNITS
Chip/Sector Erase Time 200 1600 ms
Page Programming Time 5 150 ms
Chip Programming Time 8 0 240 sec
Erase/Program Cycles 100 Cycles
Note:
(1).Sampled, not 100% tested. Excludes external system level over head.
(2).Typing values are measured at 25°C, noninal voltage
31
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
ORDER INFORMATION
PLASTIC PACKAGE
PART NO. Access Time Operating Current Standby Current PACKAGE
(ns) MAX.(mA) MAX.(uA)
MX29L1611GPC-90 90 80 20 42 PDIP
MX29L1611GPC-10 100 80 20 42 PDIP
MX29L1611GPC-12 120 80 20 42 PDIP
32
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
PACKAGE INFORMATION
33
P/N:PM0604 REV. 0.9.1, NOV. 21, 2002
MX29L1611G
REVISION HISTORY
Revision Description Page Date
0.2 Erase/programming operation voltage change(10V -->11V) P1,4,9,14,25 Mar/15/1999
P26,27
Modify Bus operation P5
Modify command definitions P6
Modify "Automatic page program time waveforms" P2 6
Modify "Sector Protection Algorithm" P2 8
Modify "Sector unprotect Algorithm" P2 9
Modify "Erase and programming performance" P31
0.3 Description correction P1,6,7,9,13,19 MAR/23/1999
P22,23
Plug in BYTE/VPP operation description P15,16,17,18,28,29,30
0.4 Delete Page mode operation P1,9,20,22 MA Y/07/1999
Delete Erase suspend/resume operation P6,10,12,16,17,19
Modify description P1,2
Undate Erase and Program P erformance P30
0.5 Change Fast random access time:100ns-->90ns P1 APR/07/2000
Change 29L1611G-10-->29L1611G-90 P20
tACC:100-->90, tCE:100-->90
Change V erify Protect Status Flow(Figure 12)-->(Figure 11) P27,28
0.6 Modify AC Characteristics 29L1611G-10-->29L1611G-90 ; P23 APR/18/2000
tWC:120-->90 P23
0. 7 Correct ID Binary Code from 1000 to 0110 P8 JUL/10/2001
Modify Package Inf ormation P31
0.8 1. Add P age Read 30ns P1 JAN/24/2002
2. Add Page Read P9
3. Add 29L1611(G)-10 P20
4. Add Page Read Timing Waveform P21
5. Add 29L1611(G)-10 P23
6. Add Order Information P31
0.9 1. Remove MX29L1611 part number All SEP/11/2002
0.9.1 1. T o modify Package Inf ormation P3 2 NO V/21/2002
MX29L1611G
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