ATF15xx-DK3 Development Kit
..............................................................................................
User Guide
ATF15xx-DK3 Development Kit User Guide i
3605B–PLD–05/06
Table of Contents
Section 1
Introduction ........................................................................................... 1-1
1.1 CPLD Development/ Programmer Kit .......................................................1-1
1.2 Kit Contents ..............................................................................................1-1
1.3 Kit Features...............................................................................................1-1
1.3.1 CPLD Development/Programmer Board ............................................1-1
1.3.2 Logic Doubling CPLDs .......................................................................1-2
1.3.3 CPLD ISP Download Cable................................................................1-2
1.3.4 PLD Software CD-ROM......................................................................1-2
1.4 Device Support .........................................................................................1-2
1.5 System Requirements...............................................................................1-3
1.6 Ordering Information .................................................................................1-3
1.7 References................................................................................................1-4
1.7.1 ProChip Designer ...............................................................................1-4
1.7.2 Atmel-WinCUPL .................................................................................1-4
1.7.3 ATMISP ..............................................................................................1-4
1.7.4 POF2JED ...........................................................................................1-4
1.8 Technical Support .....................................................................................1-4
Section 2
Hardware Description ........................................................................... 2-1
2.1 Atmel CPLD Development/ Programmer Board........................................2-1
2.1.1 7-segment Displays with Selectable Jumpers ....................................2-2
2.1.2 LEDs with Selectable Jumpers...........................................................2-5
2.1.3 Push-button Switches with Selectable Jumpers for I/O Pins..............2-6
2.1.4 Push-button Switches with Selectable Jumpers for GCLR
and OE1 Pins .....................................................................................2-8
2.1.5 2 MHz Oscillator and Clock Selection Jumper ...................................2-9
2.1.6 VCCIO and VCCINT Voltage Selection Jumpers and LEDs ............2-10
2.1.7 ICCIO and ICCINT Jumpers.............................................................2-10
2.1.8 Voltage Regulators ...........................................................................2-10
2.1.9 Power Supply Switch and Power LED..............................................2-10
2.1.10 Power Supply Jack and Power Supply Header ................................2-10
2.1.11 JTAG ISP Connector and TDO Selection Jumper............................2-11
2.2 Socket Adapter Board .............................................................................2-12
2.3 Atmel CPLD ISP Download Cable ..........................................................2-13
Table of Contents
ii ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
Section 3
CPLD Design Flow Tutorial .................................................................. 3-1
3.1 Create a Project using the “New Project Wizard” .....................................3-1
3.2 Add a Design File......................................................................................3-7
3.3 Synthesize the VHDL Design....................................................................3-7
3.4 Fit the Synthesized Design File ................................................................3-8
3.5 Program and Verify Design .....................................................................3-10
Section 4
Schematic Diagrams and VHDL File .................................................... 4-1
ATF15xx-DK3 Development Kit User Guide 1-1
3605B–PLD–05/06
Section 1
Introduction
1.1 CPLD
Development/
Programmer Kit
The Atmel CPLD Development/Programmer Kit (P/N: ATF15xx-DK3) is a complete
development system and an In-System Programming (ISP) programmer for the
ATF15xx family of industry standard pin compatible Complex Programmable Logic
Devices (CPLDs) with Logic Doubling® features. This kit provides designers a very quick
and easy way to develop prototypes and evaluate new designs with an ATF15xx ISP
CPLD. The ATF15xx family of ISP CPLDs includes the ATF15xxAS, ATF15xxASL,
ATF15xxASV, ATF15xxASVL, and ATF15xxBE CPLDs. With the availability of the dif-
ferent Socket Adapter Boards to support all the package types(1) offered in the ATF15xx
family of ISP CPLDs, this CPLD Development/Programmer Board can be used as an
ISP programmer to program the ATF15xx ISP CPLDs in all the available package
types(1) through the industry standard JTAG interface (IEEE 1149.1).
1.2 Kit Contents CPLD Development/Programmer Board
44-pin TQFP Socket Adapter Board (P/N: ATF15xx-DK3-SAA44)(2)
Atmel CPLD ISP Multi-Volt (MV) Download Cable
Atmel PLD Software CDs (includes ProChip Designer®, Precision RTL Synthesis,
ModelSim, latest ProChip patch, Atmel-WinCUPL™, and other EPLD software)
Two 44-pin TQFP Sample Devices (one ATF1502BE and one ATF1504ASV)
Notes: 1. Socket adapter board for 100-pin PQFP is not offered.
2. Only the 44-pin TQFP Socket Adapter Board is included in this kit. Other Socket
Adapter Boards are sold separately. Please refer to Section 1.6 for ordering informa-
tion of the Socket Adapter Boards.
1.3 Kit Features
1.3.1 CPLD Development/
Programmer Board
10-pin JTAG-ISP port
Regulated power supply circuits for 9V DC power source
Selectable 5V, 3.3V, 2.5V, or 1.8V I/O voltage supply
Selectable 1.8V, 3.3V, or 5.0V core voltage supply
Introduction
1-2 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
44-pin TQFP Socket Adapter Board
Headers for I/O pins of the ATF15xx device
2 MHz Crystal Oscillator
Four 7-segment LED displays
Eight individual LEDs
Eight push-button switches
Global Clear and Output Enable push-button switches
Current measurement jumpers
1.3.2 Logic Doubling
CPLDs
ATF1502BE 1.8V low-power 32-macrocell ISP CPLD with Logic Doubling architecture
ATF1504ASV 3.3V 64-macrocell ISP CPLD with Logic Doubling architecture
1.3.3 CPLD ISP Download
Cable
5V/3.3V/2.5V/1.8V ISP Download Cable for PC Parallel Printer (LPT) Port
1.3.4 PLD Software CD-
ROM
Free Atmel-WinCUPL Design Software
ProChip Designer v4.0
ProChip Designer v4.0 Patch
Precision RTL Synthesis
ModelSim
Atmel CPLD ISP Software (ATMISP)
POF2JED Conversion Utility
User Guides and Tutorials
1.4 Device Support The Atmel CPLD Development/Programmer Board supports the following devices in all
speed grades and packages (except 100-PQFP):
ATF1502BE ATF1508ASV/ASVL
ATF1502AS/ASL ATF1502ASV
ATF1504BE ATF1504ASV/ASVL
ATF1504AS/ASL ATF1508AS/ASL
Introduction
ATF15xx-DK3 Development Kit User Guide 1-3
3605B–PLD–05/06
1.5 System
Requirements
The minimum hardware and software requirements to program an ATF15xx ISP CPLD
designed using the ProChip Designer Software on the CPLD Development/Programmer
Board through the Atmel CPLD ISP Software (ATMISP) V6.0 or later are:
Pentium® or Pentium-compatible microprocessor-based computer
Windows XP®, Windows® 98, Windows NT® 4.0, or Windows 2000
64-MByte RAM
200-MByte free hard disk space
Windows-supported mouse
Available parallel printer (LPT) port
9V DC power supply with 500 mA of supply current
SVGA monitor (800 x 600 resolution)
1.6 Ordering
Information
Other socket adapters to support other packages will be available in the near future.
Part Number Description
ATF15xx-DK3 Atmel CPLD Development/Programmer Kit
(includes ATF15xxDK3-SAA44)
ATF15xxDK3-SAA100 100-pin TQFP Socket Adapter Board for DK3 Board
ATF15xxDK3-SAJ44 44-pin PLCC Socket Adapter Board for DK3 Board
ATF15xxDK3-SAJ84 84-pin PLCC Socket Adapter Board for DK3 Board
ATF15xxDK3-SAA44 44-pin TQFP Socket Adapter Board for DK3 Board
Introduction
1-4 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
1.7 References To help PLD designers use the different Atmel PLD software, documentation such as
help files, tutorials, application notes/briefs, and user guides are available.
1.7.1 ProChip Designer
1.7.2 Atmel-WinCUPL
1.7.3 ATMISP
1.7.4 POF2JED
1.8 Technical
Support
For technical support on any Atmel PLD related issues, please contact Atmel PLD Appli-
cations Group at:
URL: www.atmel.com/dyn/products/support.asp
FAQ: www.atmel.com/dyn/products/tech_support.asp?faq=y
Hotline: 1-408-436-4333
Email : pld@atmel.com
ProChip Desinger
Help Files
From the ProChip Designer main window, click on HELP and then
select PROCHIP DESIGNER HELP.
Tutorials From the ProChip Designer main window, click on HELP and then
select TUTORIALS.
Known Problems &
Solutions
From the ProChip Designer main window, click on HELP and then
select REVIEW KPS.
Help Files From the Atmel-WinCUPL main window, click on HELP and then
select CONTENTS.
CUPL Programmers
Reference Guide
From the Atmel-WinCUPL main window, click on HELP and then
select CUPL PROGRAMMERS REFERENCE.
Tutorials From the Atmel-WinCUPL main window, click on HELP, select ATMEL
INFO and then select TUTORIAL1.PDF.
Known Problems &
Solutions
From the Atmel-WinCUPL main window, click on HELP, select ATMEL
INFO and then select CUPL_BUG.PDF.
Help Files From the ATMISP main window, click on HELP and then select ISP
HELP.
Tutorials From the ATMISP main window, click on HELP, and then select
ATMISP TUTORIAL.
Known Problems &
Solutions
Using Windows Explorer, go to the directory where ATMISP is
installed and open the README.TXT file through any ASCII text
editor.
ATF15xx Conversion
Application Brief
from the POF2JED main window, click on HELP and then select
CONVERSION OPTIONS.
ATF15xx-DK3 Development Kit User Guide 2-1
3605B–PLD–05/06
Section 2
Hardware Description
2.1 Atmel CPLD
Development/
Programmer
Board
Atmel CPLD Development/Programmer Board along with the Socket Adapter Board as
shown in Figure 2-1 contains many features that designers will find very useful when
developing, prototyping, or evaluating their ATF15xx CPLD design. Features such as
push-button switches, LEDs, 7-segment displays, 2-MHz crystal oscillator,
5V/3.3V/2.5V/1.8V VCCI/O selector, 1.8V/3.3V/5.0V VCCINT selector, JTAG-ISP port,
and socket adapters make this a very versatile starter/development kit and an ISP pro-
grammer for the ATF15xx family of JTAG-ISP CPLDs.
Figure 2-1. CPLD Development/Programmer Board with 44-pin TQFP Socket Adapter Board
Voltage
Regulators
GCLR
Switch
GOE
Switch
VccIO
Selector
VCCINT Selector
VccIO LED
VccINT LED
Power LED
Clock Selector
Power Switch
Oscillator
Power Supply Jack
Power Supply Header
JTAG Cascade Jumper
JTAG ISP Header
7-Segment
Displays
ATF15xxDK3-SAA44
Socket Adapter Board
User I/O
Pin Headers
LEDs
Device Socket
Push-Button Switches
IccINT Jumper
IccIO Jumper
Hardware Description
2-2 ATF15xx-DK3 Development Kit User Guide
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2.1.1 7-segment Displays
with Selectable
Jumpers
Atmel CPLD Development/Programmer Board contains four seven-segment displays to
allow the designers to observe the outputs of the ATF15xx CPLD. These four displays
are labeled DSP1, DSP2, DSP3, and DSP4, and have common anode LEDs with the
common anode lines connected to VCCIO (I/O supply voltage for the CPLD) through
series resistors with selectable jumpers labeled JPDSP1, JPDSP2, JPDSP3, or
JPDSP4. These jumpers can be removed to disable the displays by unconnecting the
VCCIO to the displays. Individual cathode lines are connected to the I/O pins of the
ATF15xx CPLD on the CPLD Development/Programmer Board. To turn on a particular
segment including the DOT of a display, the corresponding ATF15xx I/O pin connected
to this LED segment must be in a logic low state with the corresponding selectable
jumper set. Hence, the outputs of the ATF15xx need to be configured as active-low out-
puts in the design file. These displays work best at 2.5V VCCIO or higher.
Each segment of each display is hard-wired to one specific I/O pin of the ATF15xx. For
the higher pin count devices (100-pin and larger), all seven segments and the DOT seg-
ments of the four displays are connected to the I/O pins of the ATF15xx. However, for
the lower pin count devices, only a subset of the displays (1st and 4th displays) are con-
nected to the ATF15xx’s I/O pins. Tables 2-1, 2-2, 2-3, and 2-4 show the connections for
7-segment displays to the ATF15xx in different package types. The circuit schematic of
the displays and jumpers is shown in Figure 2-2.
Figure 2-2. Circuit Diagram of 7-segment Display and Jumpers
Hardware Description
ATF15xx-DK3 Development Kit User Guide 2-3
3605B–PLD–05/06
Table 2-1. Connections of ATF15xx 44-pin TQFP to 7-segment Displays
DSP/Segment PLD Pin # DSP/Segment PLD Pin #
1/A 27 3/A NC
1/B 33 3/B NC
1/C 30 3/C NC
1/D 21 3/D NC
1/E 18 3/E NC
1/F 23 3/F NC
1/G 20 3/G NC
1/DOT 31 3/DOT NC
2/A NC 4/A 3
2/B NC 4/B 10
2/C NC 4/C 6
2/D NC 4/D 43
2/E NC 4/E 35
2/F NC 4/F 42
2/G NC 4/G 34
2/DOT NC 4/DOT 11
Table 2-2. Connections of ATF15xx 44-pin PLCC to 7-segment Displays
DSP/Segment PLD Pin # DSP/Segment PLD Pin #
1/A 33 3/A NC
1/B 39 3/B NC
1/C 36 3/C NC
1/D 27 3/D NC
1/E 24 3/E NC
1/F 29 3/F NC
1/G 26 3/G NC
1/DOT 37 3/DOT NC
2/A NC 4/A 9
2/B NC 4/B 16
2/C NC 4/C 12
2/D NC 4/D 5
2/E NC 4/E 41
2/F NC 4/F 4
2/G NC 4/G 40
2/DOT NC 4/DOT 17
Hardware Description
2-4 ATF15xx-DK3 Development Kit User Guide
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Table 2-3. Connections of ATF15xx 84-pin PLCC to 7-segment Displays
DSP/Segment PLD Pin # DSP/Segment PLD Pin #
1/A 68 3/A 22
1/B 74 3/B 28
1/C 70 3/C 25
1/D 63 3/D 21
1/E 58 3/E 16
1/F 65 3/F 17
1/G 61 3/G 12
1/DOT 73 3/DOT 29
2/A 52 4/A 5
2/B 57 4/B 10
2/C 55 4/C 8
2/D 48 4/D 79
2/E 41 4/E 76
2/F 50 4/F 77
2/G 45 4/G 75
2/DOT 50 4/DOT 11
Table 2-4. Connections of ATF15xx 100-pin TQFP to 7-segment Displays
DSP/Segment PLD Pin # DSP/Segment PLD Pin #
1/A 67 3/A 13
1/B 71 3/B 19
1/C 69 3/C 16
1/D 61 3/D 8
1/E 57 3/E 83
1/F 64 3/F 6
1/G 60 3/G 92
1/DOT 75 3/DOT 20
2/A 52 4/A 100
2/B 54 4/B 94
2/C 47 4/C 97
2/D 41 4/D 81
2/E 46 4/E 76
2/F 40 4/F 80
2/G 45 4/G 79
2/DOT 56 4/DOT 93
Hardware Description
ATF15xx-DK3 Development Kit User Guide 2-5
3605B–PLD–05/06
2.1.2 LEDs with
Selectable Jumpers
Atmel CPLD Development/Programmer Board has eight individual LEDs, which allow
designers to display the output signals from the user I/Os of the ATF15xx CPLD. These
eight LEDs are labeled LED1 to LED8 on the Atmel CPLD Development/Programmer
Board. The cathode of each LED is connected to ground through a series resistor while
the anode of each LED is connected to a user I/O pin of the CPLD through the
JPL1/JPL2/PL3/JPL4/JPL5/JPL6/JPL7/JPL8 selectable jumper. These jumpers can be
removed to disable the LEDs by unconnecting the anodes of the LEDs to the I/O pins of
the CPLD. Figure 2-3 shows the circuit diagram of the LEDs with the selection jumpers.
To turn on a particular LED, the corresponding ATF15xx I/O pin connected to the LED
must be in a logic high state with the corresponding jumper set. Hence, the outputs of
the ATF15xx need to be configured as active-high outputs in the design files. These
LEDs work best at 2.5V VCCIO or higher.
The lower pin-count devices (44-pin) only have four I/Os connected to LED1, LED2,
LED3, and LED4. For the higher pin-count devices (100-pin and larger), all eight LEDs
are connected to the I/Os of the device. Tables 2-5, 2-6, 2-7, and 2-8 show the connec-
tions of the CPLD I/Os to the LEDs in the different package types.
Figure 2-3. Circuit Diagram of the LEDs and Jumpers
Table 2-5. Connections of ATF15xx 44-pin TQFP to LEDs
LED # PLD Pin #
LED1 28
LED2 25
LED3 22
LED4 19
Table 2-6. Connections of ATF15xx 44-pin PLCC to LEDs
LED # PLD Pin #
LED1 34
LED2 31
LED3 28
LED4 25
Hardware Description
2-6 ATF15xx-DK3 Development Kit User Guide
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2.1.3 Push-button
Switches with
Selectable Jumpers
for I/O Pins
Atmel CPLD Development/Programmer Board contains eight push-button switches,
which are connected to the I/O pins of the CPLD. They allow designers to send input
logic signals to the user I/O pins of the ATF15xx CPLD. These eight switches are
labeled SW1 to SW8 on the Atmel CPLD Development/Programmer Board. One end of
each input push-button switch is connected to VCCIO while the other end of each push-
button switch is connected to a pull-down resistor and then connected to the specific I/O
pin of the CPLD through the JPS1/JPS2/JPS3/JPS4/JPS5/JPS6/JPS7/JPS8 selectable
jumper.
If any one of these switches is pressed and the corresponding jumper is set, the specific
I/O pin of the device will be driven to a logic high state by the output of switch circuit.
Since each push-button switch is also connected to a pull-down resistor, the input will
have a logic low state if the switch is not pressed with the corresponding jumper set. If
the push-button jumper is not set, the corresponding pin will be treated as an uncon-
nected pin. Figure 2-4 on page 2-7 is a circuit diagram of the push-button switch and
selectable jumper. Tables 2-9, 2-10, 2-11, and 2-12 show the connections of these eight
push-button switches to the CPLD I/O pins in the different package types.
Table 2-7. Connections of ATF15xx 84-pin PLCC to LEDs
LED # PLD Pin #
LED1 69
LED2 67
LED3 64
LED4 60
LED5 27
LED6 24
LED7 18
LED8 15
Table 2-8. Connections of ATF15xx 100-pin TQFP to LEDs
LED # PLD Pin #
LED1 68
LED2 65
LED3 63
LED4 58
LED5 17
LED6 14
LED7 10
LED8 9
Hardware Description
ATF15xx-DK3 Development Kit User Guide 2-7
3605B–PLD–05/06
Figure 2-4. Circuit Diagram of the Push-button Switches and Jumpers for the I/O Pins
Table 2-9. Connections of ATF15xx 44-pin TQFP to the Switches for I/O Pins
Push Button # PLD Pin #
SW1 15
SW2 14
SW3 13
SW4 12
SW5 8
SW6 5
SW7 2
SW8 44
Table 2-10. Connections of ATF15xx 44-pin PLCC to the Switches for I/O Pins
Push Button # PLD Pin #
SW1 21
SW2 20
SW3 19
SW4 18
SW5 14
SW6 11
SW7 8
SW8 6
Hardware Description
2-8 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
2.1.4 Push-button
Switches with
Selectable Jumpers
for GCLR and OE1
Pins
Atmel CPLD Development/Programmer Board also contains two push-button switches
for the Global Clear (GCLR) and Output Enable (OE1) pins of the CPLD. They allow the
designers to control the logic states of the OE1 and GCLR inputs of the ATF15xx CPLD.
These two switches are labeled SW-GCLR and SW-GOE1 on the Atmel CPLD Develop-
ment/Programmer Board. One end of the SW-GCLR input push-button switch is
connected to ground (GND). The other end of the push-button switch is connected to a
pull-up resistor to VCCIO, and then connected to the GCLR dedicated input pin of the
ATF15xx. It is intended to be used as an active-low reset signal to reset the registers in
the ATF15xx with the JPGCLR selectable jumper set. Similarly, one end of the SW-
GOE1 input push-button switch is connected to ground (GND). The other end of the
push-button switch is connected to a pull-up resistor to VCCIO, and then connected to
the OE1 dedicated input pin of the ATF15xx. It is intended to be used as an active-low
output enable signal to control the enabling/disabling of the tri-state output buffers in the
ATF15xx with the JPGOE selectable jumper set. Figure 2-5 on page 2-9 is the circuit
diagram of these two push-button switches and the jumpers for the GCLR and OE1
pins.
If any of these push-button switches is pressed and the corresponding jumper is set,
then the specific I/O of the CPLD will be driven to a logic low state. Since each push-
button is also connected to a pull-up resistor, the corresponding CPLD input will have a
logic high state if the push-button switch is not pressed with the corresponding select-
able jumper set. If the selectable jumper is not set, the corresponding dedicated input
pin of the CPLD can be considered a “no connect” (NC) pin. Table 2-13 on page 2-9
Table 2-11. Connections of ATF15xx 84-pin PLCC to the Switches for I/O Pins
Push Button # PLD Pin #
SW1 54
SW2 51
SW3 49
SW4 44
SW5 9
SW6 6
SW7 4
SW8 80
Table 2-12. Connections of ATF15xx 100-pin TQFP to the Switches for I/O Pins
Push Button # PLD Pin #
SW1 48
SW2 36
SW3 44
SW4 37
SW5 96
SW6 98
SW7 84
SW8 99
Hardware Description
ATF15xx-DK3 Development Kit User Guide 2-9
3605B–PLD–05/06
shows the pin numbers of the GCLR and OE1 dedicated input pins of the ATF15xx in all
the different available package types.
Figure 2-5. Circuit Diagram of Push-button Switches and Selectable Jumpers for
GCLR and OE1
2.1.5 2 MHz Oscillator and
Clock Selection
Jumper
The Clock Selection Jumper, labeled JP-GCLK, on the CPLD Development/Program-
mer Board is a two-position jumper that allows the users to select which GCLK
dedicated input pin (either GCLK1 or GCLK2) of the ATF15xx should be connected to
the output of the 2 MHz oscillator. In addition, the jumper can be removed to allow an
external clock source to be connected to GCLK1 and/or GCLK2 of the ATF15xx. Figure
2-6 is the circuit diagram of the oscillator and selection jumper. Table 2-14 on page 2-10
shows the pin numbers for the GCLK1 and GCLK2 dedicated input pins of the ATF15xx
in all the different available package types.
Note: If GCLK1 jumper is set, the jumper will be located toward the side of the board.
On the other hand, if GCLK2 jumper is set, the jumper will be located toward the
middle of the board.
Figure 2-6. Circuit Diagram of Oscillator and Clock Selection Jumper
Table 2-13. Pin Numbers of GCLR and OE1
44-pin
TQFP
44-pin
PLCC
84-pin
PLCC
100-pin
TQFP
GCLR 39 1 1 89
OE1 38 44 84 88
Hardware Description
2-10 ATF15xx-DK3 Development Kit User Guide
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2.1.6 VCCIO and VCCINT
Voltage Selection
Jumpers and LEDs
The VCCIO and VCCINT Voltage Selection Jumpers, labeled VCCIO Selector and
VCCINT Selector respectively on ATF15xx-DK3 Development/Programming Board,
allow the designers to select I/O supply voltage level (VCCIO) and core supply voltage
level (VCCINT) that are used for the target CPLD on the board. Once these jumpers are
set correctly, the LEDs (labeled VCCINT LED and VCCIO LED) will be turn on as
expected. However, at lower supply voltage levels (i.e. 2.5V or lower), the LEDs might
be very dim.
For ATF15xxAS/ASL (5.0V) CPLDs, both the VCCIO Selector and VCCINT Selector
jumpers MUST BE set to 5.0V. For ATF15xxASV/ASVL (3.3V) CPLDs, both the VCCIO
Selector and VCCINT Selector Jumpers MUST BE set to 3.3V only. For the ATF15xxBE
(1.8V) CPLDs, designers MUST SET VCCINT Selector jumper to 1.8V for its core volt-
age supply. However, designers can set the VCCIO Selector jumper to 3.3V, 2.5V, or
1.8V (but not 5.0V) in order for the I/Os of the ATF15xxBE CPLD to interface with differ-
ent voltage levels devices.
Note: The power of the CPLD Development/Programmer Board MUST BE turned
OFF when changing the position of the VCCIO or VCCINT voltage selection
jumper (VCCIO Selector or VCCINT Selector).
2.1.7 ICCIO and ICCINT
Jumpers
The IccIO and IccINT jumpers can be removed and used as Icc measurement points.
When the jumpers are removed, current meters can be connected to the posts to mea-
sure the current consumption of the target CPLD. When users are not using these
jumpers to measure the current, these jumpers must be set in order for the board and
CPLD to operate.
2.1.8 Voltage Regulators Two voltage regulators, labeled VR1 and VR2, are used to independently generate and
regulate the VCCINT and VCCIO voltages from the 9V DC power supply. For details,
please review the schematic of the ATF15xx-DK3 board.
2.1.9 Power Supply
Switch and Power
LED
The Power Supply Switch, labeled POWER SWITCH, can be switched to the ON or
OFF position, which is used to turn on or off the power of the ATF15xx-DK3 board
respectively. It allows the 9V DC voltage at the Power Supply Jack to pass to the volt-
age regulators when it is in the ON position. When the Power Supply Switch is turned
ON, the Power LED (labeled POWER LED) will light up to indicate that the ATF15xx-
DK3 board is supplied with power.
2.1.10 Power Supply Jack
and Power Supply
Header
The Atmel ATF15xx-DK3 Development/Programmer Board contains two different types
of power supply connectors labeled JPower and JP Power. Either one of these power
supply connectors can be used to connect a 9V DC power source to the board. The first
power connector, labeled JPower, is a barrel power jack with a 2.1mm diameter post
and it mates to a 2.1mm (inner diameter) x 5.5mm (outer diameter) female plug. The
second is the power supply header, labeled JP Power, is a 4-pin male 0.1" header with
0.025" square posts. The availability of these two types of power connectors allows the
users to choose the type of power supply equipment to use for ATF15xx-DK3 Develop-
ment/Programmer Board. However, please note that only one of these two power
supply connectors should be powered with a 9V DC source but not both at the same
time.
Table 2-14. Pin Numbers of GCLK1 and GCLK2
44-pin
TQFP
44-pin
PLCC
84-pin
PLCC
100-pin
TQFP
GCLK1374383 87
GCLK2 40 2 2 90
Hardware Description
ATF15xx-DK3 Development Kit User Guide 2-11
3605B–PLD–05/06
2.1.11 JTAG ISP Connector
and TDO Selection
Jumper
The JTAG ISP Connector, labeled JTAG-IN, is used to connect the ATF15xx’s JTAG
port pins (TCK, TDI, TMS and TDO) through the ISP download cable to the parallel
printer (LPT) port of a PC for JTAG ISP programming of the ATF15xx. Polarized con-
nectors are used on the ATF15xx-DK3 and ISP Download Cable (ATDH1150VPC) Rev
6.0 or later to minimize connection problems. The PIN1 label at the bottom of the JTAG
ISP connector indicates the pin 1 position of the 10-pin header and further reduces the
chance of connecting the ISP Download Cable incorrectly.
To the left of the JTAG-IN connector, there are two columns of vias and they are labeled
JTAG-OUT. They are intended to allow the users to create a JTAG daisy chain to per-
form JTAG operations to multiple devices. Users will need to solder the same type of
connector as the one used for JTAG-IN into the JTAG-OUT position in order to utilize
this available feature.
To create a JTAG daisy chain using multiple ATF15xx-DK3 boards, the TDO Selection
Jumper, labeled JP-TDO, must be set to the appropriate position. For all the devices in
the daisy chain except the last device, this jumper must be set to the “TO NEXT
DEVICE” position. For the last device in the chain, this jumper must be set to the “TO
ISP CABLE” position. When this jumper is in the “TO NEXT DEVICE” position, the TDO
of that particular JTAG device will be connected to the TDI of the next JTAG device in
the chain. When this jumper is in the “TO ISP CABLE” position, the TDO of that device
will be connected to the TDO of the JTAG 10-pin connector, which will allow the TDO
signal of the that device in the chain to be transmitted back to the host PC with the ISP
software. Figure 2-7 below is a circuit diagram of the JTAG connectors and the JP-TDO
jumper. Table 2-15 on page 2-12 lists the pin numbers of the four JTAG pins for the
ATF15xx in all the available packages.
For a single device setup, the position of the JP-TDO jumper must be set to “TO ISP
CABLE”.
Figure 2-7. Circuit Diagram of the JTAG ISP Connectors and TDO Jumper
Hardware Description
2-12 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
The ISP algorithm is controlled by the ATMISP software, which is running on the PC.
The four JTAG signals are generated by the LPT port and they are buffered by the ISP
download cable before going into the ATF15xx on the CPLD Development/Programmer
Board. The pinout for the 10-pin JTAG Port Header on the CPLD Development/Pro-
grammer Board is shown in Figure 2-8 and the dimensions of this 10-pin male JTAG
header are shown in Figure 2-9.
Figure 2-8. Pinout Diagram of 10-pin JTAG Port Header (Top-view)
Figure 2-9. 10-pin Male Header Dimensions
The pinout of this 10-pin JTAG Port Header is compatible with the Altera® ByteBlaster,
ByteBlasterMV, and ByteBlaster II cables. In addition, the ATMISP software allows
users to choose either the Atmel CPLD ISP Cable or the ByteBlaster/ByteBlast-
erMV/ByteBlaster II cable to implement ISP.
2.2 Socket Adapter
Board
Atmel ATF15xx-DK3 CPLD Development/Programmer Socket Adapter Boards
(ATF15xx-DK3-XXXXX) are circuit boards that interface with the Atmel ATF15xx-DK3
CPLD Development/Programmer Board. They are used in conjunction with the
ATF15xx-DK3 CPLD Development/Programmer Board to evaluate/program Atmel
ATF15xx ISP CPLDs with different package types. At press time, there are four Socket
Adapter Boards available for the ATF15xx-DK3 covering the 44-TQFP, 44-PLCC, 84-
Table 2-15. Pin Numbers of JTAG Port Signals
44-pin
TQFP
44-pin
PLCC
84-pin
PLCC
100-pin
TQFP
TDI 1 7 14 4
TDO323871 73
TMS 7 13 23 15
TCK263262 62
10
87
6
3
21
5
GND TDI
NC NC
NC
TDOVCC
TMS
GND TCK
9
4
0.100 0.025 Sq.
0.235
Top ViewSide View
0.100
All dimensions are in inches
Hardware Description
ATF15xx-DK3 Development Kit User Guide 2-13
3605B–PLD–05/06
PLCC, and 100-TQFP package types in the ATF15xx family of CPLDs. Socket Adapter
boards for other packages will become available in the near future.
Each socket adapter board contains a socket for the Atmel ATF15xx device and with
male headers on the bottom side, labeled JP1 and JP2. The headers on the bottom side
mate with the female headers on the ATF15xx-DK3 board, labeled JP4 and JP3. The
four 7-segment displays, push-button switches, JTAG port signals, oscillator, VCCINT,
VCCIO, and GND on the CPLD Development/Programmer Board are connected to the
ATF15xx device on the Socket Adapter Board through these two sets of connectors.
On the top of the 44-TQFP socket adapter, there are four 10-pin connectors with the
same dimensions as the JTAG ISP connector. The pins of these four connectors are
connected to the input and I/O pins (except the four JTAG pins) of the target CPLD
device. They can be used to connect to an oscilloscope or logic analyzer to capture the
activities of the input and I/O pins of the CPLD. They also can be used to connect the
input and I/O pins of the CPLD to other external boards or devices for system level eval-
uation or testing.
2.3 Atmel CPLD ISP
Download Cable
The Atmel CPLD ISP Download Cable (P/N: ATDH1150VPC) connects the parallel
printer (LPT) port of your PC to the 10-pin JTAG header on the Atmel CPLD Develop-
ment/Programmer Board or a custom circuit board. This is shown in Figure 2-10 on
page 2-14. This ISP cable acts as a buffer to buffer the JTAG signals between the PC’s
LPT port and the ATF15xx on the circuit board. The Power-On LED on the back of the
25-pin male connector housing indicates that the cable is connected properly. Make
sure this LED is turned on before using the Atmel CPLD ISP Software (ATMISP).
This ISP cable consists of a 25-pin (DB25) male connector, which is connected to the
LPT port of a PC. The 10-pin female plug connects to the 10-pin male JTAG header on
the ISP circuit board. The red color stripe on the ribbon cable indicates the orientation of
Pin 1 of the female plug. The 10-pin male JTAG header on the CPLD Development/Pro-
grammer Board is polarized to prevent users from inserting the female plug in the wrong
orientation.
The Atmel CPLD Development/Programmer kits includes an Atmel ISP cable; however,
other supported ISP cables can also be used. The use of the ISP cable on Atmel devel-
opment kit is depending on the device that is selected.
The following shows the appropriate ISP cable that can be used for the different voltage
families of Atmel CPLDs.
1. Atmel-ISP Cable (Rev 4.0 or earlier) can be used for ATF15xxAS/ASL (5.0V)
device only.
2. Atmel-ISP Cable (Rev 5.0) can be used for ATF15xxAS/ASL (5.0V) or
ATF15xxASV/ASVL (3.3V) device only.
3. Atmel-ISP Cable (Rev 6.0), also known as the “Atmel CPLD-ISP MV Cable”,
can be used for ATF15xxAS/ASL (5.0V) or ATF15xxASV/ASVL (3.3V) or
ATF15xxBE (1.8V core) device.
4. ByteBlaster ISP Cable can be used for ATF15xxAS/ASL (5.0V) device only.
5. ByteBlasterMV ISP Cable can be used for ATF15xxAS/ASL (5.0V) or
ATF15xxASV/ASVL (3.3V) device only.
6. ByteBlaster II ISP Cable can be used for ATF15xxAS/ASL (5.0V) or
ATF15xxASV/ASVL (3.3V) or ATF15xxBE (1.8V core) device.
Hardware Description
2-14 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
Figure 2-10. Atmel ISP Cable Connection to ISP Hardware Board/Circuit Board
Figure 2-11 shows the pinout for the 10-pin female header on the Atmel ISP cable. The
pinout on the 10-pin male header on the PC board (if used for ISP) must match this
pinout.
Figure 2-11. Atmel ISP Download Cable 10-pin Female Header Pinout
Note: Your circuit board must supply Vcc and GND to the Atmel CPLD ISP Cable
through the 10-pin male header. When programming ATF15xxBE device,
VCCIO must be used for the ISP Cable.
ISP
DOWNLOAD
CABLE
Pin 1
LED
Color Stripe
13579
246810
13579
246810
Color Stripe
ATF15xx-DK3 Development Kit User Guide 3-1
3605B–PLD–05/06
Section 3
CPLD Design Flow Tutorial
This tutorial will guide you through a complete VHDL design cycle for the Atmel
ATF15xx CPLD. It provides step-by-step procedure to go through each phase of the
design cycle from design entry, logic synthesis, device fitting, in-system programming,
and finally verifying the design on the Atmel ATF15xx-DK3 CPLD Development/Pro-
gramming Board.
Note: To complete this tutorial, ProChip Designer V4.0 with Level 2 Update and
Atmel-ISP Software (ATMISP) V6.1 are required.
3.1 Create a Project
using the “New
Project Wizard”
Before starting the design process, a Project File must be created within ProChip
Designer. ProChip Designer’s New Project Wizard provides a very easy way to create a
new project file.
CPLD Design Flow Tutorial
3-2 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
1. Click on the Start > Programs > ProChip icon to launch ProChip Designer. Or
double-click on the ProChip icon on the desktop.
2. Click on Project > New or double-click on the New Project shortcut button to
launch the New Project Wizard.
3. Click on the Next button to start the project file creation process.
4. Click on the Browse button to open the browser window.
(1) Click to
launch
ProChip
Designer
(2) Click to
create new
project
(3) Click Next
to start
CPLD Design Flow Tutorial
ATF15xx-DK3 Development Kit User Guide 3-3
3605B–PLD–05/06
5. Use C:\PROCHIP\DESIGNS\VHDL as the directory of the project.
6. Enter DEV_KIT.APJ as the project filename. The extension of a project file must
be .APJ.
Note: The name and directory of the design project is specified in this window. All
design, simulation, and other project files must be placed in this project direc-
tory.
7. Choose ATF1502BE-7AU44 as the target device type for the project. Also review
the filters that allow for selection of a specific speed grade or package type.
(4) Click to
Browse
(5) Select the
project directory
(6) Enter the project
filename
(7) Select the
device type
CPLD Design Flow Tutorial
3-4 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
8. Select VHDL - Mentor Graphics as the software tool for this design flow.
ProChip Designer V4.0 with software patch level 1 and later version supports the follow-
ing design flows:
9. Select Done with parts so that there will be only one device in this project.
Design Flow Design Flow Type
CUPL – Altium CUPL design compiled through Altium Protel 99SE
Verilog – Mentor Graphics Verilog design synthesized through Mentor Graphics Precision
VHDL – Altium VHDL design synthesized through the Altium PeakFPGA
VHDL – Mentor Graphics VHDL design synthesized through Mentor Graphics Precision
Schematic – Altium Schematic design compiled through Altium Protel 99SE
(8) Select the
design flow
CPLD Design Flow Tutorial
ATF15xx-DK3 Development Kit User Guide 3-5
3605B–PLD–05/06
On the other hand, users can select Add more parts to include more parts to the cur-
rent project directory.
10. Click the Finish button to finish the New Project Wizard and the project creation
process.
This closes the New Project Wizard and opens the ProChip Designer window. The
sources in the project are shown in the left window.
(9) Select Done
with parts
(10) Select Finish
to end the New
Project Wizard
CPLD Design Flow Tutorial
3-6 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
11. Click on the ATF1502BE-7AU44 device icon to view the Design Flow window.
(11) Click on the device iconMessage window
Project Sources windowInformation dialog box
Project File windowDesign Flow window
CPLD Design Flow Tutorial
ATF15xx-DK3 Development Kit User Guide 3-7
3605B–PLD–05/06
3.2 Add a Design
File
Once the project file is created, the next step is to add the design source file(s) into your
project. For this tutorial, a single VHDL design file will be added into the project.
1. Click on the Add/Edit button from Source Manager to open the Source Manager
window. You can view the Source Manager help file by clicking on the Help but-
ton within the Source Manager window to view the description for the different
processes.
2. In the Source Manager window, click on the Add button to add a VHDL design
file to the project.
3. In the File Manager window, select .VHD from the C:\PRO-
CHIP\DESIGNS\VHDL directory as the source design file for this project.
This VHDL design is available at the end of this document.
The F02_44TQFP.VHD file is a VHDL design that uses two 7-segment displays and the
built-in oscillator on the Atmel ATF15xx-DK3 CPLD Development/Programmer Board to
generate two scrolling “0” characters. This design will also pass the states of the I/O
push-button switches (SW1-SW4) to the LEDs at LED1-LED4 on the ATF15xx-DK3
CPLD Development/Programmer Board. For details, please review the VHDL code.
3.3 Synthesize the
VHDL Design
In this part of the tutorial, the VHDL design code will be synthesized through the Mentor
Graphics Precision Synthesis process into an EDIF netlist (*.EDF), which contains a set
of optimized/minimized logic equations for the specified CPLD.
(1) Click Add/Edit
to open Source
Manager window
(2) Select VHDL
source file
(3) Click Add to
add design file
CPLD Design Flow Tutorial
3-8 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
1. Click on the VHDL - Precision button in the Design Flow window to open the
Logic Synthesis window.
2. In the Logic Synthesis window, check both options to Update Pin Assignments
after each Compilation and also Run Precision in shell mode:
3. Click on the Compile button to start the compile process. Close the log file when
the synthesis is done successfully.
Note: If you have encountered any syntax error during synthesis, the report file will
pop up to indicate which line of the code contains problem. In such case, you
must correct the syntax problem and save the file before synthesize the code
again before proceeding to the next step.
3.4 Fit the
Synthesized
Design File
In Section 3.3, the logic synthesis portion of the CPLD design flow was completed. On
successful compilation, the Precision tool will produce an EDIF output file (with .EDF
extension). An EDIF file contains the netlist of the optimized and minimized logic equa-
tions. We now need to map this netlist into a specific Atmel CPLD architecture using the
Atmel Fitter.
(1) Open the Logic
Synthesis window
(2) Check
both options
here
CPLD Design Flow Tutorial
ATF15xx-DK3 Development Kit User Guide 3-9
3605B–PLD–05/06
1. You can now proceed to the device fitter portion of the design flow by clicking on
the Atmel Fitter button.
You can either use the default options or specify fitter properties. ProChip Designer will
automatically select the EDIF file (*.EDF) associated to the current design project and
the tool type. In this example, since our target device is an ATF1502BE, we will select
the FIT1502.EXE device fitter.
The fitter creates the important JEDEC and Fit Report output files. They contain the data
for programming the device (using in-system programming or on a third-party device
programmer) and the pin assignments required for board layout respectively.
Please review the Global Device Parameters and Pin/Node Options as well. The help
files also show the Device Pin_Node lists for each of the Atmel CPLDs.
2. Make sure the JTAG box is checked. This enables the JTAG port for ISP
programming.
3. Make sure the Pin Fit Control setting is set to Keep. This will ensure that the pin
assignments in the PLD file will be kept during the place-and-route process.
4. Make sure the Logic Double setting is set to if necessary.
5. When all the fitter options are set, click on the Run Fitter button to fit the design.
(1) Open the Atmel
Fitter window
(2) Check the
JTAG box
(3) Set the Pin
Fit Control
setting to
Keep
(4) Set Logic Double
to if necessary
(5) Start the fitting
process
CPLD Design Flow Tutorial
3-10 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
The above message will be displayed after the design is successfully fit the selected
device.
If there are any error messages, you can review the exported *.FIT file or you can copy
your *.EDF file to the C:\PROCHIP\PLDFIT\ directory, open the DOS command prompt,
and then type the fit command that is starting from the second line of the *.FIT file to see
more details about the fitter errors.
Parts of the fitter report (.FIT) file generated for this design is shown below.
Total dedicated input used: 3/4 (75%)
Total I/O pins used 24/32 (75%)
Total Macro cells used 35/32 (109%)
Total Flip-Flop used 28/32 (87%)
Total Foldback logic used 15/32 (46%)
Total Nodes+FB/MCells 50/32 (156%)
Total cascade used 0
Total input pins 10
Total output pins 17
Total Pts 93
Creating pla file c:\Prochip\designs\vhdl\f02_44TQFP.tt3 with 0 inputs 0
outputs, 0 pins 0 nodes and 0 pterms...
---------------- End fitter, Design FITS
$Device TQFP44 fits
FIT1502 completed in 0.00 seconds
3.5 Program and
Verify Design
In this step of the tutorial, you will program an ATF1502BE 44-pin TQFP device on the
Atmel ATF15xx-DK3 CPLD Development/Programmer Board through ISP. Then you will
be able to verify the design by observing the four 7-segment displays and four LEDs on
the CPLD Development/Programmer Board.
You will need to follow the steps below to setup the ATMISP software (V6.0 or latest
version) in order to program the ATF1502BE 44-pin TQFP on the ATF15xx-DK3 CPLD
Development/Programmer Board.
CPLD Design Flow Tutorial
ATF15xx-DK3 Development Kit User Guide 3-11
3605B–PLD–05/06
1. To create a new chain file, the ATMISP Software first needs to be launched either
through the Program Chip button in the ProChip Designer window, the ATMISP
desktop icon or the Start > Programs > Atmel-ISP menu.
Note: If ATMISP is launched through ProChip Designer, then the appropriate chain
(.CHN) file will be automatically created by ProChip Designer. Therefore, steps
2 through 6 can be skipped.
2. To create a new chain file, select the New command under the File menu or click
on the New shortcut button.
3. The first piece of information that the software asks for when creating a new
chain is the number of devices in the JTAG chain. Therefore, enter “1” and then
click OK since you will be programming a single-device JTAG chain.
4. Next you will need to specify the properties of each JTAG device in the Device
Properties window. First, you will need to select the target device type of the first
device in the JTAG chain. For this tutorial, please select ATF1502BE as the tar-
get device type.
5. In the JTAG Instruction field, you can specify which JTAG instruction to be exe-
cuted on this device in the chain. Please select Program/Verify to program and
verify the ATF1502BE.
6. The next step is to specify the JEDEC file to be programmed into the target
device in the JEDEC File field. Click on the Browse button, change the directory
to ..\PROCHIP\DESIGNS\VHDL and then select F02_44TQFP.JED as the
(1) Launch
ATMISP
(2) Create new
chain file
(3) Enter the
number of
devices
CPLD Design Flow Tutorial
3-12 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
JEDEC file. Click OK to close the JTAG Device Properties window when all prop-
erties are specified.
The next step requires you to setup the Atmel ATF15xx-DK3 CPLD Development/Pro-
grammer Board to program the ATF1502BE-7AU44 through the CPLD ISP cable.
7. Connect the DB25 side of the Atmel CPLD ISP MV cable (Revision 6) to the PC’s
parallel port and the 10-pin header side of the cable to the Atmel ATF15xx-DK3
CPLD Development Board as shown Figure 2-10 on page 2-14.
8. Connect a 9V AC/DC power supply to the power connector (JPower) of the Atmel
ATF15xx-DK3 CPLD Development/Programmer Board.
9. Set the VCCIO Selector jumper to the 1.8V(BE) position for supplying the core
voltage of the ATF1502BE device at 1.8V, then set the VCCINT Selector jumper
to the 1.8V(BE) position for supplying the I/O pad voltage of the ATF1502BE
device at 1.8V.
Note: Make sure the ICCINT and ICCIO jumpers are in their default positions. These
two jumpers are only removed when you are connecting them from two poles of
the digital multimeter to perform current measurement.
10. Set the JPCLK jumper to GCLK1 so that the output of the crystal oscillator will go
to pin 37 (GCLK1) of the ATF1502BE. For this design, you can also set the
JPCLK jumper to GCLK2 so that the output of the crystal oscillator will go to pin
40 (GCLK2) of the ATF1502BE for selecting another global clock source.
11. Set the JPJTAG Jumper ISP Cable position, which is toward the middle of the
board.
12. Connect the 44-pin TQFP Socket Adapter Board onto the main develop-
ment/programmer board.
Note: If a device in a different package type is to be programmed, then the appropri-
ate Socket Adapter Board must be used.
13. Select which LPT port is being used for Atmel CPLD ISP cable in the Port Setting
field. LPT1 is the default port and it represents address 0x378.
14. Select the ISP download cable type in the Cable Type field. The default cable
type is the “Atmel CPLD-ISP MV”, which represents the Atmel CPLD ISP Cable
Rev 6.0, but it can be changed to other cables that can be used for other devices.
Note: The “Atmel CPLD-ISP” cable type represents the Atmel CPLD ISP Cable Rev
5.0 or older.
15. Switch the power switch to the ON position.
(4) Specify target
device type
(5) Specify JTAG
instruction
(6) Select JEDEC
file
CPLD Design Flow Tutorial
ATF15xx-DK3 Development Kit User Guide 3-13
3605B–PLD–05/06
Now both your software and hardware are setup for ISP programming and you can exe-
cute the Program/Verify instruction to program the ATF1502BE on the Atmel ATF15xx-
DK3 CPLD Development/Programmer Board.
16. Click on the Run button in the ATMISP main window to execute the JTAG
instruction to program the ATF1502BE on ATF15xx-DK3 CPLD Develop-
ment/Programmer Board.
If you do not see above message after programming of the device, please review the
troubleshooting guide and FAQs from the Atmel-ISP software to debug the problem.
After successfully programming the ATF1502BE with the F02_144TQFP.JED file, the
first and fourth 7-segment LED displays should show two rotating “0” characters. In
addition, with the setting of the LED jumpers (JPL1, JPL2, JPL3, and JPL4) and push-
button jumpers (JPS8, JPS7, JPS6, and JPS5), you can press SW8, SW7, SW6, or
SW5 to light up LEDs 1-4.
If the result is displayed correctly on the ATF15xx-DK3 CPLD Development/Program-
mer Board, then you have successfully completed this tutorial.
(13) Select the
LPT port
number
(14) Select the
cable type
(16) Click on the
Run button
ATF15xx-DK3 Development Kit User Guide 4-1
3605B–PLD–05/06
Section 4
Schematic Diagrams and VHDL File
Schematic Diagrams and VHDL File
4-2 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
Figure 4-1. ATF15xx-D3 Development/Programmer Board Schematic Diagram
a
b
c
d
e
f
Vc1
Vc2
g
a
b
c
d
e
fg
DOT
DSP1
a
b
c
d
e
f
Vc1
Vc2
g
a
b
c
d
e
fg
DOT
DSP2
a
b
c
d
e
f
Vc1
Vc2
g
a
b
c
d
e
fg
DOT
DSP3
a
b
c
d
e
f
Vc1
Vc2
g
a
b
c
d
e
fg
DOT
DSP4
RDSP2 1
RDSP2 2
RDSP2 3
RDSP2 4
RDSP2 5
RDSP2 6
RDSP2 7
RDSP3 1
RDSP3 2
RDSP3 3
RDSP3 4
RDSP3 5
RDSP3 6
RDSP3 7
RDSP4 1
RDSP4 2
RDSP4 3
RDSP4 4
RDSP4 5
RDSP4 6
RDSP4 7
VccIO
BIGATMEL
MARK
ATMEL
D2
Vin
3
ADJ
1
+Vout 2
VR1
D1
1N4001
POWER SWITCH
C1
100uF
C2
0.1uF
R3
220
R2
500
GCL R
14
23
OSC
2MHZ
GCLK2 GCLK1
1
2
3
JPGCLK
R18
1K
R17
1K
R15
1K
R16
1K
9VDC
500mA
JPower
9V DC Cente r Positive
C3
0.1uF
LM317 VccIO
VccIO
DOT2
DOT3
DOT4
RDOT2 RDOT3 RDOT4
D4A
D4B
D4C
D4D
D4E
D4F
D4G
VCCI O GND
GCLK1
TCK
VCCINT GND
GCLK2
TDO
VCCI OGND
GCLR
TDI
VCCI N TGND
GOE
TMS
12
34
56
78
910
JTAGIN
TCK
TDO
TDI
TMS
R12
4.7K
R14
10K
R13
4.7K
R11
4.7K
R1
1K
R4
280
R5
320
R6
680
JPIO18
1.8V(BE)
JPIO25
2.5V(BE)
JPIO33
3.3V(ASV/BE)
JPIO50
5V(AS)
C4
10uF
VccIN Vin
3
ADJ
1
+Vout 2
VR2
R8
220
R7
500
C5
0.1uF
LM317 VccINT
R9
600
R10
680
JPINT18
1.8V(BE)
JPINT33
3.3V(ASV)
JPINT50
5.0( AS)
C6
10uF
C9
0.1uF
C10
0.1uF
VccIO
C12
0.1uF
JP2
IccINT
JP1
IccIO
JPDSP1
JPLED1
JPDSP2
JPLED2
JPDSP3
JPLED3
JPDSP4
JPLED4
12
34
56
78
910
JTAGOUT
VccIOVccIO
1
2
3
JPJTAG
VccIO
JPGCLR JPGOE GOE
C7
0.001uF
C8
0.001uF
C11
0.1uF
VccINT
RDOT1
RDSP1 1
RDSP1 2
RDSP1 3
RDSP1 4
RDSP1 5
RDSP1 6
RDSP1 7
DOT1
LED8
GREEN
LED7
GREEN
LED6
GREEN
LED5
GREEN
JPL8
SI P 2
JPL7
SI P 2
JPL6
SI P 2
JPL5
SI P 2
RL8
220
RL7
220
RL6
220
RL5
220
D1A
D1B
D1C
D1D
D1E
D1F
D1G
D2A
D2B
D2C
D2D
D2E
D2F
D2G
D3A
D3B
D3C
D3D
D3E
D3F
D3G
D1 A
D1 B
D1 C
D1 D
D1 E
D1 F
D1 G
D2 A
D2 B
D2 C
D2 D
D2 E
D2 F
D2 G
DOT1
DOT2
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED1
LED2
D4 A
D4 B
D4 C
D4 D
D4 E
D4 F
D4 G
D3 A
D3 B
D3 C
D3 D
D3 E
D3 F
D3 G
DOT3
DOT4
LED3
LED4
LED5
LED6
LED7
LED8
LED4
GREEN
LED3
GREEN
LED2
GREEN
LED1
GREEN
JPL4
SI P 2
JPL3
SI P 2
JPL2
SI P 2
JPL1
SI P 2
RL4
220
RL3
220
RL2
220
RL1
220
R19
1K
SW1
VCCI O
C13
0.001uF
JPS1
SI P 2
R21
1K
SW2
VCCI O
C15
0.001uF
JPS2
SI P 2
R23
1K
SW3
VCCI O
C17
0.001uF
JPS3
SI P 2
R25
1K
SW4
VCCI O
C19
0.001uF
JPS4
SI P 2
R20
1K
SW5
VCCI O
C14
0.001uF
JPS5
SI P 2
R22
1K
SW6
VCCI O
C16
0.001uF
JPS6
SI P 2
R24
1K
SW7
VCCI O
C18
0.001uF
JPS7
SI P 2
R26
1K
SW8
VCCI O
C20
0.001uF
JPS8
SI P 2
SW1
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
SW- GCL R
SW- GCL R
SW-GOE
SW-GOE
VCCI N
D3
R27
1K
D4
R28
1K
C21
0.1uF
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP3
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP4
GNDGND
GND GND
GND GND
GND GND
R37
2.2K
R38
2.2K R3 9
100
R29
4.7K
SW5
R30
4.7K
SW6
R32
4.7K
SW2
R31
4.7K
SW3
R33
4.7K
SW7
R34
4.7K
SW4
R35
4.7K
SW8
R36
4.7K
1
2
3
4
JP
JP Power
Schematic Diagrams and VHDL File
ATF15xx-DK3 Development Kit User Guide 4-3
3605B–PLD–05/06
Figure 4-2. 44-pin TQFP Socket Adapter Board Schematic Diagram
c1
0.1uF
c2
0.1uF
c3
0.1uF
c4
0.1uF
VCCI NT
TDI
TMS
VCCI O
VCCINT
VCCI O
TDO
TCK
VCCINT
GND
GND
GND
GND
VCCIO GND
GCLK1
TCK
VCCINT GND
GCLK2
TDO
VCCIOGND
GCLR
TDI
VCCINTGND
GOE
TMS
D1 A
D1 B
D1 C
D1 D
D1 E
D1 F
D1 G
D2 A
D2 B
D2 C
D2 D
D2 E
D2 F
D2 G
DOT1
DOT2
LED1
LED2
D4 A
D4 B
D4 C
D4 D
D4 E
D4 F
D4 G
D3 A
D3 B
D3 C
D3 D
D3 E
D3 F
D3 G
DOT3
DOT4
LED3
LED4
LED5
LED6
LED7
LED8
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP2
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP1
GNDGND
GND GNDGND GND
GND GND
PIN38
PIN39
PIN37
PIN40
12
34
56
78
910
JL 12
34
56
78
910
JR
12
34
56
78
910
JB
12
34
56
78
910
JT
ATMEL TQFP44
TDI
1I/O
2I/O
3GND
4I/O
5
TMS
7I/O
8VCC
9I/O
10 I/O
11
I/O
6
I/O 12
I/O 13
I/O 14
I/O 15
GND 16
VCC 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
GND 24
I/O 25
TCK 26
I/O 27
I/O 28
VCC 29
I/O 30
I/O 31
TDO 32
I/O 33
I/O
34 GCLK3
35 GND
36 GCLK1
37 OE1
38 GCLR
39 I/OE2/GCLK2
40 VCC
41 I/O
42 I/O
43 I/O
44
U1
TQFP44
PIN2
PIN3
PIN5
PIN6
PIN8
PIN10
PIN11
PIN12
PIN13
PIN14
PIN15
PIN18
PIN19
PIN20
PIN21
PIN22
PIN23
PIN25
PIN27
PIN28
PIN30
PIN31
PIN33
PIN34
PIN35
PIN37
PIN38
PIN39
PIN40
PIN42
PIN43
PIN44
PIN34
PIN35
PIN42
PIN43
PIN2 PIN3
PIN5 PIN6
PIN8 PIN10
PIN11
PIN44
PIN34 PIN35
PIN37 PIN38
PIN39 PIN40
PIN42 PIN43
PIN44
PIN2 PIN3
PIN5 PIN6
PIN8 PIN10
PIN11
PIN12 PIN13
PIN14 PIN15
PIN18 PIN19
PIN20 PIN21
PIN22
PIN23
PIN25PIN27
PIN28PIN30
PIN31PIN33
PIN23
PIN25PIN27
PIN28PIN30
PIN31PIN33
PIN18
PIN19PIN20
PIN21
PIN22
BIGATMEL
MARK
ATMEL
PIN12
PIN13
PIN14
PIN15
VCCI O
Schematic Diagrams and VHDL File
4-4 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
Figure 4-3. 44-pin PLCC Socket Adapter Board Schematic Diagram
ATMEL PLCC44
TDI
7I/O
8I/O
9GND
10 I/O
11
TMS
13 I/O
14 VCC
15 I/O
16 I/O
17
I/O
12
I/O 18
I/O 19
I/O 20
I/O 21
GND 22
VCC 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
GND 30
I/O 31
TCK 32
I/O 33
I/O 34
VCC 35
I/O 36
I/O 37
TDO 38
I/O 39
I/O
40 GCLK3
41 GND
42 GCLK1
43 OE1
44 GCLR
1I/OE2/GCLK2
2VCC
3I/O
4I/O
5I/O
6
U1
PLCC44
PIN1
PIN2
VCCINT
PIN4
PIN5
PIN6
TDI
PIN8
PIN9
GND
PIN11
PIN12
TMS
PIN14
VCCIO
PIN16
PIN17
PIN18
PIN19
PIN20
PIN21
GND
VCCINT
PIN24
PIN25
PIN26
PIN27
PIN28
PIN29
GND
PIN31
TCK
PIN33
PIN34
VCCIO
PIN36
PIN37
TDO
PIN39
PIN40
PIN41
GND
PIN43
PIN44
VCCIO GND
GCLK1
TCK
VCCINT GND
GCLK2
TDO
VCCIOGND
GCLR
TDI
VCCINTGND
GOE
TMS
D1 A
D1 B
D1 C
D1 D
D1 E
D1 F
D1 G
D2 A
D2 B
D2 C
D2 D
D2 E
D2 F
D2 G
DOT1
DOT2
LED1
LED2
D4 A
D4 B
D4 C
D4 D
D4 E
D4 F
D4 G
D3 A
D3 B
D3 C
D3 D
D3 E
D3 F
D3 G
DOT3
DOT4
LED3
LED4
LED5
LED6
LED7
LED8
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP2
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP1
GNDGND
GND GNDGND GND
GND GND
PIN44
PIN1
PIN43
PIN2
PIN40
PIN41
PIN4
PIN5
PIN8 PIN9
PIN11 PIN12
PIN14 PIN16
PIN17
PIN6
PIN29
PIN31PIN33
PIN34PIN36
PIN37PIN39
PIN24
PIN25PIN26
PIN27
PIN28
PIN18
PIN19
PIN20
PIN21
12
34
56
78
910
JL
12
34
56
78
910
JB
12
34
56
78
910
JR
12
34
56
78
910
JT
PIN8 PIN9
PIN11 PIN12
PIN14 PIN16
PIN17
PIN18 PIN19
PIN20 PIN21
PIN24 PIN25
PIN26 PIN27
PIN28
PIN29 PIN31
PIN33 PIN34
PIN36 PIN37
PIN39
PIN40 PIN41
PIN43 PIN44
PIN1 PIN2
PIN4 PIN5
PIN6
c1
0.1uF
c2
0.1uF
c3
0.1uF
c4
0.1uF
VCCINTVCCIO
Schematic Diagrams and VHDL File
ATF15xx-DK3 Development Kit User Guide 4-5
3605B–PLD–05/06
Figure 4-4. 84-pin PLCC Socket Adapter Board Schematic Diagram
INPUT/GCLRn
1INPUT/OE2/GCLK2
2VCC_INT
3I/O
4I/O
5I/O
6GND
7I/O
8I/O
9I/O
10 I/O
11
I/O
12 VCC_IO
13 I/O / TDI
14 I/O
15 I/O
16 I/O
17 I/O
18 GND
19 I/O
20 I/O
21 I/O
22 I/O / TMS
23 I/O
24 I/O
25 VCC_IO
26 I/O
27 I/O
28 I/O
29 I/O
30 I/O
31 GND
32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
VCC_IO 38
I/O 39
I/O 40
I/O 41
GND 42
VCC_INT 43
I/O 44
I/O 45
I/O 46
GND 47
I/O 48
I/O 49
I/O 50
I/O 51
I/O 52
VCC_IO 53
I/O 54
I/O 55
I/O 56
I/O 57
I/O 58
GND 59
I/O 60
I/O 61
I/O / TCK 62
I/O 63
I/O 64
I/O 65
VCC_ I O 66
I/O 67
I/O 68
I/O 69
I/O 70
I/O / TDO 71
GND 72
I/O 73
I/O 74
I/O
75 I/O
76 I/O
77 VCC_IO
78 I/O
79 I/O
80 I/O
81 GND
82 INPUT/GCLK1
83 INPUT/OE1
84
ATMEL
ATF1508AS-15JC84
U1
PIN1
GND
GND
GND
GND
GND
GND
GND
GND
VCCINT
VCCIO
VCCI O
VCCI O
VCCI O
VCCIO
VCCIO
VCCINT
PIN84
PIN83
PIN2
TDI
TMS
TDO
TCK
C1
0.1uF
C2
0.1uF
C3
0.1uF
C5
0.1uF
VCCI O
SMALLATMEL
MARK1
PIN4
PIN5
PIN6
PIN8
PIN9
PIN10
PIN11
PIN12
PIN15
PIN16
PIN17
PIN18
PIN20
PIN21
PIN22
PIN24
PIN25
PIN27
PIN28
PIN29
PIN30
PIN31
PIN33
PIN34
PIN35
PIN36
PIN37
PIN39
PIN40
PIN41
PIN44
PIN45
PIN46
PIN48
PIN49
PIN50
PIN51
PIN52
PIN54
PIN55
PIN56
PIN57
PIN58
PIN60
PIN61
PIN63
PIN64
PIN65
PIN67
PIN68
PIN69
PIN70
PIN73
PIN74
PIN75
PIN76
PIN77
PIN79
PIN80
PIN81
PIN1 PIN84
PIN83
PIN2PIN4
PIN5PIN6
PIN8PIN9
PIN10PIN11
PIN75
PIN76PIN77
PIN79PIN80
PIN81
12
34
56
78
910
11 12
13 14
15 16
17 18
JP3
JPTOP
12
34
56
78
910
11 12
13 14
15 16
17 18
JP4
JPLEFT
PIN12
PIN15 PIN16
PIN17PIN18
PIN20
PIN21
PIN22
PIN24
PIN25
PIN27
PIN28
PIN29 PIN30
PIN31
12
34
56
78
910
11 12
13 14
15 16
17 18
JP6
JPBOTTOM
PIN33 PIN34
PIN35 PIN36
PIN37 PIN39
PIN40 PIN41
PIN44 PIN45
PIN46 PIN48
PIN49 PIN50
PIN51 PIN52
VCCI O GND
GCLK1
TCK
VCCI NT GND
GCLK2 TDO
VCCI OGND
GCLR
TDI
VCCI NTGND
GOE
TMS
D1 A
D1 B
D1 C
D1 D
D1 E
D1 F
D1 G
D2 A
D2 B
D2 C
D2 D
D2 E
D2 F
D2 G
DOT1
DOT2
LED1
LED2
D4 A
D4 B
D4 C
D4 D
D4 E
D4 F
D4 G
D3 A
D3 B
D3 C
D3 D
D3 E
D3 F
D3 G
DOT3
DOT4
LED3
LED4
LED5
LED6
LED7
LED8
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP2
IDC40
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP1
IDC40
GNDGND
GND GND
GND GND
GND GND
12
34
56
78
910
11 12
13 14
15 16
17 18
JP5
JPBOTTOM
PIN1
PIN2
PIN83
PIN84
PIN5
PIN6 PIN8
PIN9
PIN12
PIN15
PIN18
PIN16
PIN21
PIN17
PIN24
PIN25
PIN22
PIN29 PIN28
PIN37
PIN39PIN40
PIN41PIN44
PIN45PIN46
PIN48PIN49
PIN50PIN51 PIN52
PIN58
PIN60PIN61
PIN63
PIN64PIN65
PIN67PIN68
PIN69PIN70
PIN73PIN74
PIN54PIN55
PIN56PIN57
PIN58 PIN60
PIN61 PIN63
PIN64 PIN65
PIN67 PIN68
PIN69 PIN70
PIN73 PIN74
C7
0.1uF
C8
0.1uF
C4
0.1uF
C6
0.1uF
VCCI N T
PIN11
PIN10
PIN4
PIN80
PIN79
PIN75
PIN77
PIN57
PIN55
PIN48
PIN41
PIN50
PIN45
PIN56
PIN54
PIN51
PIN49
PIN44
PIN27
PIN76
Schematic Diagrams and VHDL File
4-6 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
Figure 4-5. 100-pin TQFP Socket Adapter Board Schematic Diagram
I/On
1I/On
2VCCIO
3TDI
4I/On
5I/O
6I/On
7I/O
8I/O
9I/O
10 GND
11 I/O
12 I/O
13 I/O
14 TMS
15 I/O
16 I/O
17 VCCIO
18 I/O
19 I/O
20 I/O
21 I/On
22 I/O
23 I/On
24 I/O
25
GND 26
I/On 27
I/On 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
VCCIO 34
I/O 35
I/O 36
I/O 37
GND 38
VCCINT 39
I/O 40
I/O 41
I/O 42
GND 43
I/O 44
I/O 45
I/O 46
I/O 47
I/O 48
I/On 49
I/On 50
VCCIO 51
I/O 52
I/On 53
I/O 54
I/On 55
I/O 56
I/O 57
I/O 58
GND 59
I/O 60
I/O 61
TCK 62
I/O 63
I/O 64
I/O 65
VCCIO 66
I/O 67
I/O 68
I/O 69
I/On 70
I/O 71
I/On 72
TDO 73
GND 74
I/O 75
ATMEL TQFP100
I/O
76 I/On
77 I/O
78 I/On
79 I/O
80 I/O
81 VCCIO
82 I/O
83 I/O
84 I/O GCLK3
85 GND
86 GCLK1
87 OE1
88 GCLR
89 GCLK2
90 VCCINT
91 I/O
92 I/O
93 I/O
94 GND
95 I/O
96 I/O
97 I/O
98 I/O
99 I/O
100
U1
TQFP100
PIN1
PIN2
VCCIO
TDI
PIN5
PIN6
PIN7
PIN8
PIN9
PIN10
GND
PIN12
PIN13
PIN14
TMS
PIN16
PIN17
VCCIO
PIN19
PIN20
PIN21
PIN22
PIN23
PIN24
PIN25
GND
PIN27
PIN28
PIN29
PIN30
PIN31
PIN32
PIN33
VCCIO
PIN35
PIN36
PIN37
GND
VCCINT
PIN40
PIN41
PIN42
GND
PIN44
PIN45
PIN46
PIN47
PIN48
PIN49
PIN50
VCCIO
PIN52
PIN53
PIN54
PIN55
PIN56
PIN57
PIN58
GND
PIN60
PIN61
TCK
PIN63
PIN64
PIN65
VCCIO
PIN67
PIN68
PIN69
PIN70
PIN71
PIN72
TDO
GND
PIN75
PIN76
PIN77
PIN78
PIN79
PIN80
PIN81
VCCIO
PIN83
PIN84
PIN85
GND
PIN87
PIN88
PIN89
PIN90
VCCINT
PIN92
PIN93
PIN94
GND
PIN96
PIN97
PIN98
PIN99
PIN100
C1
0.1uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
VCCIO
C5
0.1uF
C6
0.1uF
VCCINT
VCCIO GND
GCLK1
TCK
VCCINT GND
GCLK2
TDO
VCCI OGND
GCLR
TDI
VCCINTGND
GOE
TMS
D1 A
D1 B
D1 C
D1 D
D1 E
D1 F
D1 G
D2 A
D2 B
D2 C
D2 D
D2 E
D2 F
D2 G
DOT1
DOT2
LED1
LED2
D4 A
D4 B
D4 C
D4 D
D4 E
D4 F
D4 G
D3 A
D3 B
D3 C
D3 D
D3 E
D3 F
D3 G
DOT3
DOT4
LED3
LED4
LED5
LED6
LED7
LED8
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP2
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP1
GNDGND
GND GNDGND GND
GND GND
PIN88
PIN89
PIN87
PIN90
PIN76
PIN79
PIN80
PIN81
PIN84
PIN92
PIN93
PIN94PIN96
PIN97PIN98
PIN83
PIN64
PIN65PIN67
PIN68PIN69
PIN71 PIN75
PIN57
PIN58PIN60
PIN61
PIN63
PIN37
PIN44
PIN46
PIN48
PIN9
PIN10
PIN14
PIN17
PIN20
PIN13
PIN19
PIN16
PIN8
PIN100
PIN6
PIN99
PIN56
PIN47
PIN52
PIN45
PIN41
PIN40 PIN36
PIN54
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
JL
HEADER 11X2
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
JT
HEADER 11X2
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
JR
HEADER 11X2
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
JB
HEADER 11X2
PIN1
PIN2
PIN5
PIN6
PIN7
PIN8
PIN9
PIN10
PIN12
PIN13
PIN14
PIN16
PIN17
PIN19
PIN20
PIN21
PIN22
PIN23
PIN24
PIN25
PIN27
PIN28
PIN29
PIN30
PIN31
PIN32
PIN33 PIN35
PIN36 PIN37
PIN40 PIN41
PIN42 PIN44
PIN45
PIN46
PIN47
PIN48
PIN49
PIN50
PIN52PIN53
PIN54
PIN55 PIN56
PIN57
PIN58PIN60
PIN61PIN63
PIN64PIN65
PIN67PIN68
PIN69
PIN70
PIN71
PIN72
PIN75
PIN76 PIN77
PIN78
PIN79 PIN80
PIN81
PIN83
PIN84
PIN85
PIN87
PIN88PIN89
PIN90
PIN92PIN93
PIN94PIN96
PIN97PIN98
PIN99 PIN100
C7
0.1uF
C8
0.1uF
C9
0.1uF
C10
0.1uF
Schematic Diagrams and VHDL File
ATF15xx-DK3 Development Kit User Guide 4-7
3605B–PLD–05/06
------------------------------------------------------------------------------------
-- Library Declaration
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;
------------------------------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------------------------------
entity f02_44TQFP is
port
(
GCLK1 : in std_logic; -- 2MHz clock (positive edge)
GCLK2 : in std_logic; -- 2MHz clock (negative edge)
GCLR : in std_logic; -- Register reset
SW : in std_logic_vector(8 downto 5);-- Switches
DSP1 : inout std_logic_vector(5 downto 0);-- 7-segment display LEDs (F to A)
DSP4 : inout std_logic_vector(5 downto 0);-- 7-segment display LEDs (F to A)
LED : out std_logic_vector(4 downto 1)-- LEDs
);
------------------------------------------------------------------------------------
-- Pin Assignment
------------------------------------------------------------------------------------
attribute pinnum: string;
attribute pinnum of GCLK1: signal is"37";
attribute pinnum of GCLK2: signal is"40";
attribute pinnum of GCLR: signal is"39";
attribute pinnum of SW: signal is"12,13,14,15";
attribute pinnum of DSP1: signal is"23,18,21,30,33,27";
attribute pinnum of DSP4: signal is"42,35,43,6,10,3";
attribute pinnum of LED: signal is"19,22,25,28";
end entity f02_44TQFP;
------------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------------
architecture LOGIC of f02_44TQFP is
------------------------------------------------------------------------------------
-- Internal Signal Declaration
------------------------------------------------------------------------------------
signal CNT1: unsigned(15 downto 0);
signal iCLK : std_logic;
Schematic Diagrams and VHDL File
4-8 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
begin
iCLK <= GCLK1 or GCLK2;
------------------------------------------------------------------------------------
-- Frequency Divider
------------------------------------------------------------------------------------
FREQ_DIV1 : process (iCLK,GCLR)
begin
if (GCLR = '0') then
CNT1 <= (others => '0');
elsif (rising_edge(iCLK)) then
CNT1 <= CNT1 + 1;
end if;
end process;
------------------------------------------------------------------------------------
-- LED Control
------------------------------------------------------------------------------------
LED_CTL : process (SW)
begin
LED(1) <= SW(5);
LED(2) <= SW(6);
LED(3) <= SW(7);
LED(4) <= SW(8);
end process;
------------------------------------------------------------------------------------
-- DSP Control
------------------------------------------------------------------------------------
DSP_CTL : process (CNT1(15), GCLR)
begin
if (GCLR = '0') then
DSP1 <= (others => '0');
DSP4 <= (others => '0');
elsif rising_edge(CNT1(15)) then
DSP1(0) <= not DSP1(5);
DSP1(1) <= DSP1(0);
DSP1(2) <= DSP1(1);
DSP1(3) <= DSP1(2);
DSP1(4) <= DSP1(3);
DSP1(5) <= DSP1(4);
DSP4(0) <= not DSP4(5);
Schematic Diagrams and VHDL File
ATF15xx-DK3 Development Kit User Guide 4-9
3605B–PLD–05/06
DSP4(1) <= DSP4(0);
DSP4(2) <= DSP4(1);
DSP4(3) <= DSP4(2);
DSP4(4) <= DSP4(3);
DSP4(5) <= DSP4(4);
end if;
end process;
end architecture LOGIC;
3605B–PLD–05/06
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