Surface Mount RF PIN Low
Distortion Attenuator Diodes
Technical Data
Features
• Diodes Optimized for:
– Low Distortion Attenuating
– Microwave Frequency
Operation
• Surface Mount Packages
– Single and Dual Versions
– Tape and Reel Options
Available
• Low Failure in Time (FIT)
Rate[1]
Note:
1. For more information see the
Surface Mount PIN Reliability Data
Sheet.
HSMP-381x Series and
HSMP-481x Series
Package Lead Code
Identification, SOT-23
(Top View)
Description/Applications
The HSMP-381x series is
specifically designed for low
distortion attenuator applica-
tions. The HSMP-481x products
feature ultra low parasitic
inductance in the SOT-23 and
SOT-323 packages. They are
specifically designed for use at
frequencies which are much
higher than the upper limit for
conventional diodes.
A SPICE model is not available
for PIN diodes as SPICE does not
provide for a key PIN diode
characteristic, carrier lifetime.
COMMON
CATHODE
#4
COMMON
ANODE
#3
SERIES
#2
SINGLE
#0
12
3
12
3
12
3
12
3
4810
12
3
DUAL CATHODE
Package Lead Code
Identification, SOT-323
(Top View)
COMMON
CATHODE
F
COMMON
ANODE
E
SERIES
C
SINGLE
B
481B
DUAL CATHODE
2
Absolute Maximum Ratings[1] TC = +25°C
Symbol Parameter Unit SOT-23 SOT-323
IfForward Current (1 µs Pulse) Amp 1 1
PIV Peak Inverse Voltage V Same as VBR Same as VBR
TjJunction Temperature °C 150 150
Tstg Storage Temperature °C -65 to 150 -65 to 150
θjc Thermal Resistance[2] °C/W 500 150
Notes:
1. Operation in excess of any one of these conditions may result in permanent damage to
the device.
2. TC = +25°C, where TC is defined to be the temperature at the package pins where
contact is made to the circuit board.
Electrical Specifications TC = +25°C (Each Diode)
Conventional Diodes
Minimum Maximum Maximum Minimum Maximum
Part Package Breakdown Total Total High Low
Number Marking Lead Voltage Resistance Capacitance Resistance Resistance
HSMP- Code Code Configuration VBR (V) RT (Ω)C
T (pF) RH (Ω)R
L (Ω)
3810 E0[1] 0 Single 100 3.0 0.35 1500 10
3812 E2[1] 2 Series
3813 E3[1] 3 Common Anode
3814 E4[1] 4 Common Cathode
381B E0[2] B Single
381C E2[2] C Series
381E E3[2] E Common Anode
381F E4[2] F Common Cathode
Test Conditions VR = VBR IF = 100 mA VR = 50 V IR = 0.01 mA IF = 20 mA
Measure f = 100 MHz f = 1 MHz f = 100 MHz f= 100 MHz
IR ≤ 10 µA
High Frequency (Low Inductance, 500 MHz – 3 GHz) PIN Diodes
Minimum Maximum Typical Maximum Typical
Part Package Breakdown Series Total Total Total
Number Marking Lead Voltage Resistance Capacitance Capacitance Inductance
HSMP- Code Code Configuration VBR (V) RS (Ω)C
T (pF) CT (pF) LT (nH)
4810 EB B[1] Dual Cathode 100 3.0 0.35 0.4 1.0
481B EB B[2] Dual Cathode
Test Conditions VR = VBR IF = 100 mA VR = 50 V VR = 50 V f = 500 MHz–
Measure f = 1 MHz f = 1 MHz 3 GHz
IR ≤ 10 µAV
R = 0 V
Notes:
1. Package marking code is white.
2. Package laser marked.
3
Typical Parameters at TC = 25°C
Part Number Series Resistance Carrier Lifetime Reverse Recovery Time Total Capacitance
HSMP- RS (Ω)τ (ns) Trr (ns) CT (pF)
381x 75 1500 300 0.27 @ 50 V
Test Conditions IF = 1 mA IF = 50 mA VR = 10 V f = 1 MHz
f = 100 MHz IR = 250 mA IF = 20 mA
90% Recovery
Typical Parameters at TC = 25°C (unless otherwise noted), Single Diode
10000
1000
100
10
1
RF RESISTANCE (OHMS)
0.01 0.1 1 10 100
I
F
– FORWARD BIAS CURRENT (mA)
T
A
= +85°C
T
A
= +25°C
T
A
= –55°C
Figure 2. RF Resistance vs. Forward
Bias Current.
0.15
0.30
0.25
0.20
0.35
0.40
0.45
02 64101281614 18 20
TOTAL CAPACITANCE (pF)
REVERSE VOLTAGE (V)
Figure 1. RF Capacitance vs. Reverse
Bias.
1 MHz
30 MHz
frequency>100 MHz
120
110
100
90
80
70
60
50
40
1000 100 10
Diode Mounted as a
Series Attenuator
in a 50 Ohm Microstrip
and Tested at 123 MHz
DIODE RF RESISTANCE (OHMS)
Figure 3. 2nd Harmonic Input
Intercept Point vs. Diode RF
Resistance.
INPUT INTERCEPT POINT (dBm)
100
10
1
0.1
0.010 0.2 0.4 0.6 0.8 1.0 1.2
I
F
– FORWARD CURRENT (mA)
V
F
– FORWARD VOLTAGE (mA)
Figure 4. Forward Current vs.
Forward Voltage.
125°C 25°C–50°C
INPUT RF IN/OUT
Figure 5. Four Diode π Attenuator. See Application Note 1048
for Details.
FIXED
BIAS
VOLTAGE
VARIABLE BIAS
Typical Applications for Multiple Diode Products
4
Typical Applications for HSMP-481x Low Inductance Series
Microstrip Series
Connection for
HSMP-481x Series
In order to take full advantage of
the low inductance of the
HSMP-481x series when using
them in series applications,
both lead 1 and lead 2 should be
connected together, as shown in
Figure 7.
Figure 7. Circuit Layout.
0.3 nH
0.3 nH
0.3 pFR
j
1.5 nH 1.5 nH
Figure 9. Equivalent Circuit.
R
j
≈
0.08
+ 2.5
I
b0.9
12
3
Figure 6. Internal Connections.
HSMP-481x
Microstrip Shunt
Connections for
HSMP-481x Series
In Figure 8, the center
conductor of the microstrip
line is interrupted and
leads 1 and 2 of the
HSMP-481x series diode are
placed across the resulting gap.
This forces the 1.5 nH lead
inductance of leads 1 and 2 to
appear as part of a low pass
filter, reducing the shunt
parasitic inductance and
increasing the maximum
available attenuation. The
0.3 nHof shunt inductance
external to the diode is created
by the via holes, and is a good
estimate for 0.032" thick material.
50 OHM MICROSTRIP LINES
PAD CONNECTED TO
GROUND BY TWO
VIA HOLES
Figure 8. Circuit Layout.
5
Typical Applications for HSMP-481x Low Inductance Series (continued)
Figure 10. Circuit Layout.
Co-Planar Waveguide
Groundplane
Center Conductor
Groundplane
Co-Planar Waveguide
Shunt Connection for
HSMP-481x Series
Co-Planar waveguide, with
ground on the top side of the
printed circuit board, is shown
in Figure 10. Since it eliminates
the need for via holes to ground,
it offers lower shunt parasitic
inductance and higher maximum
attenuation when compared to a
microstrip circuit.
Figure 11. Equivalent Circuit.
0.3 pF
0.75 nH
R
j
0.18 pF*
* Measured at -20 V
2.5 Ω
R
j
R
s
C
j
R
j
= 80 Ω
I
0.9
R
T
= 2.5 + R
j
C
T
= C
P
+ C
j
I
= Forward Bias Current in mA
*See AN1124 for package models.
Equivalent Circuit Model
HSMS-381x Chip*
6
Assembly Information
SOT-323 PCB Footprint
A recommended PCB pad layout
for the miniature SOT-323 (SC-70)
package is shown in Figure 12
(dimensions are in inches). This
layout provides ample allowance
for package placement by auto-
mated assembly equipment
without adding parasitics that
could impair the performance.
0.026
0.035
0.07
0.016
Figure 12. PCB Pad Layout
(dimensions in inches).
SOT-23 PCB Footprint
0.037
0.95
0.037
0.95
0.079
2.0
0.031
0.8
DIMENSIONS IN inches
mm
0.035
0.9
Figure 13. PCB Pad Layout.
TIME (seconds)
T
MAX
TEMPERATURE (°C)
0
0
50
100
150
200
250
60
Preheat
Zone Cool Down
Zone
Reflow
Zone
120 180 240 300
Figure 14. Surface Mount Assembly Profile.
SMT Assembly
Reliable assembly of surface
mount components is a complex
process that involves many
material, process, and equipment
factors, including: method of
heating (e.g., IR or vapor phase
reflow, wave soldering, etc.)
circuit board material, conductor
thickness and pattern, type of
solder alloy, and the thermal
conductivity and thermal mass of
components. Components with a
low mass, such as the SOT-323/-23
package, will reach solder reflow
temperatures faster than those
with a greater mass.
Agilent’s diodes have been
qualified to the time-temperature
profile shown in Figure 14. This
profile is representative of an IR
reflow type of surface mount
assembly process.
After ramping up from room
temperature, the circuit board
with components attached to it
(held in place with solder paste)
passes through one or more
preheat zones. The preheat zones
increase the temperature of the
board and components to prevent
thermal shock and begin evaporat-
ing solvents from the solder paste.
The reflow zone briefly elevates
the temperature sufficiently to
produce a reflow of the solder.
The rates of change of tempera-
ture for the ramp-up and cool-
down zones are chosen to be low
enough to not cause deformation
of the board or damage to compo-
nents due to thermal shock. The
maximum temperature in the
reflow zone (TMAX) should not
exceed 235°C.
These parameters are typical for a
surface mount assembly process
for Agilent diodes. As a general
guideline, the circuit board and
components should be exposed
only to the minimum tempera-
tures and times necessary to
achieve a uniform reflow of
solder.
7
Package Dimensions
Outline SOT-323 (SC-70)
Package Characteristics
Lead Material...................................Copper (SOT-323); Alloy 42 (SOT-23)
Lead Finish............................................................................Tin-Lead 85-15%
Maximum Soldering Temperature.............................. 260°C for 5 seconds
Minimum Lead Strength.......................................................... 2 pounds pull
Typical Package Inductance .................................................................. 2 nH
Typical Package Capacitance ..............................0.08 pF (opposite leads)
3
12
SIDE VIEW
TOP VIEW
END VIEW
DIMENSIONS ARE IN MILLIMETERS (INCHES)
1.02 (0.040)
0.89 (0.035)
0.50 (0.024)
0.45 (0.018)
1.40 (0.055)
1.20 (0.047) 2.65 (0.104)
2.10 (0.083)
3.06 (0.120)
2.80 (0.110)
2.04 (0.080)
1.78 (0.070)
1.02 (0.041)
0.85 (0.033)
0.152 (0.006)
0.066 (0.003)
0.10 (0.004)
0.013 (0.0005) 0.69 (0.027)
0.45 (0.018)
0.54 (0.021)
0.37 (0.015)
X X X
PACKAGE
MARKING
CODE (XX)
DATE CODE (X)
Outline 23 (SOT-23)
2.20 (0.087)
2.00 (0.079) 1.35 (0.053)
1.15 (0.045)
1.30 (0.051)
REF.
0.650 BSC (0.025)
2.20 (0.087)
1.80 (0.071)
0.10 (0.004)
0.00 (0.00)
0.25 (0.010)
0.15 (0.006) 1.00 (0.039)
0.80 (0.031) 0.20 (0.008)
0.10 (0.004)
0.30 (0.012)
0.10 (0.004)
0.30 REF.
10°
0.425 (0.017)
TYP.
DIMENSIONS ARE IN MILLIMETERS (INCHES)
PACKAGE
MARKING
CODE (XX)
X X X
DATE CODE (X)
Ordering Information
Specify part number followed by option. For example:
HSMP - 381x - XXX
Bulk or Tape and Reel Option
Part Number; x = Lead Code
Surface Mount PIN
Option Descriptions
-BLK = Bulk, 100 pcs. per antistatic bag
-TR1 = Tape and Reel, 3000 devices per 7" reel
-TR2 = Tape and Reel, 10,000 devices per 13" reel
Tape and Reeling conforms to Electronic Industries RS-481, “Taping of
Surface Mounted Components for Automated Placement.”
www.semiconductor.agilent.com
Data subject to change.
Copyright © 1999 Agilent Technologies
5968-5427E (11/99)
USER
FEED
DIRECTION COVER TAPE
CARRIER
TAPE
REEL END VIEW
8 mm
4 mm
TOP VIEW
### ### ### ###
Note: “###” represents Package Marking Code,
Date Code.
Device Orientation
Tape Dimensions
For Outline SOT-323 (SC-70 3 Lead)
P
P
0
P
2
FW
C
D
1
D
E
A
0
8° MAX.
t
1
(CARRIER TAPE THICKNESS) T
t
(COVER TAPE THICKNESS)
5° MAX.
B
0
K
0
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A
0
B
0
K
0
P
D
1
2.24 ± 0.10
2.34 ± 0.10
1.22 ± 0.10
4.00 ± 0.10
1.00 + 0.25
0.088 ± 0.004
0.092 ± 0.004
0.048 ± 0.004
0.157 ± 0.004
0.039 + 0.010
CAVITY
DIAMETER
PITCH
POSITION
D
P
0
E
1.55 ± 0.05
4.00 ± 0.10
1.75 ± 0.10
0.061 ± 0.002
0.157 ± 0.004
0.069 ± 0.004
PERFORATION
WIDTH
THICKNESS W
t
1
8.00 ± 0.30
0.255 ± 0.013 0.315 ± 0.012
0.010 ± 0.0005
CARRIER TAPE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P
2
3.50 ± 0.05
2.00 ± 0.05
0.138 ± 0.002
0.079 ± 0.002
DISTANCE
WIDTH
TAPE THICKNESS C
T
t
5.4 ± 0.10
0.062 ± 0.001 0.205 ± 0.004
0.0025 ± 0.00004
COVER TAPE
