IRF1405Z
IRF1405ZS
IRF1405ZL
HEXFET® Power MOSFET
VDSS = 55V
RDS(on) = 4.9mΩ
ID = 75A
08/29/03
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AUTOMOTIVE MOSFET
Description
Specifically designed for Automotive applications,
this HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating . These features com-
bine to make this design an extremely efficient and
reliable device for use in Automotive applications
and a wide variety of other applications.
S
D
G
Features
lAdvanced Process Technology
lUltra Low On-Resistance
l175°C Operating Temperature
lFast Switching
lRepetitive Avalanche Allowed up to Tjmax
Absolute Maxi mum Rat i ngs
Parameter Units
ID @ TC = 25°C Continuous Drai n Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C Continuous Drai n Current, VGS @ 10V A
ID @ TC = 25°C Continuous Drai n Current, VGS @ 10V (Package Limited)
IDM Pulsed Drai n Current
c
PD @TC = 25°C Power Dissipation W
Linear Derating Fac t or W/°C
VGS Gate-to-Source Voltage V
EAS (Thermally limited) Single Pul se Avalanche Energy
d
mJ
EAS (Tested ) Single Pul se Avalanche Energy Tested Value
h
IAR Avalanche Current
c
A
EAR Repetitive Avalanche Energy
g
mJ
TJ Operating Junction and
TSTG Storage Temperat ure Range °C
Soldering Temperat ure, for 10 sec onds
Mounting Torque, 6-32 or M 3 screw
Thermal Resistance Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.65
RθCS Case-to-Si nk, Flat, Greased Surfac e 0.50 ––– °C/W
RθJA Junction-to-Ambient ––– 62
RθJA Junct i on-to-Ambient (P CB Mount, steady s tate)
i
––– 40
420
270
See Fig.12a, 12b, 15, 16
230
1.5
± 20
Max.
150
110
600
75
-55 to + 175
300 (1.6mm f rom case )
10 lbf
y
in (1.1N
y
m)
HEXFET® is a registered trademark of International Rectifier.
D2Pak
IRF1405ZS
TO-220AB
IRF1405Z TO-262
IRF1405ZL
PD - 94645A
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S
D
G
S
D
G
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
V(BR)DSS Drai n-to-Source B reak down Voltage 55 ––– ––– V
∆V(BR)DSS
/
∆TJ Breakdown Voltage Temp. Coeff i cient ––– 0.049 ––– V/°C
RDS(on) Static Drai n-to-Source On-Res i stance ––– 3.7 4.9 mΩ
VGS(th) Gate Threshol d V ol tage 2.0 ––– 4.0 V
gfs Forward Transconductance 88 ––– ––– S
IDSS Drain-to-S ource Leakage Current ––– ––– 20 µA
––– ––– 250
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA
Gate-to-Source Reverse Leak age ––– ––– -200
QgTotal Gate Charge ––– 120 180
Qgs Gate-to-Source Charge ––– 31 ––– nC
Qgd Gate-to-Drain ("Miller") Charge ––– 46 –––
td(on) Turn-On Delay Time ––– 18 –––
trRise Time ––– 110 –––
td(off) Turn-Off Del ay Ti m e ––– 48 ––– ns
tfFall Time ––– 82 –––
LDInternal Drain I nductance ––– 4.5 ––– Between lead,
nH 6mm (0.25in.)
LSInternal Source Induct ance ––– 7.5 ––– from package
and center of di e contact
Ciss Input Capacit ance ––– 4780 –––
Coss Output Capacit ance ––– 770 –––
Crss Reverse Transfer Capacitance ––– 410 ––– pF
Coss Output Capacit ance ––– 2730 –––
Coss Output Capacit ance ––– 600 –––
Coss eff. Effec t i ve Output Capac i tance ––– 910 –––
Source-Drain Ratin
g
s and Characteristics
Parameter Min. Typ. Max. Units
ISContinuous S ource Current ––– ––– 75
(Body Diode) A
ISM Pulsed S ource Current ––– ––– 600
(Body Diode)
c
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reverse Recovery Time ––– 30 46 ns
Qrr Reverse Rec overy Charge ––– 30 45 nC
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 44V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 44V
f
VGS = 10V
e
VDD = 25V
ID = 75A
RG = 4.4Ω
TJ = 25°C, IS = 75A, V GS = 0V
e
TJ = 25°C, IF = 75A, V DD = 25V
di/dt = 100A/µs
e
Conditions
VGS = 0V, ID = 250µA
Reference t o 25° C, ID = 1mA
VGS = 10V, ID = 75A
e
VDS = VGS, ID = 250µA
VDS = 55V, VGS = 0V
VDS = 55V, VGS = 0V, TJ = 125°C
MOSFET symbol
showing the
integral rev erse
p-n juncti on di ode.
VDS = 25V, I D = 75A
ID = 75A
VDS = 44V
Conditions
VGS = 10V
e
VGS = 0V
VDS = 25V
ƒ = 1.0MHz
VGS = 20V
VGS = -20V
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.10mH
RG = 25Ω, IAS = 75A, VGS =10V. Part not
recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from 0 to 80%
VDSS .
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical
repetitive avalanche performance.
This value determined from sample failure population.
100%tested to this value in production.
This is applied to D2Pak, when mounted on 1" square PCB
( FR-4 or G-10 Material ). For recommended footprint and
soldering techniques refer to application note #AN-994.
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Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance
vs. Drain Current
0.1 110 100
VDS, Drain-t o-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
4.5V
20µs PULSE WIDTH
Tj = 25°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
0.1 110 100
VDS, Drain-t o-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
4.5V
20µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
46810 12
VGS, Gate-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (Α)
TJ = 25°C
TJ = 150°C
VDS = 25V
20µs PULSE WIDTH
0 25 50 75 100 125 150 175 200
ID,Drain-to-Source Current (A)
0
25
50
75
100
125
150
175
200
Gfs, Forward Transconductance (S)
TJ = 25°C
TJ = 175°C
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C, Capacitance(pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0 20 40 60 80 100 120
QG T ot al Gat e Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
VGS, Gate-to-Source Voltage (V)
VDS= 44V
VDS= 28V
ID= 75A
0.0 0.5 1.0 1.5 2.0 2.5
VSD, Source-to-Drain Voltage (V)
0.10
1.00
10.00
100.00
1000.00
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
1 10 100 1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
1msec
10msec
OPERATIO N IN THI S AREA
LIMITED BY RDS(on)
100µsec
Tc = 25°C
Tj = 175°C
Single Pulse
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature Fig 10. Normalized On-Resistance
vs. Temperature
25 50 75 100 125 150 175
TC , Case T emperature (°C)
0
25
50
75
100
125
150
ID, Drain Current (A)
Limited By Package
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (° C)
0.5
1.0
1.5
2.0
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 75A
VGS = 10V
1E-006 1E-005 0.0001 0.001 0.01 0.1 110
t1 , Rectangular Pulse Durati on (sec)
0.001
0.01
0.1
1
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPO NSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + T c
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QG
QGS QGD
VG
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage vs. Temperature
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
25 50 75 100 125 150 175
Starting TJ , Junction Tem perat ure (° C)
0
100
200
300
400
500
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 31A
53A
BOTTOM 75A
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperat ure ( ° C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VGS(th) Gate threshold Voltage (V)
ID = 250µA
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Fig 15. Typical Avalanche Current vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3· BV· Zth]
EAS (AR) = PD (ave)·tav
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
10000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses
0.01
25 50 75 100 125 150 175
Starting TJ , Junction Tem perat ure (° C)
0
50
100
150
200
250
300
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 10% Duty Cycle
ID = 75A
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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
V
DS
90%
10%
V
GS t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
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LEAD ASSIGNMENTS
1 - GAT E
2 - DRAIN
3 - SOURCE
4 - DRAIN
- B -
1.32 (.052)
1.22 (.048)
3X 0. 55 (. 02 2)
0. 46 (. 01 8)
2.92 (.115)
2.64 (.104)
4.69 (.185)
4.20 (.165)
3X 0.93 (.037)
0.69 (.027)
4.06 (.160)
3.55 (.140)
1. 15 (. 04 5)
MIN
6.47 (.255)
6.10 (.240)
3.78 (.149)
3.54 (.139)
- A -
10. 54 (.41 5)
10. 29 (.40 5)
2.87 (.113)
2.62 (.103)
15.24 (.600)
14.84 (.584)
14.09 (.555)
13.47 (.530)
3X 1.40 (. 05 5)
1.15 (. 04 5)
2.54 (.100)
2X
0.36 (.014) M B A M
4
1 2 3
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
2 CONTROLLING DIMENSION : INCH 4 HEATSI NK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
EXAMPLE : THIS IS AN IRF1010
WITH ASSEMBLY
LOT CODE 9B1M
ASSEMBLY
LOT CODE
DATE CODE
(YYWW)
YY = YEAR
WW = WEEK
9246
IRF1010
9B 1M
A
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D2Pak Part Marking Information
F530S
THIS IS AN IRF530S WIT H
LOT CODE 8024
AS S E MBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
ASSEMBLY
LOT CODE
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
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TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXA
MPLE:THIS IS A
N IRL3103L
LO
T C
O
DE 1789
A
SSEMBLY
PA
RT NUM
BER
DA
TE C
O
DE
W
EEK 19
LINE C
LOT C
O
DE
YEA
R 7 = 1997
A
SSEMBLED ON W
W 19, 1997
IN THE A
SSEMBLY LINE "C
"LO
G
O
REC
TIFIER
INTERNA
TIO
NA
L
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
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Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 08/03
TO-220AB packages are not recommended for Surface Mount Application.
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
3
4
4
TRR
FEED DIRE CTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRE CTION
10.90 (.429)
10.70 (.421) 16.10 (. 634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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