16-Bit Registered Transceivers
CY74FCT16652T
CY74FCT162652T
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
SCCS061B - July 1994 - Revised September 2001
Copyright © 2001, Texas Instruments Incorporated
1CY74FCT162652T
Features
•I
off supports partial-power-down mode operation
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40˚C to +85˚C
•V
CC = 5V ± 10%
CY74FCT16652T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25˚C
CY74FCT162652T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25˚C
Functional Description
These 16-bit, high-speed, low-power, registered transceivers
that are organized as two independent 8-bit bus transceivers
with three-state D-type registers and control circuitry arranged
for multiplexed transmission of data directly from the input bus
orfromtheinternal storageregisters.OEABandOEBAcontrol
pinsare provided to controlthe transceiverfunctions.SAB and
SBA control pins are provided to select either real-time or
stored data transfer.
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by LOW-to-HIGH transitions at the
appropriate clock pins (CLKAB or CLKBA), regardless of the
select or enable control pins. When SAB and SBA are in the
real-time transfer mode, it is also possible to store data without
using the internal D-type flip-flops by simultaneously enabling
OEAB and OEBA. In this configuration, each output reinforces
its input. Thus, when all other data sources to the two sets of
bus lines are at high impedance, each set of bus lines will
remain at its last state.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device
when it is powered down.
The CY74FCT16652T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162652T has 24-mA balanced output drivers
with current-limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162652T is ideal for driving transmission lines.
TO7 OTHER CHANNELS
1OEAB
C
D
1A1
1OEBA
1CLKBA
1CLKAB
1SBA
B REG
C
D
AREG
1B1
1SAB
FCT16652-1
2OEAB
2SAB
2OEBA
2CLKBA
2CLKAB
2SBA
2B1
2A1
C
D
BREG
C
D
AREG
TO 7 OTHER CHANNELS FCT16652-2
Logic Block Diagrams
CY74FCT16652T
CY74FCT162652T
2
Pin Configuration
SSOP/TSSOP
Top View
FCT16652–1
GND
1OEAB
1CLKAB
1SAB
1A1
1A2
1CLKBA
1SBA
1B1
1OEBA
GND
GND
VCC
1A3
VCC
GND
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
GND
2A5
2A6
VCC
2A7
2A8
2SAB
2CLKAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
2OEAB
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OEBA
FCT16652-3
Pin Description
Name Description
A Data Register A Inputs
Data Register B Outputs
B Data Register B Inputs
Data Register A Outputs
CLKAB, CLKBA Clock Pulse Inputs
SAB, SBA Output Data Source Select Inputs
OEAB, OEBA Output Enable Inputs
CY74FCT16652T
CY74FCT162652T
3
Function Table[1]
Inputs Data I/O[2]
Operation or FunctionOEAB OEBA CLKAB CLKBA SAB SBA A B
L
LH
HH or L H or L X
XX
XInput Input Isolation
Store A and B Data
X
HH
HH or L X
X[3] X
XInput
Input Unspecified[2]
Output Store A, Hold B
Store A in Both Registers
L
LX
LH or L X
XX
X[3] Unspecified[2] Input
Input Hold A, Store B
Store B in both Registers
L
L
L
L
X
X
X
H or L
X
X
L
H
Output Input Real Time B Data to A Bus
Stored B Data to A Bus
H
H
H
H
X
H or L
X
X
L
H
X
X
Input Output Real Time A Data to B Bus
Stored A Data to B Bus
H L H or L H or L H H Output Output Stored A Data to B Bus and
Stored B Data to A Bus
Notes:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
=LOW-to-HIGH Transition
2. The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at
the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
3. Select control=L; clocks can occur simultaneously.
Select control=H; clocks must be staggered to load both registers.
CY74FCT16652T
CY74FCT162652T
4
Maximum Ratings[4]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .....................Com’l −55°C to +125°C
Ambient Temperature with
Power Applied.................................Com’l −55°C to +125°C
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)...........................−60 to +120 mA
Power Dissipation..........................................................1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Note:
4. Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
BUS BBUS A
OEAB
LOEBA
LCLKAB
XSAB
X
BUS BBUS A
OEAB
X
L
L
OEBA
H
X
H
CLKAB
X
SAB
X
X
X
SBA
X
X
X
BUS BBUS A
OEAB
HOEBA
LSAB
LSBA
X
BUS ABUS A
OEAB
HOEBA
LSAB
HSBA
H
Real-Time Transfer
BusB to BusA Real-Time Transfer
BusA to BusB
Storagefrom
A and/orB TransferStored Data
to A and/orB
CLKBA
XCLKAB
XCLKBA
X
SBA
L
CLKBA
XCLKAB
HorL CLKBA
HorL
Operating Range
Range Ambient
Temperature VCC
Industrial −40°C to +85°C 5V ± 10%
CY74FCT16652T
CY74FCT162652T
5
DC Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions[5] Min. Typ.[6] Max. Unit
VIH Input HIGH Voltage Logic HIGH Level 2.0 V
VIL Input LOW Voltage Logic LOW Level 0.8 V
VHInput Hysteresis 100 mV
VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 −1.2 V
IIH Input HIGH Current VCC=Max., VI=VCC ±1µA
IIL Input LOW Current VCC=Max., VI=GND ±1µA
IOZH High Impedance Output
Current
(Three-State Output pins)
VCC=Max., VOUT=2.7V ±1µA
IOZL High Impedance Output
Current
(Three-State Output pins)
VCC=Max., VOUT=0.5V ±1µA
IOS Short Circuit Current[8] VCC=Max., VOUT=GND −80 −140 −200 mA
IOOutput Drive Current[8] VCC=Max., VOUT=2.5V −50 −180 mA
IOFF Power-Off Disable VCC=0V, VOUT≤4.5V[7] ±1µA
Output Drive Characteristics for CY74FCT16652T
Parameter Description Test Conditions[5] Min. Typ.[6] Max. Unit
VOH Output HIGH Voltage VCC=Min., IOH=−3 mA 2.5 3.5 V
VCC=Min., IOH=−15 mA 2.4 3.5
VCC=Min., IOH=−32 mA 2.0 3.0
VOL Output LOW Voltage VCC=Min., IOL=64 mA 0.2 0.55 V
Output Drive Characteristics for CY74FCT162652T
Parameter Description Test Conditions[5] Min. Typ.[6] Max. Unit
IODL Output LOW Current[8] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA
IODH Output HIGH Current[8] VCC=5V, VIN=VIH or VIL, VOUT=1.5V −60 −115 −150 mA
VOH Output HIGH Voltage VCC=Min., IOH=−24 mA 2.4 3.3 V
VOL Output LOW Voltage VCC=Min., IOL=24 mA 0.3 0.55 V
Capacitance(TA = +25˚C, f = 1.0 MHz)
Parameter Description[10] Test Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6.0 pF
COUT Output Capacitance VOUT = 0V 5.5 8.0 pF
Notes:
5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
6. Typical values are at VCC=5.0V, +25°C ambient.
7. Tested at TA=+25°C.
8. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
9. Duration of the condition cannot exceed one second.
10. This parameter is measured at characterization but not tested.
CY74FCT16652T
CY74FCT162652T
6
Power Supply Characteristics
Param. Description Test Conditions[11] Min. Typ.[12] Max. Unit
ICC Quiescent Power Supply
Current VCC=Max. VIN<0.2V
VIN>VCC−0.2V — 5 500 µA
∆ICC Quiescent Power Supply
Current
TTL Inputs HIGH
VCC = Max. VIN=3.4V[13] — 0.5 1.5 mA
ICCD Dynamic Power Supply
Current[14] VCC=Max.
Outputs Open
OEAB=OEAB=GND
One Input Toggling
50% Duty Cycle
VIN=VCC or
VIN=GND — 75 120 µA/
MHz
ICTotal Power Supply Current[15] VCC=Max.
Outputs Open
fo=10 MHz(CLKBA)
50% Duty Cycle
OEAB=OEBA=GND
One-Bit Toggling
f1=5 MHz
50% Duty Cycle
VIN=VCC or
VIN=GND — 0.8 1.7 mA
VIN=3.4V or
VIN=GND — 1.3 3.2 mA
VCC=Max.
Outputs Open
fo=10 MHz (CLKBA)
50% Duty Cycle
OEAB=OEBA=GND
Sixteen Bits Toggling
f1=2.5 MHz
50% Duty Cycle
VIN=VCC or
VIN=GND — 3.8 6.5[16] mA
VIN=3.4V or
VIN=GND — 8.3 20.0[16] mA
Notes:
11. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
12. Typical values are at VCC=5.0V +25° ambient.
13. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
14. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
15. IC=I
QUIESCENT + IINPUTS + IDYNAMIC
IC=I
CC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH= Duty Cycle for TTL inputs HIGH
NT= Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
16. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
CY74FCT16652T
CY74FCT162652T
7
Switching Characteristics Over the Operating Range[17]
Parameter Description
CY74FCT16652AT
CY74FCT162652AT
UnitMin. Max. Fig. No.[18]
tPLH
tPHL Propagation Delay Bus to Bus 1.5 6.3 ns 1, 3
tPZH
tPHL Output Enable Time OEAB or OEBA to Bus 1.5 9.8 ns 1, 7, 8
tPHZ
tPLZ Output Disable Time OEAB or OEBA to Bus 1.5 6.3 ns 1, 7, 8
tPLH
tPHL Propagation Delay Clock to Bus 1.5 6.3 ns 1, 5
tPLH
tPHL Propagation Delay SBA or SAB to Bus 1.5 7.7 ns 1, 5
tSU Set-Up time HIGH or LOW Bus to Clock 2.0 — ns 4
tHHold Time HIGH or LOW Bus to Clock 1.5 — ns 4
tWClock Pulse Width HIGH or LOW 5.0 — ns 5
tSK(O) Output Skew[19] — 0.5 ns
Parameter Description
CY74FCT16652CT
CY74FCT162652CT
UnitMin. Max. Fig. No.[18]
tPLH
tPHL Propagation Delay
Bus to Bus 1.5 5.4 ns 1, 3
tPZH
tPHL Output Enable Time
OEAB or OEBA to Bus 1.5 7.8 ns 1, 7, 8
tPHZ
tPLZ Output Disable Time
OEAB or OEBA to Bus 1.5 6.3 ns 1, 7, 8
tPLH
tPHL Propagation Delay
Clock to Bus 1.5 5.7 ns 1, 5
tPLH
tPHL Propagation Delay
SBA or SAB to Bus 1.5 6.2 ns 1, 5
tSU Set-Up Time
HIGH or LOW
Bus to Clock
2.0 — ns 4
tHHold Time
HIGH or LOW
Bus to Clock
1.5 — ns 4
tWClock Pulse Width
HIGH or LOW 5.0 — ns 5
tSK(O) Output Skew[19] — 0.5 ns
Notes:
17. Minimum limits are specified, but not tested, on propagation delays.
18. See “Parameter Measurement Information” in the General Information section.
19. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design.
CY74FCT16652T
CY74FCT162652T
8
Ordering Information CY74FCT16652
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
5.4 CY74FCT16652CTPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial
6.3 CY74FCT16652ATPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial
Ordering Information CY74FCT162652
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
5.4 74FCT162652CTPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT162652CTPVC O56 56-Lead (300-Mil) SSOP
74FCT162652CTPVCT O56 56-Lead (300-Mil) SSOP
6.3 CY74FCT162652ATPVC O56 56-Lead (300-Mil) SSOP Industrial
74FCT162652ATPVCT O56 56-Lead (300-Mil) SSOP
CY74FCT16652T
CY74FCT162652T
9
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
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