AUIR0815S
1 www.irf.com © 2012 International Rectifier
January 08, 2013
Automotive Grade
BUFFER GATE DRIVER IC
Features
• High peak output cur rent > 10A
• Low propagation delay time
• Negative turn off bias can be applied to VEE usi ng an external supply
• Two output pins permi t to choose differe nt Ron and Roff resistors.
• Low supply current
• Undervoltage l ock out
• Continuous ‘on’ capability
• Suitable for high power inverter applications in conjun ct i on with an
external pre-driver
• Lead-Free, RoHS Compliant
• Automotive qualif i ed
Description
The AUIR0815 buff er gate driver family, in conjunction with a pre-driver
stage, is suited to drive a single half bri dge in power switching
applications. Thes e buffer gate drivers i ncorporate the abilit y to enter into
a low quiescent cur rent m ode.
Product Summary
VCC -GND
10V to 30V
GND -VEE
-1V to 20V
Vcc- VEE
10V to 30V
IO drive
> 10A
Package
8 Pin SOIC
Typical connection
AUIR0815S
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January 08, 2013
Qualification Information†
Qualification Level
Automotive
(per AEC-Q100
††
)
Comments: This family of ICs has passed an
Automotive qualification.
IR’s Industrial and
Consumer qualification level is granted by extension
of the higher Automotive level.
Moisture Sensitivity Level SOIC8N MSL2††† 260°C
(per IPC/JEDEC J-STD-020)
ESD
Machine Model
Class M1 (Pass +/-100 V)
(per AEC-Q100-003)
Human Body Model
Class H1B (+/-1000V)
(per AEC-Q100-002)
Charged Device Model
Class C4 (Pass +/-1000V)
(per AEC-Q100-011)
IC Latch-Up Test
Class II, Level A
(per AEC-Q100-004)
RoHS Compliant
Yes
†
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
††
Exceptions to AEC-Q100 requirements, if any, are noted in the qualification report.
†††
Higher MSL ratings may be available for the specific package type listed here. Please contact
your International Rectifier sales representative for further information.
AUIR0815S
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January 08, 2013
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which permanent damage to the device may occur. These are stress
ratings only, functional operation of the device at these or any other condition beyond those indicated in the “Recommended
Operating Condition” is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device
reliability. All voltage parameters are absolute voltages referenced to GND unless otherwise stated in the table. The thermal
resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min
Max
Units
GND to Vcc -37 0.3 V
VEE
To Vcc
-37
0.3
V
V
IN
Logic input vol tage to Vcc
- 40
0.3
V
VB Vbootstrap to OUTPUT -0.3 5.5 V
LPM LPM voltage to Vcc - 40 0.3(*) V
VOUTH
OUTH Output voltage
Vcc-37
VCC + 0.3
V
V
OUTL
OUTL output volt age
V
EE
-0.2
V
CC
+ 0.3
V
PD Package po we r di s sipation @ TA ≤ 25 °C — 1 W
RthJA Thermal resistance, junction to ambient — 80 °C/W
TJ
Junction temperature
-40
150
°C
T
S
Storage temperature
-55
150
°C
TL Lead temperatur e (soldering, 10 seconds) — 300 °C
(*) LPM is al lowed to settle to an higher voltage than specifi ed providing a current limi t ation of 10uA
Recommended Operating Condi t ions
For proper
operation the device should be used within the recommended conditions. All voltage parameters are
absolute voltages referenced to GND unless otherwise stated in t he table
Symbol
Definition
Min.
Max.
Units
VCC-GND Gate driver positive sup ply voltage 6(*) 30
V
GND- VEE
Gate driver negative supply voltage.
VEE is Shorted to GND in case of single supply operation
-1 15
Vcc- V
EE
Total suppl y voltage 10 30
VOUTH
OUTH Output voltage
Vcc-30
Vcc
VOUTH - VEE
Voltage difference between OUTH and VEE
-5
—
VIN
Logic input vol tage (IN and LPM)
Vcc-35
VCC
Cboot OUTPUT pull up boot capacitor 10 20 nF
Ron
OUTH series resi s tor to gate
1.5
20
Ohm
Roff OUTL series resist or to gate 1.5 20 Ohm
Cs Snubber capacitor between OUTH and VCC 10 24 nF
PWoff IN ‘lo w’ pulse width (**) 2 usec
(*)When 3V< V
CC-GND
< V
CC-GND_MIN
30 Ohm max resist ance pulls d own OUTL to V
EE
while OUTH is in HiZ. Guarant eed by
design.
(**) VCC-VEE<12V, see als o “Role of Cboot and Effect of Short ‘Off’ Pulses” chapter.
AUIR0815S
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January 08, 2013
Static Electrical Characteristics
VCC -GND= 15V; GND-VEE = 5V; 15nF conne cts CB to OUTH; 22nF connec ts Vcc to OUTH ;-40 °C < TA < 125 °C unl ess other wise
specified.
Symbol
Definition
Min
Typ
Max
Units
Test Conditions
VCCUV+
V
CC
-GND supply undervoltage
positive goi ng threshold
10.2 11.7 12.8
V
LPM=HIN=1=VCC VE=GND; OUTH pulled to
V
CC-2V with 100mA current lim itation
VCCUV-
V
CC
-GND supply undervoltage
negative going threshold
9.6 10.5 11.4
VCCUVH
V
CC
-GND supply undervoltage
lockout hysteresis
0.5 1.2 —
VBUV Vbootstrap undervoltage (* ) — 4 — V
IQGG
GND supply cu rrent
—
—
60
uA
IN=X; LPM=X
I
QEESW
V
EE
supply current , IN switching
2
4
10
mA
IN switches at 10k H z 50% duty cycle; LPM=1
IQEE0 VEE supply current , IN=0 — — 8.0 mA steady state with IN=0 and LPM=1
IQEE025 VEE supply current, IN=0 — — 6.5 mA steady state with IN=0 and LPM=1 , T=25 ^C
IQEE1
VEE supply current, IN=1
—
—
3
mA
steady state with IN=1 and LPM=1
I
QEELQ0
V
EE
supply current , LPM=0, IN=0
—
—
2
mA
steady state with IN=0 and LPM=0
IQEELQ1 VEE supply current, LPM=0, IN=1 — — 1.5 mA steady state with IN=1 and LPM=0
IQEEUV VEE supply current , VCC<VCCUV- — — 1.8 mA steady state with IN=X, LPM=X, VCC<VCCUV-
IQOUTL1 Current flowing into OUT L — — 1.5 uA
IN=1; LPM=1 ; OUTL-GND=15V; OUTH
disconnected
IQB
Current into CB pin
—
—
1
mA
IN=1; LPM= 1 ;CB -OUTH=5V
IQOUTH0 Current flowing out from OUTH — — 3.5 mA
steady state with IN=0 and LPM=1,
V(OUTH)=VEE, OUTL disconnected
IBOUTH Current f l owing out from CB,
bootstrap discharged
— 20 40 mA
steady state, C B shorted to OUTH, IN=0 and
LPM=1, V(OUTH)=VEE, OUTL disconnec ted
IOUTH+
OUTH high short circuit pulsed
current
10 — — A 10A current pulse with PW<10usec
IOUTL-
OUTL low short circuit pulsed current
10
—
—
A
(*)When CB-O UTH< VBUV the power nm os pulling up O UTH is turned off. The high lev el on OUTH is kept by a parallel PMOS (see
also block diagram).
Pins: IN, LPM
VCC -GND= 15V; GND-VEE = 5V; 15nF conne cts CB to OUTH; 22nF connec ts Vcc to OUTH; -40 °C < TA < 125 °C unless otherwise
specified.
Symbol
Definition
Min
Typ
Max
Units
Test Conditions
VINH vcc Logic "1" IN input voltage to VCC -3.5 -2.5 -1.0 V VCC-GND> VCCUV-
VINL vc c
Logic "0" IN input voltage to VCC
-5.5
-4.5
-3.5
VINhis Logic IN input hysteresis
1
2
3.3
VLPMH vcc Logic "1" LPM input voltage to VCC -3 -2.5 -1.4 V VCC-GND> VCCUV-
VLPML vcc
Logic "0" LPM input voltage to VCC
-3.8
-3
-2.5
VLPMhis Logic LPM input hysteres i s
0.25
-
1.8
IIN15
Current flowing out from IN when VCC-IN=15V
40
90
180
uA
IN=GND
I
LPM15
Current flowing out from LPM V
CC
-LPM=15V 10 25 50 uA LPM=GND
AUIR0815S
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January 08, 2013
Pins: OUTH,OUTL
VCC -GND= 15V; GND-VEE = 5V; 15nF conne cts CB to OUTH; 22nF connec ts Vcc to OUTH; -40 °C < TA < 125 °C unles s otherwise
specified.
Symbol
Definition
Min
Typ
Max
Units
Test Conditions
Rup_OUTH25 R ds on pull up transistor OUT H — 90 120
mOhm
10A current pulse with PW<10usec
TA=25^C
Rdw_OUTL25
Rdson pull down tr ansistor OUTL
—
180
240
Rup_OUTH
Rdson pull up transistor OU TH
—
—
180
10A current pulse with PW<10usec
Rdw_OUTL Rdson pull down tra ns i s tor OUTL — — 320
IPMOS OUTH Pull up current when bootstrap
cap is discharged 5 20 30 mA IN=1 LPM=1, CB-OUTH=2.5V,
OUTH pulled to V C C -1.5V
AC Electrical Character istics
V
CC
-GND= 15V; GND-V
EE
=5V; 15nF connects CB to OUTH; 22nF connects Vcc to OUTH ;Ron= 5 Ohm , Roff = 5 Ohm ,
CLOAD=100nF , -40 °C < TA < 125 °C unless otherwise spec ified.
Propagation is from INP U T at GND or VCC to 10% vol tage variation of output
RISE FALL TIME is delay from 10% to 90% output s wing
Symbol
Definition Min. Typ. Max. Units Test Conditions
ton
Turn on propagation delay IN-OUTH
—
250
400
ns
toff Turn off propagati on delay IN-OUTL — 250 350
t
r
Turn on rise ti m e OUTH
—
—
260
tf
Turn off fall time OUTL
—
—
150
trLQ Turn on rise t ime OUTH in Low Quiescent
Currrent Mode — — 1000 ns
V
EE
=GND, LPM=0, V
CC
rises
above VCCUV+; CLOAD=100nF
Ron= 5 Ohm, Roff = 5 Ohm
tfLQ Turn off fall time OUTL in Low Quiescent
Currrent Mode — — 1000 ns
V
EE
=GND, LPM=0, V
CC
falls
below VCCUV-+; CLOAD=100nF
Ron= 5 Ohm, Roff = 5 Ohm
PWON IN high pulse width (*) 500
—
—
ns
No C
LOAD
, -40 °C < T
A
< 125
°C
PWOFF
IN low pulse width (*) 500
—
—
ns
No C
LOAD
, -40 °C < T
A
< 125
°C
(*) IN pulse width lower tha n PWONMIN (PWOFFMIN) min can be filtered
AUIR0815S
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January 08, 2013
Block Diagram:
CB
V
EE
IN
LPM
V
CC
40 V 6 V
V
CC,UV
V
CC
V
CC
40 V 6 V
LPM mode
Normal mode I bias
0
1
V
CC
CB
40 V
40 V
VB
UV
OUTH
OUTL
V
CC
GND
CB
OUTH
OUTH
GND
GND
40 V
V
CC
40 V
V
CC
6 V
40 V
V
CC
OUTH
V
EE
Typical connection
Cb 12nF
Ron 5 Ohm To IGBT
gate
VCC
C1 2.2uF
C2 2.2uF
VEE
IN
LPM
Roff 5 Ohm
Cs 20nF
OUTH
OUTL
GND
Cg
It is recommended:
• to have a capacitance Cs connected between OUTH and VCC to limit dv/dt in OUTH node
(mandatory if Vcc-Vee>15V). See Recommended Operating Condition for Cs value.
• to avoid the condition with OUTH directly shorted to OUTL
• Use ceramic capacitor for C1 and C2 with value > 20* Cgate
AUIR0815S
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January 08, 2013
Application Inform ation And Addi t ional Details
Recommended maximum switching frequency when driving a capacitance C
with a 3 Ohm external resistor.
Cs=20nF is connected between OUTH and Vcc.
Vcc-VEE=24V. Truth Table
Vcc
IN
LPM
Status/Comment
VCC-GND_MIN
to V
CCUV
-
-
OUTL = V
EE
, OUTH in HiZ IGBT OFF ; Low Quiescent
Current Mode is active.
VCCUV to 30V
0
1
OUTL = V
EE
, OUTH in HiZ IGBT OF F;
VCCUV to 30V
1
1
OUTL in HiZ, OUT H = Vc c
IGBT ON;
V
CCUV
to 30V
0
0
OUTL = V
EE
, OUTH in HiZ IGBT OFF ; Low Quiescent
Current Mode is active
V
CCUV
to 30V
1
0
OUTL in HiZ, OUT H = Vc c IGBT ON; Low Quiescent Current
Mode is active
Role of Cboot and Effect of Short ‘Off’ Pulses
Cboot capacitance, connected between OUTH and CB acts as a bootstrap supplying the circuitry driving
the low rdson (Rup_OUTH ) pull-up nmos connected between Vcc and OUTH.
In the application, when IN is low, OUTH is tied to VEE and Cboot is charged to around 6V.
At IN rising the pullup nmos is turned on and it is able to provide a low impedence path between VCC
and OUTH.
Maintaining IN high, Cboot get discharged and therefore the pull-up nmos is turned off but the parallel
pmos (see Block diagram) remains on maintaining OUTH tied to VCC.
Cboot discharge rate is IQB/Cboot, typically it takes about 250 usec for a complete discharge.
In case Cboot get discharged, the subsequent off pulse width must be long enough to recharge Cboot
above the bootstrap under-voltage threshold VBUV. to allow the turn on of the pull-up nmos when IN rises
again. Short Off pulse width can lead to a situation, after the pulse, with too low IGBT Vge voltage, worst
case is for low values of VCC-VEE, that is just above VCCUV-. Even though it is allowed, at higher values of
Vcc-VEE, to reduce the off pulse width below PWoff min, it is suggested to keep the off pulse width
above 1usec in every working condition.
AUIR0815S
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January 08, 2013
Examples of system schematics with HVIC
This section shows how IR High Voltage IC (HVIC) gate drivers can be used to drive the AUIR0815.
All the examples refer to an inverter leg, showing the floating voltage sources Vcch and Veeh to supply
the high side AUIR0815 and Vccl and Veel to supply the low side AUIR0815.
All the examples show 7V floating voltage sources to provide a negative Vge to turn off each IGBT.
In case a negative Vge is not required these voltage sources can be replaced with a short circuit.
In case of three phase inverters, each of the high side AUIR0815 must have separated and isolated
voltage supplies.
Only one DC power supply can be shared for the low sides AUIR0815 supplies (to be connected between
AUIR0815 Vcc and GND pins) and the corresponding drivers supplies (to be connected between HVIC
Vcc and Vss=COM) pins.
Normally high di/dt occurs at low side switch turn on. This causes voltage spikes at low side IGBT
emitter node, because of the inductive impedance Zl, and the system must be robust to this.
A better immunity to the above transients can be obtained using one separate low side DC power supply
for each low side.
Example 1: using the AUIRS2181, high and low side driver with COM and no VSS pin.
AUIRS2181
V
B
HO
V
S
V
CC
HIN
COM
LIN
LO
AUIR0815
BUFFER
GNDV
EE
V
CC
OUTH
OUTL
IN
Vcch=15V
Veeh=7V
DC+
AUIR0815
BUFFER
GNDV
EE
V
CC
OUTH
OUTL
IN
Vccl=15V
Veel=7V DC-
Z
h
Zl
Example 1
AUIR0815S
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January 08, 2013
Example 2: using the AUIRS21814 (or the AUIRS2191), high and low side driver with COM pin and
VSS pin.
AUIRS21814
V
B
HO
V
S
V
CC
HIN
V
SS
LIN
LO
COM
AUIR0815
BUFFER
GNDV
EE
V
CC
OUTH
OUTL
IN
Vcch=15V
Veeh=7V
DC+
AUIR0815
BUFFER
GNDV
EE
V
CC
OUTH
OUTL
IN
Vccl=15V
Veel=7V DC-
(AUIRS2191)
Zh
Zl
Example 2
Example 3: using the AUIRS2117(8), single channel driver.
COM can be shorted to the Vs of the low side.
AUIRS2117(8)
V
B
HO
V
S
V
CC
IN
COM
AUIR0815
BUFFER
GNDV
EE
V
CC
OUTH
OUTL
IN
Vcch=15V
Veeh=7V
DC+
AUIRS2117(8)
V
B
HO
V
S
V
CC
IN
COM
AUIR0815
BUFFER
GNDV
EE
V
CC
OUTH
OUTL
IN
Vccl=15V
Veel=7V
Vcc=15V
DC-
Zh
Zl
Example 3
AUIR0815S
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January 08, 2013
AUIR0815S
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January 08, 2013
Lead Assignments
LPM
1
45
8V
CC
IN
GND
V
EE
OUTL
CB
OUTH
8 pin
SOIC
Lead Definitions
Symbol Description
VCC
Positive supply
IN
Logic input for OUT
LPM
Logic input, for Low Power Mode: LPM=0 ac tivates the Low Quiescent Current Mode
GND
Ground
OUTH
Power Output (pull up)
OUTL
Power Output (pull do wn)
CB
Boot capacitor
VEE
Negative supply pin (short to GND in case of s i ngle supply operation)
AUIR0815S
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January 08, 2013
Parameter Temperature Trends
Figures illustrated in this chapter provide information on the experimental performance of the IC. The line plotted in
each figure is generated from actual lab data. A large number of individual samples were tested at three
temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental curve. The line consists of three
data points (one data point at each of the tested temperatures) that have been connected together to illustrate the
understood trend. The individual data points on the curve were determined by calculating the averaged
experimental value of the parameter (for a given temperature).
AUIR0815S
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January 08, 2013
AUIR0815S
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January 08, 2013
AUIR0815S
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January 08, 2013
Case Outline
AUIR0815S
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January 08, 2013
Tape and Reel: SOIC8
CARRIER TAPE DIMENSION FOR 8SOICN
Code Min Max Min Max
A7.90 8.10 0.311 0.318
B 3.90 4.10 0.153 0.161
C11.70 12.30 0.46 0.484
D5.45 5.55 0.214 0.218
E6.30 6.50 0.248 0.255
F5.10 5.30 0.200 0.208
G1.50 n/a 0.059 n/a
H1.50 1.60 0.059 0.062
REEL DIMENSIONS FOR 8SOICN
Code Min Max Min Max
A329.60 330.25 12.976 13.001
B20.95 21.45 0.824 0.844
C12.80 13.20 0.503 0.519
D1.95 2.45 0.767 0.096
E98.00 102.00 3.858 4.015
Fn/a 18.40 n/a 0.724
G14.50 17.10 0.570 0.673
H12.40 14.40 0.488 0.566
Metric
Imperial
Metric
Imperial
E
F
A
C
D
G
A
B
H
NOTE : CONTROLLING
DIMENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
B
C
AUIR0815S
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January 08, 2013
Part Marking Information
A0815SD
IR logo
AYWW ?
Part number
Date code
Pin 1
Identifier
Lot Code
(Prod mode –
4 digit SPN code)
Assembly site code
Per SCOP 200-002
? XXXX
MARKING CODE
Lead Free Released
?
P
Ordering Informati on
Base Part Number Package Type Standard Pack Complete Part Number
Form Quantity
AUIR0815S
SOIC8 Tube/Bulk 95 AUIR0815S
Tape and Reel 2500 AUIR0815STR
AUIR0815S
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January 08, 2013
IMPORTANT NOTICE
Unless specifically designated for the automotive market, International Rectifier Corporation and its subsidiaries (IR)
reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products
and services at any time and to discontinue any product or services without notice. Part numbers designated with the
“AU” prefix follow automotive industry and / or customer specific requirements with regards to product discontinuance
and process change notification. All products are sold subject to IR’s terms and conditions of sale supplied at the time
of order acknowledgm ent.
IR warrants performance of its hardware products to the specifications applicable at the time of sale in accordance
with IR’s standard warranty. Testing and other quality control techniques are used to the extent IR deems necessary
to support this warranty. Except where mandated by government requirements, testing of all parameters of each
product is not necessarily performed.
IR assumes no liability for applications assistance or customer product design. Customers are responsible for their
products and applications using IR components. To minimize the risks with customer products and applications,
customers should provide adequate design and operating safeguards.
Reproduction of IR information in IR data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information
with alterations is an unfair and deceptive business practice. IR is not responsible or liable for such altered
documentation. Information of third parties may be subject t o addi tional restrictions.
Resale of IR products or serviced with statements different from or beyond the parameters stated by IR for that
product or service voids all express and any implied warranties for the associated IR product or service and is an
unfair and deceptive business practic e. IR is not responsibl e or liable for any such statemen ts.
IR products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or in other applications intended to support or sustain life, or in any other application in which the failure
of the IR product could create a situation where personal injury or death may occur. Should Buyer purchase or use IR
products for any such unintended or unauthorized application, Buyer shall indemnify and hold International Rectifier
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that IR was negligent regarding the
design or manuf act ure of the product.
Only products cert i fied as military grade by the Defense Logistics Agency ( DLA) of the US Department of Defense, are
designed and manufactured to meet DLA military specifications required by certain military, aerospace or other
applications. Buyers acknowledge and agree that any use of IR products not certified by DLA as military-grade, in
applications requiring military grade products, is solely at the Buyer’s own risk and that they are solely responsible for
compliance with all l egal and regulatory requir em ents in connection with such use.
IR products are neither designed nor intended for use in automotive applications or environments unless the specific
IR products are designated by IR as compliant with ISO/TS 16949 requirements and bear a part number including the
designation “AU”. Buyers acknowledge and agree that, if they use any non-designated products in automotive
applications, I R wil l not be responsible fo r any failure to meet such requirements.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
101 N. Sepulveda Blvd., El Segundo, Ca li fornia 90245
Tel: (310) 252-7105
AUIR0815S
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January 08, 2013
Revision History
Date
Comment
Dec. 2, 2009
-V
E
pin name changed into V
EE
; note1 modified; VEE-VCC 40V diode added in block diagram; current consumption table
parameters modified;
Feb 24, 2010
St. El. Ch: I
QOUTL1
parameter added; I
QOUTH0
max=2mA; I
QB
max=0.5mA; I
BOUTH
=60mA; I
QEE0
max=6mA; I
QEE1
max=3mA; I
QB
definition corrected; IQEESW value deleted;
Rec. Op. Con.:Cboot=10nF..20nF
AC El Char: Rise Fall time definition modified; Ssd= 100us typ
Feb 24b, 2010
Soft shutdown function removed (SSD
IN
/EN pin renamed EN); Rup dc max value deleted;
Typ connection; IQGG and IQEEEN0
Feb 25, 2010
OUTLCLAMP function added: changes in IQOUTL1, IQEE1; added Vcl, tcl1, tcl2
Apr 23, 2010
OUTLCLAMP function removed:
I
QOUTL1
=1uA typ, I
QEE1
=3mA typ; Vcl, tcl1 and tcl2 removed.
Change in EN pin functionality, now it is a low quiescent current mode input: front end page description; Abs Max Rat EN
Max note added;
Rec Op Cond: note added to specify pulldown 30 Ohm max for Vcc down to 3V.
Static el char: change in EN and IN thresholds and Rin.
IQEELQ and IQEEUV parameters introduced to specify consumption in Low Quiescent Current Mode (EN=1 or Vcc< VccUV-).
Truth Table modified to define VCCUV and low quiescent current mode conditions
Lead Definition modified to specify new EN function.
AC Electr Char: Tr and Tf specified for Low Quiescent Current Mode.
May 15, 2010
EN pin renamed into LPM.
Over temperature protection removed
Block diagram:
• Diode OUTL-Vcc added,
• IN and LPM input stage detailed drawing added.
Static El Char:
• IN and LPM input impedance spec modified
• note added to define VBUV.
• IQEELEN0 parameter removed because already covered by IQEELQ,
• IQGG Test Conditions changed from IN=0; LPM=1 into IN=X; LPM=X,
• LPM input thresholds lowered by 1V
• Rup renamed IPMOS.
Ac El Char:
• tEN parameter removed,
• max values added for ton, toff, tr, tf.
Rec. Op. Cond.:
GND-VEE min changed from 0V to -1V.
Jun 25, 2010
IBOUTH, IIN15, parameters change; added PWON and PWOFF parameters;
Mar 01, 2011
Update in test conditions for I
OUTH+,
I
OUTL,
Rup_OUTH, Rdw_OUTL. I
QEELQ
split into I
QEELQ0
and I
QEELQ1
IBOUTH redefined as current flowing out from CB (and not OUTH).
Truth Table corrected to show how LPM does not affect the functionality.
Update of heading for absolute maximum ratings
Update of chart with max f vs C.
Abs Max Rat: VOUTH = Vcc-37V min; VOUTL = VEE-0.2V min.
Rec Op Con: VOUTH = Vcc-30V min; VOUTH - VEE = -5V min;
Mar 02, 2011
Static and dynamic el. Char: parameter limits reviewed for matching full temp range. Values in blue are still older
datasheet version target value at T=25^C.
Added recommendation to avoid direct short between OUTH and OUTL.
Added preliminary parameter temperature trend paragraph.
IPMOS test condition corrected.
Jun 22, 2011
Vccuv thresholds modified; typ connection diagram: diode removed and snubber capacitance added; maxf vc C chart
updated taking into account Cs=20nF as snubber capacitance
Jun 27, 2011 Matched delay outputs front page note deleted; Rec Op Cond Vcc-GND max changed from 20V to 30V. AC El Cher:
tofftyp changed from 150ns to 250ns.Vccuv+ and Toff charts modified.
Aug 26, 2011
Added paragraph explaining role of Cboot.
Cs snubber capacitor added in Recommended Operating Conditions and in default test set-up.
VCCUV+: Min from 10.6V to 10.2V ; VCCUV-:Min from 9.7V to 9.6V ; VCCUVH:Min from 0.8V to 0.5V ;
IQEESW: Max from 8mA to 10mA ; IQOUTH0: Max from 3mA to 3.5mA ;
VINH vcc: Max from -1.5 V to -1V; VLPMH vc c: Max from -2.5 V to -1.5V; VLPMhis: Max from 1 V to 1.8V;
IPMOS: Min from 10mA to 5mA;
ton: Max from 380ns to 400ns; toff: Max from 300ns to 350ns; tr: Max from 150ns to 250ns;
Sep 6, 2011 Changes in typ connection recommandations; maxf vs C chart update;
VLPML vcc Min Change from -3.5Vto -3.8V. Temperature charts updated.
Sept. 7, 2011 Corrected part number on header; added RoHS compliant & Automotive qualified to front page; deleted preliminary
and added automotive grade on front page top header; added qual info page; added tape and reel info; added part
marking; added ordering info; added important notice
AUIR0815S
20 www.irf.com © 2012 International Rectifier
January 08, 2013
Oct 10, 2011
Rec Op Cond: Added description of Vouth and Vouth-Vee
Oct 17, 2011
Rec Op Cond: added “ Guaranteed by design” in note under the table;
Sta. El. Char. table: VCCUVH Min changed from 0.5V to 0.3V.
Pins: IN, LPM table: VINhis Max changed from 3V to 3.3V; VLPMH vcc Max changed from -1.5V to -1.4V
AC El Char table: tr Max changed from 250ns to 260ns
Oct 19, 2011 Sta. El. Char. table: VCCUVH Min changed back from 0.3V to 0.5V.
Oct 26, 2011
Revised MSL rating to MSL-2
Jan 20th, 2012
Application section added: Examples of system with HVIC
Jan 24th, 2012
“Examples of system schematics with HVIC” modified; block diagram updated.
October 24th 2012 Added Effect of Short ‘Off’ Pulses part in application info and minimum PWoff in recommended op cond.
Front page typ connection, snubber cap added.
Examples of system schematics with HVIC: added pullup resistors at IN in Ex1 and Ex2
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AUIR0815STR