16-Bit, 65 MSPS A/D Converter
AD10677
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
65 MSPS sample rate
80 dBFS signal-to-noise ratio
Transformer-coupled analog input
Single PECL clock source
Digital outputs
True binary format
3.3 V and 5 V CMOS-compatible
APPLICATIONS
Low signature radar
Medical imaging
Communications instrumentation
Instrumentation
Antenna array processing
GENERAL DESCRIPTION
The AD10677 is a 16-bit, high performance, analog-to-digital
converter (ADC) for applications that demand increased SNR
levels. Exceptional noise performance and a typical signal-to-
noise ratio of 80 dBFS are obtained by digitally postprocessing
the outputs of four ADCs. A single analog input and PECL
sampling clock and 3.3 V and 5 V power supplies are required.
The AD10677 is assembled using a 0.062-inch laminate board
with three sets of connector interface pads to accommodate
analog and digital isolation. Analog Devices recommends
using the FSI-110-03-G-D-AD-K-TR connector from Samtec.
The overall card fits a 2.2 inch × 2.8 inch PCB specified from
0°C to 70°C.
FUNCTIONAL BLOCK DIAGRAM
03208-B-001
AD10677
ANALOG
POWER CLOCK
DISTRIBUTION CIRCUIT
DIGITAL POWERENCODE ENCODE
AGND
ADC
ADC
ADC
ADC
AGND DGND DGND
+3.3VE
+3.3V
+5VA
AIN
AIN
DOUT0
DOUT15
14
14
14
14
DIGITAL
POST-
PROCES-
SING
OUTPUT
DATA
BITS
Figure 1.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 65 MSPS.
2. Input signal conditioning with optimized noise
performance.
3. Fully tested and guaranteed performance.
AD10677
Rev. D | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Digital Specifications ................................................................... 3
AC Specifications.......................................................................... 4
Switching Specifications .............................................................. 4
Absolute Maximum Ratings............................................................ 5
Explanation of Test Levels........................................................... 5
Operating Range........................................................................... 5
ESD Caution.................................................................................. 5
Test Circuits ....................................................................................... 6
Pin Configurations and Function Descriptions............................7
Typical Performance Characteristics ..............................................9
Ter m in olog y .................................................................................... 11
Theory of Operation ...................................................................... 12
Thermal Considerations............................................................ 12
Input Stage................................................................................... 12
Encoding the AD10677 ............................................................. 12
Output Loading .......................................................................... 12
Analog and Digital Power Supplies.......................................... 12
Analog and Digital Grounding................................................. 13
Other Notes................................................................................. 13
Evaluation Board ........................................................................ 13
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
5/06—Rev. C to Rev. D
Changes to Figure 9.......................................................................... 8
Edits to Table 8................................................................................ 13
Edits to Figure 19............................................................................ 14
3/05—Rev. B to Rev. C
Changes to Figure 1.......................................................................... 1
Changes to Figure 2 and Figure 3................................................... 6
Added Figure 6 to Figure 8.............................................................. 7
Reformatted Table 7 ......................................................................... 7
Changes to Figure 9.......................................................................... 8
Changes to Figure 10 to Figure 13.................................................. 9
Reformatted Theory of Operation Section ................................. 12
Changes to Figure 19...................................................................... 14
12/03—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Table 1 and Footnotes...................................................3
Changes to Theory of Operation.................................................. 12
Changes to Ordering Guide.......................................................... 20
8/03—Rev. 0 to Rev. A
Changes to Specifications..................................................................2
Changes to Table 1..............................................................................4
Changes to Definition of Specifications....................................... 10
Updated Outline Dimensions........................................................ 18
11/02—Revision 0: Initial Version
AD10677
Rev. D | Page 3 of 20
SPECIFICATIONS
DC SPECIFICATIONS
AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V, TA = 25°C, differential encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted.
Table 1.
Parameter Test Level Min Typ Max Unit
RESOLUTION 16 Bits
Offset Error I –0.30 +0.12 +0.30 %FS
Gain Error I –7 +7 %FS
Differential Nonlinearity (DNL) V ±0.7 LSB
Integral Nonlinearity (INL) V ±4 LSB
TEMPERATURE DRIFT
Offset Error V 13 ppm/ºC
Gain Error V 200 ppm/ºC
POWER SUPPLY REJECTION RATIO (PSRR) V 60 dB
ANALOG INPUTS (AIN, AIN)1
Differential Input Voltage Range V 2.15 V p-p
Differential Input Resistance V 50 Ω
Differential Input Capacitance V 2.5 nF
Input Bandwidth IV 0.40 210 MHz
VSWR2V 1.04:1 Ratio
POWER SUPPLY3
Supply Current
IAVCC (AVCC = 5.0 V) I 0.95 1.05 A
IEVCC (EVCC = 3.3 V) I 0.15 0.2 A
IVDD (VDD = 3.3 V) I 0.49 0.625 A
Total Power Dissipation4I 6.86 7.5 W
1 Measurement includes the recommended interface connector.
2 Input VSWR, see Figure 15.
3 Supply voltages should remain stable within 65% for normal operation. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V.
4 Power dissipation measured with encode at rated speed and −1 dBFS analog input at 10 MHz.
DIGITAL SPECIFICATIONS
AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V, TA = 25°C, differential encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted.
Table 2.
Parameter Test Level Min Typ Max Unit
ENCODE INPUTS (ENCODE, ENCODE)
Differential Input Voltage Range IV 0.4 V p-p
Differential Input Resistance V 100 Ω
Differential Input Capacitance V 160 pF
LOGIC OUTPUTS (D15 to D0)
Logic Compatibility CMOS
Logic 1 Voltage ILOAD ≤ 100 mA IV 0.9 × VDD V
Logic 0 Voltage ILOAD ≤ 100 mA IV 0.4 V
Output Coding True binary
Series Output Resistance per Bit 120 Ω
AD10677
Rev. D | Page 4 of 20
AC SPECIFICATIONS
AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V, TA = 25°C, differential encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted.
Table 3.
Parameter Test Level Min Typ Max Unit
SNR1
Analog Input 2.5 MHz I 77.5 80 dBFS
@ –1 dBFS 10 MHz I 77.5 80 dBFS
30 MHz I 76.5 78.5 dBFS
SINAD2
Analog Input 2.5 MHz I 77.2 79 dBFS
@ –1 dBFS 10 MHz I 77.2 79 dBFS
30 MHz I 74.5 77 dBFS
SFDR3
Analog Input 2.5 MHz I 84 92 dBFS
@ –1 dBFS 10 MHz I 84 92 dBFS
30 MHz I 79.5 84 dBFS
TWO-TONE4
Analog Input
@ –7 dBFS—IMD
f1 = 10 MHz, f2 = 12 MHz V 96 dBFS
1 Analog input signal power at –1 dBFS; signal-to-noise (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR is reported
in dBFS, related back to converter full scale.
2 Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS. SINAD is
reported in dBFS, related back to converter full scale.
3 Analog input signal at –1 dBFS; SFDR is the ratio of converter full scale to the worst spur.
4 Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third-order intermodulation product.
SWITCHING SPECIFICATIONS
AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V, TA = 25°C, differential encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted.
Table 4.
Parameter Test Level Min Typ Max Unit
MAXIMUM CONVERSION RATE I 65 MSPS
MINIMUM CONVERSION RATE IV 15 MSPS
DUTY CYCLE IV 40 60 %
ENCODE INPUT PARAMETERS
Encode Period @ 65 MSPS, tENC V 15.4 ns
Encode Pulse Width High @ 65 MSPS, tENCH V 7.7 ns
Encode Pulse Width Low @ 65 MSPS, tENCL V 7.7 ns
ENCODE/DATA (D15:D0)
Propagation Delay, tPDH 6.7 ns
Valid Time, tPDL 7.3 ns
APERTURE DELAY, tAV 480 ps
APERTURE UNCERTAINTY (JITTER), tJV 500 fs rms
PIPELINE DELAYS V 9 Cycles
AD10677
Rev. D | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVCC to AGND 0 V to 7 V
EVCC to AGND 0 V to 6 V
VDD to DGND –0.5 V to +3.8 V
Analog Input Voltage 0 V to AVCC
Analog Input Current 25 mA
Encode Input Voltage 0 V to 5 V
Digital Output Voltage –0.5 V to VDD
Maximum Junction Temperature 150°C
Storage Temperature Range Ambient –65°C to +150°C
Maximum Operating Temperature Ambient 92°C
Table 6. Output Coding (True Binary)
Code AIN (V) Digital Output
65535 +1.1 1111 1111 1111 1111
. .
. .
. .
32768 0 1000 0000 0000 0000
32767 –0.000034 0111 1111 1111 1111
. .
. .
. .
0 –1.1 0000 0000 0000 0000
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range; 100%
production tested at temperature extremes for military devices.
OPERATING RANGE
Operating ambient temperature range: 0°C to 70°C. See the
Thermal Considerations section.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD10677
Rev. D | Page 6 of 20
TEST CIRCUITS
ANALOG INPUT
ENCODE, ENCODE
DATA BITS, D[15:0]
t
0
N N+1 N+2 N+3 N+4 N+5 N+6
N N+1 N+2 N+3 N+4 N+5 N+6
N–9 N–7N–8 N–6 N–5 N–4
t
ENC
t
ENCL
t
ENCH
t
PDH
t
PDL
03208-B-002
Figure 2. Timing Diagram
200Ω500ΩV
REF
V
CL
V
CL
V
CH
V
CH
AV
CC
AV
CC
BUF
BUF
BUF
T/H
T/H
25Ω
1:1 500Ω
25Ω
×4
500Ω
AIN
AIN
03208-B-003
Figure 3. Analog Input Stage
100Ω
EV
CC
37.5kΩ
PECL
DRIVER
ENC
ENC
03208-B-004
Figure 4. Equivalent Encode Input
D
0
–D
15
MACROCELL
LOGIC
120Ω
P
N
V
DD
V
DD
03208-B-005
Figure 5. Digital Output Stage
AD10677
Rev. D | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
03208-B-023
AD10677
TOP VIEW
(Not to Scale)
NC = NO CONNECT
DGND
1
DGND
2
D
OUT
15
3
NC
4
D
OUT
14
5
DGND
6
D
OUT
13
7
NC
8
D
OUT
12
9
DGND
10
D
OUT
11
11
NC
12
D
OUT
10
13
DGND
14
D
OUT
9
15
NC
16
D
OUT
8
17
DGND
18
DGND
19
NC
20
Figure 6. Pin Configuration P1
(See Figure 9)
03208-B-024
AD10677
TOP VIEW
(Not to Scale)
DGND 1DGND2
+3.3VD 3DOUT04
+3.3VD 5DOUT1
6
+3.3VD 7DOUT2
8
DGND 9DOUT310
DGND 11 DOUT412
DGND 13 DOUT514
DGND 15 DOUT616
+3.3VD 17 DOUT7
18
+3.3VD 19 DGND
20
Figure 7. Pin Configuration P2
(See Figure 9)
03208-B-025
AD10677
TOP VIEW
(Not to Scale)
+3.3VE
1
+5.0VA
2
+3.3VE
3
+5.0VA
4
AGND
5
+5.0VA
6
AGND
7
+5.0VA
8
AGND
9
AGND
10
AGND
11
AIN
12
AGND
13
AIN
14
ENCODE
15
AGND
16
ENCODE
17
AGND
18
AGND
19
AGND
20
Figure 8. Pin Configuration P3
(See Figure 9)
Table 7. Pin Function Descriptions
P1 Pin No.1P2 Pin No.2P3 Pin No.3Mnemonic Description
1, 2, 6, 10, 14, 18, 19 1, 2, 9, 11, 13, 15, 20 N/A DGND Digital Ground.
3, 5, 7, 9, 11, 13, 15, 17 4, 6, 8, 10, 12, 14, 16, 18 N/A DOUTx Data Bit Output.
N/A 3, 5, 7, 17, 19 N/A +3.3VD Digital Voltage (VDD).
4, 8, 12, 16, 20 N/A N/A NC No Connection.
N/A N/A 1, 3 +3.3VE Encode Voltage (EVCC).
N/A N/A 2, 4, 6, 8 +5.0VA Analog Voltage (AVCC).
N/A N/A 5, 7, 9 to 11, 13, 16, 18 to 20 AGND Analog Ground.
N/A N/A 12 AIN Analog Input.
N/A N/A 14 AIN Analog Input (Complement).
N/A N/A 15 ENCODE Encode Input.
N/A N/A 17 ENCODE Encode Input (Complement).
1 Equivalent pin configuration in Figure 19 is J12.
2 Equivalent pin configuration in Figure 19 is J11.
3 Equivalent pin configuration in Figure 19 is J13.
AD10677
Rev. D | Page 8 of 20
0.960
P3
P1
P2
MH4
MH3
MH2
MH1
2.148
1.223
0.466
0.888
1.693
0.805
0.900
0.526
0.7570.955
0.925
0.433
INT E RFACE NOT E S
SUGGESTED I NTERFACE MANUFACTURER: SAMT E C
INT E RFACE PART NUMBERS FO R P1- P 3 : FSI-110-03-G-D-AD-K-TR (20- P IN)
HOL E S 1–4 ACCOMMOD ATE 2-56 THREADED HARDWARE. USE FO UR 2- 56 NUTS F OR SECURING
THEPART TO INTERFACE PCB.
MANUFACTURER: BUILDING FASTENE RS
PART NUM BE R: HNS S 256
DIGI KEY #: H723-ND
ALL METAL HARDWARE TO BE TORQ UED TO 1.0 I NCH- P OUND.
CARE MUST BE TAKEN WHEN TIGHTENI NG HARDWARE ADJACENT TO SURFACE-MOUNTE D
COM P ONENT S TO AVOID DAM AGE.
03208-D-006
TOL E RANCE S: 0.xxx = ±5 mils
Figure 9. Interface PCB Assembly, Top View
(Dimensions Shown in Inches)
AD10677
Rev. D | Page 9 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
0 2.5 5.0 7.5 10.0 15.0 25.012.5 17.5 20.0 22.5 27.5 30.0 32.5
–130
–120
–100
–60
–40
–20
–10
0
–80
–110
–70
–50
–30
–90
FREQUENCY (MHz)
dBFS
ENCODE = 65MSPS
AIN = 2.3MHz
SNR = 80.1dBFS
SFDR = 96.16dBFS
03208-B-007
Figure 10. Single-Tone at 2.3 MHz
0 2.5 5.0 7.5 10.0 15.0 25.012.5 17.5 20.0 22.5 27.5 30.0 32.5
–130
–120
–100
–60
–40
–20
–10
0
–80
–110
–70
–50
–30
–90
FREQUENCY (MHz)
dBFS
ENCODE = 65MSPS
AIN = 10.1MHz
SNR = 80.22dBFS
SFDR = 94.3dBFS
03208-B-008
Figure 11. Single-Tone at 10.1 MHz
0 2.5 5.0 7.5 10.0 15.0 25.012.5 17.5 20.0 22.5 27.5 30.0 32.5
–130
–120
–100
–60
–40
–20
–10
0
–80
–110
–70
–50
–30
–90
FREQUENCY (MHz)
dBFS
ENCODE = 65MSPS
AIN = 31.7MHz
SNR = 78.95dBFS
SFDR = 85.5dBFS
03208-B-009
Figure 12. Single-Tone at 31.7 MHz
0 2.5 5.0 7.5 10.0 15.0 25.012.5 17.5 20.0 22.5 27.5 30.0 32.5
–130
–120
–100
–60
–40
–20
–10
0
–80
–110
–70
–50
–30
–90
FREQUENCY (MHz)
dBFS
03208-B-010
ENCODE = 65MSPS
AIN = 10.1MHz AND 12.1MHz
IMD = 97.03dBFS
Figure 13. Two-Tone @ 10.1 MHz and 12.1 MHz
FREQUENCY (MHz)
dBFS
–2.0
–1.8
–1.6
–1.4
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2
0
1.0 10.9 20.8 30.7 40.6 50.5 60.4 70.3 80.2 90.1 100.0
AIN = –1dBFS
03208-B-011
Figure 14. Gain Flatness
FREQUENCY (MHz)
VSWR
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
0.1 1.0 10.0 100.0 1000.0
03208-B-012
Figure 15. Analog Input VSWR
AD10677
Rev. D | Page 10 of 20
FUNDAMENTAL LEVEL (dBFS)
dBc
–80 –70 –60 –50 –40 –30 –20 –10 0
0
10
20
30
40
50
60
70
80
90
100
SFDR 30MHz SNR 30MHz
SFDR 10MHz
SNR 10MHz
SFDR 2.5MHz
SNR 2.5MHz
03208-B-013
Figure 16. SFDR and SNR vs. Analog Input Level
ANALOG INPUT FREQUENCY (MHz)
dBc
76
78
80
82
84
86
88
90
92
94
96
SNR
SFDR
0 1015202530355
03208-B-014
Figure 17. SFDR and SNR vs. Analog Input Frequency
AD10677
Rev. D | Page 11 of 20
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point on the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity (DNL)
The deviation of any code from an ideal 1 LSB step.
Encode Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time the encode
pulse should be left in a Logic 1 state to achieve rated perform-
ance; pulse width low is the minimum time the encode pulse
should be left in a low state. At a given clock rate, these speci-
fications define an acceptable encode duty cycle.
Integral Nonlinearity (INL)
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB or less below the
guaranteed limit.
Output Propagation Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the time when all output data bits
are within valid logic levels.
Power Supply Rejection Ratio (PSRR)
The ratio of a change in output offset voltage to a change in
power supply voltage.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including the first five harmonics and dc. Can be
reported in dBc (that is, degrades as signal level is lowered) or
in dBFS (always related back to converter full scale).
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full scale)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc. Can be reported in dBc
(that is, degrades as the signal level is lowered) or in dBFS
(always related back to converter full scale).
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be an harmonic. SFDR can be reported in
dBc (that is, degrades as signal level is lowered) or in dBFS
(always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection (IMD)
The ratio of the rms value of an input tone to the rms value of the
worst third-order intermodulation product; reported in dBc.
Voltage Standing-Wave Ratio (VSWR)
The ratio of the amplitude of the elective field at a voltage
maximum to that at an adjacent voltage minimum.
AD10677
Rev. D | Page 12 of 20
THEORY OF OPERATION
The AD10677 uses four parallel high speed ADCs in a
correlation technique to improve the dynamic range of the
ADCs. The technique sums the parallel outputs of the four
converters to reduce the uncorrelated noise introduced by the
individual converters. Signals processed through the high speed
adder are correlated and summed coherently. Noise is not
correlated and sums on an rms basis.
The four high speed ADCs use a three-stage subrange architec-
ture. The AD10677 provides complementary analog input pins,
AIN and AIN. Each analog input is centered around 2.4 V and
should swing ±0.55 V around the reference. Because AIN and
AIN are 180 degrees out of phase, the differential analog input
signal is 2.15 V p-p.
The analog input meets a 50 Ω input impedance for easy
interface to commercial cables, filters, drivers, and so on.
The AD10677 encode inputs are ac-coupled to a PECL
differential receiver/driver. The output of the receiver/driver
provides a clock source for a 1:5 PECL clock driver and a
PECL-to-TTL translator. The 1:5 PECL clock driver provides
the differential encode signal for each of the four high speed
ADCs. The PECL-to-TTL translator provides a clock source for
the complex programmable logic device (CPLD).
The digital outputs from the four ADCs drive 120 Ω series
output terminators and are applied to the CPLD for post-
processing. The digital outputs are added together in the
complex programmable logic device through a ripple-carry
adder, which provides the 16-bit data output. The AD10677
provides valid data following nine pipeline delays. The result
is a 16-bit parallel digital CMOS-compatible word coded as
true binary.
THERMAL CONSIDERATIONS
Due to the high power nature of the part, it is critical that the
following thermal conditions be met for the part to perform to
data sheet specifications. This also ensures that the maximum
junction temperature (150°C) is not exceeded.
• Operation temperature (TA) must be within 0°C to 70°C.
• All mounting standoffs should be fastened to the interface
PCB assembly with 2-56 nuts. This ensures good thermal
paths as well as excellent ground points.
• The unit rises to ~72°C (TC) on the heat sink in still air
(0 linear feet per minute (LFM)). The minimum recom-
mended air flow is 100 linear feet per minute (LFM) in
either direction across the heat sink (see Figure 18).
03208-B-016
AIR FLOW (AMBIENT) (LFM) 3000 100 15050 200 250
TEMPERATURE (CASE) (°C)
30
75
70
65
60
55
50
45
40
35
Figure 18. Temperature (Case) vs. Air Flow (Ambient)
INPUT STAGE
The user is provided with a single-to-differential transformer-
coupled input. The input impedance is 50 Ω and requires a
2.15 V p-p input level to achieve full scale.
ENCODING THE AD10677
The AD10677 encode signal must be a high quality, low phase
noise source to prevent performance degradation. The clock
input must be treated as an analog input signal because aperture
jitter can affect dynamic performance. For optimum perform-
ance, the AD10677 must be clocked differentially.
OUTPUT LOADING
Take care when designing the data receivers for the AD10677.
The complex programmable logic device’s 16-bit outputs drive
120 Ω series resistors to limit the amount of current that can
flow into the output stage. To minimize capacitive loading,
there should be only one gate on each of the output pins. A
typical CMOS gate combined with the PCB trace has a load of
approximately 10 pF. Note that extra capacitive loading
increases output timing and invalidates timing specifications.
Digital output timing is guaranteed with 10 pF.
ANALOG AND DIGITAL POWER SUPPLIES
Care must be taken when selecting a power source. Linear
supplies are recommended. Switching supplies tend to have
radiated components that can be coupled into the ADCs. The
AD10677 features separate analog and digital supply and
ground currents, helping to minimize digital corruption of
sensitive analog signals.
The +3.3VE supply provides power to the clock distribution
circuit. The +3.3VD supply provides power to the digital output
section of the ADCs, the PECL-to-TTL translator, and the
CPLD. Separate +3.3VE and +3.3VD supplies are used to
prevent modulation of the clock signal with digital noise.
AD10677
Rev. D | Page 13 of 20
The +5.0VA supply provides power to the analog sections of the
ADCs. Decoupling capacitors are strategically placed throughout
the circuit to provide low impedance noise shunts to ground.
The +5.0VA supply (analog power) should be decoupled to
analog ground (AGND) and +3.3VD (digital power) should be
decoupled to digital ground (DGND). The +3.3VE supply
(analog power) should be decoupled to AGND. The evaluation
board schematic (Figure 19) and layout data (Figure 20 and
Figure 21) show a PCB implementation of the AD10677. Table 8
shows the PCB bill of materials.
ANALOG AND DIGITAL GROUNDING
Although the AD10677 provides separate analog and digital
ground pins, the device should be treated as an analog
component. Proper grounding is essential in high speed,
high resolution systems. Multilayer printed circuit boards are
recommended to provide optimal grounding and power
distribution. The use of power and ground planes provides
distinct advantages. Power and ground planes minimize
the loop area encompassed by a signal and its return path,
minimize the impedance associated with power and ground
paths, and provide a distributed capacitor formed by the
power plane, printed circuit board material, and ground plane.
The AD10677 has four metal standoffs (see Figure 9). MH2 is
located in the center of the unit, and MH1 is located directly
below analog header P3. Both of these standoffs are tied to
analog ground and should be connected accordingly on the
next level assembly for best performance. The two standoffs
located near P1 and P2 (MH3 and MH4) are tied to digital
ground and should be connected accordingly on the next
level assembly.
OTHER NOTES
The circuit is configured on a 2.2 inch × 2.8 inch laminate
board with three sets of connector interface pads. The pads
are configured to provide easy keying for the user. The pads
are made for low profile applications and have a total height
of 0.12 inches after mating. The part numbers for the header
mates are provided in Figure 9. All pins of the analog and digital
sections are described in the Pin Configurations and Function
Descriptions section.
EVALUATION BOARD
The AD10677 evaluation board provides an easy way to test the
16-bit, 65 MSPS ADC. The board requires a clock source, an
analog input signal, two 3.3 V power supplies, and a 5 V power
supply. The clock source is buffered on the board to provide a
latch, a data ready signal, and the clock for the AD10677. The
ADC digital outputs are latched on board by a 74LCX16374.
The digital outputs and output clock are available on a 40-pin
connector, J1. Power is supplied to the board via uninsulated
metal banana jacks.
The analog input is connected via an SMA connector, AIN. The
analog input section provides a single-ended input option
or a differential input option. The board is shipped in a single-
ended analog input option. Removing a ground tie at E17
converts the circuit to a differential analog input configuration.
Table 8. PCB Bill of Materials
Item Quantity Reference Designator Description
1 1 J1 Connector, 40-position header, male straight
2 1 U1 IC, LV 16-bit, D-type flip-flop with 5 V tolerant IO
3 3 L1 to L3 Common-mode surface-mount ferrite bead 20 Ω
4 3 J11 to J13 Connector, 1 mm single-element interface
5 6 P1, P2, P8 to P10, P12 Uninsulated banana jack, all metal
6 2 U5, U6 IC, 3.3 V/5 V ECL differential receiver/driver
7 1 U7 IC, 3.3 V dual differential LVPECL-to-LVTTL translator
8 1 R24 RES 0.0 Ω 1/10 W 5% 0805 SMD
9 19 R0 to R16, R20, R23 RES 51.1 Ω 1/10 W 1% 0805 SMD
10 1 R17 RES 18.2 kΩ 1/10 W 1% 0805 SMD
11 4 R18, R19, R21, R22 RES 100 Ω 1/10 W 1% 0805 SMD
12 17 C1, C10 to C13, C16 to C18, C23 to C26, C28 to C32 CAP 0.1 μF 16 V ceramic X7R 0805
13 6 C8, C9, C14, C15, C27, C33 CAP 10 μF 10 V ceramic Y5V 1206
14 4 J2, J3, J5, J6 Connector, SMA jack 200 mil STR gold
15 1 A1 Assembly, AD10677BWS
16 1 AD106xx Evaluation Board GS04483 (PCB)
AD10677
Rev. D | Page 14 of 20
J6
ENCODE
J5
ENCODE
MC10EL16D
U5
MC10EL16D MC100ELT23D
74LCX16374MTD
40-PIN
HMS
SINGLE-ENDED
INPUT OPTION
AD10677 PART OUTLINE
BYPASS CAPACITORSPOWER CONNECTIONS POWER CONNECTIONS
OPTIONAL EVALUATION BOARD GROUND TIES
DIFFERENTIAL
INPUT OPTION
J2
ANALOG
INPUT
LATCH
LATCH
AGND
AGND
AGND
AGND
AGND AGND AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
L1
P10
P1
P9
P2
L2
AGND
AGND
DGND
DGND
DGND
DGND DGND
DGND
DGND
DGND DGND DGND DGND
DGND
DGND
DGND
AGND
AGND
MH4
MH3
MH1–MH4 = DUT MOUNTING HOLES
E17
E2 E6 E10 E12 E18 E19 E21 E4 E3 E20 E22 E13 E1 E5 E9 E11
E7 E8
BUFMEM
BUFMEM
DRY
DRY
U6 U7
U1
J1
R30
DNI
R30
DNI
R25
DNI
R27
DNI
R28
DNI R31
DNI
HEADER 732mm
SI-110-03-G-D-AD-TR
FSI-110-03-G-D-AD-TR
FSI-110-03-G-D-AD-TR
R29
DNI
R22
100Ω
R23
51.1Ω
R0 51.1Ω
VCC
VCC
VCC
VCC
O15
O14
O13
O12
O11
O10
O9
O8
25
24
26
27
29
30
32
33
35
36
48
1
37
38
40
41
43
44
46
47
28
34
39
45
7
18
23
22
20
19
17
16
14
13
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
2
4
6
8
10
12
14
1
3
5
7
9
11
13
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
12
14
16
18
20
1
3
2
4
1
3
2
4
1
3
5
7
9
11
13
15
17
19
1
3
5
7
8
7
6
5
V
CC
Q
Q
VEE
1
2
3
4
NC
D
D
VBB
8
7
6
5
V
CC
Q
Q
VEE
1
2
3
4
NC
D
D
VBB
8
7
6
5
V
CC
Q0
Q1
GND
1
2
3
4
D0
D1
D1
9
11
13
15
17
19
19
17
15
13
11
9
7
5
3
1
19
17
15
13
11
9
7
5
3
1
20
18
16
14
12
10
8
6
4
2
20
18
16
14
12
10
8
6
4
2
19
17
15
13
11
9
7
5
3
1
19
17
15
13
11
9
7
5
3
1
20
18
16
14
12
10
8
6
4
2
20
18
16
14
12
10
8
6
4
2
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
42
31
12
11
9
8
6
5
3
2
21
15
10
4
O7
O6
O5
O4
O3
O2
O1
O0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0 GND
GND
GND
GND
GND
GND
GND
GND
OE2
OE1
CP2
CP1
R1 51.1Ω
R2 51.1Ω
R3 51.1Ω
R4 51.1Ω
R5 51.1Ω
R6 51.1Ω
R7 51.1Ω
R8 51.1Ω
R9 51.1Ω
R10 51.1Ω
R11 51.1Ω
R12 51.1Ω
R13 51.1Ω
R14 51.1Ω
R15 51.1Ω
C10
0.1μF
16V
C13
0.1μF
16V
C12
0.1μF
16V
C11
0.1μF
16V
C15
10μF
10V
C32
0.1μF
16V
C30
0.1μF
16V
C14
10μF
10V
C16
0.1μF
16V
C9
10μF
10V
C8
10μF
10V
C25
0.1μF
16V
C26
0.1μF
16V
C18
0.1μF
16V
C29
0.1μF
16V
C23
0.1μF
16V
C28
0.1μF
16V C27
10μF
10V
C1
0.1μF
16V
C17
0.1μF
16V
C31
0.1μF
16V
C33
10μF
10V
C24
0.1μF
16V
R20
51.1Ω
R16
51.1Ω
R24
0.0Ω
R21
100Ω
R19
100Ω
+3.3VE
+3.3VE
+3.3VE
DGND
AGND
DGND
AGND AGND AGND AGND AGND AGND AGND AGND DGND DGND DGND DGND DGND DGND DGND DGND
AGND
DGND
DGND
DGND
L3
P8
P12
2
4
1
3
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD+3.3VD
+3.3VD
+3.3VE
+3.3VE
+3.3VE
+5VA
+5VA
R17
18.2kΩ
R18
100Ω
J12
J8
J11
J13
+5VA
J3
AGND
MH1
AGND
MH2
E15
D0
03208-B-015
Figure 19. Evaluation Board Schematic
AD10677
Rev. D | Page 15 of 20
AD10677/PCP
EVALUATION BOARD
03208-B-017
Figure 20. Evaluation Board Mechanical Layout, Top View
03208-B-018
Figure 21. Evaluation Board Mechanical Layout, Bottom View
AD10677
Rev. D | Page 16 of 20
03208-B-019
Figure 22. Evaluation Board Top Layer Copper
03208-B-020
Figure 23. Evaluation Board Second Layer Copper
AD10677
Rev. D | Page 17 of 20
03208-B-021
Figure 24. Evaluation Board Third Layer Copper
03208-B-022
Figure 25. Evaluation Board Bottom Layer Copper
AD10677
Rev. D | Page 18 of 20
OUTLINE DIMENSIONS
2.220
2.170
2.120
C21
C1 R41
P3
a
Top View
2.795
2.745
2.695
C15
MP3
MP4
MP5
MP6
U2
0.170
0.120
0.070
0.370
0.320
0.270 0.314
0.264
0.214
AD10677BWS
LOT NUMBER
DATA CODE
USA
C50
C54
C53
R15
R17
R16
C56
C55
C23
T1
R9
C63
C66
C64
C12
C62
R8
R7
C11
R37
C5
C18
R5
C6
R11 U8
U7
R25
C9
C7
R10
C14 C52 C51
C67
C59
C22C2R1
R4
R3
C19
C65
C13
C20
C25 C26
U1
R38
R13
R14
R40
R12
U3
C49
C39 C40
C17
C58
C57
R33
R27
R30
C43
C41
C45
C44
C35
C28
C24
C60
C61
R19
R18
C34
C8
R32R31
U6
U4
U5
R39
R2
R29 R34
R21
R28
C42
R26
C48
C38
R6 C47 C30
C37
C10
C36
C46
P1
P2
C31
C32
C3
C27
C4
C29
C33
R35
Figure 26. AD10677 Outline Dimensions
Dimensions shown in inches
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD10677BWS 0°C to 70°C Non-Herm Hybrid Surface Mount (2.2" × 2.8") WS-120
AD10677/PCB Evaluation Board
AD10677
Rev. D | Page 19 of 20
NOTES
AD10677
Rev. D | Page 20 of 20
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03208-0-5/06(D)