CY8C21123/CY8C21223/CY8C21323
PSoC® Programmable System-on-Chip™
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-12022 Rev. AC Revised November 22, 2017
Features
■Powerful Harvard-architecture processor:
❐M8C processor speeds up to 24 MHz
❐Low power at high speed
❐Operating voltage: 2.4 V to 5.25 V
❐Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐Industrial temperature range: –40 °C to +85 °C
■Advanced peripherals (PSoC® blocks):
❐Four analog type “E” PSoC blocks provide:
• Two comparators with digital to analog converter (DAC)
references
• Single or dual 10-Bit 8-to-1 analog to digital converter
(ADC)
❐Four digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• CRC and PRS modules
❐Full duplex UART, SPI master or slave: Connectable to all
general-purpose I/O (GPIO) pins
❐Complex peripherals by combining blocks
■Flexible on-chip memory:
❐4 KB flash program storage 50,000 erase/write cycles
❐256 bytes SRAM data storage
❐In-system serial programming (ISSP)
❐Partial flash updates
❐Flexible protection modes
❐EEPROM emulation in flash
■Complete development tools:
❐Free development software (PSoC Designer™)
❐Full-featured, in-circuit emulator (ICE) and programmer
❐Full-speed emulation
❐Complex breakpoint structure
❐128-KB trace memory
■Precision, programmable clocking:
❐Internal ±5% 24- / 48-MHz main oscillator
❐Internal low-speed, low-power oscillator for watchdog and
sleep functionality
■Programmable pin configurations:
❐25-mA sink, 10-mA source on all GPIOs
❐Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
❐Up to eight analog inputs on all GPIOs
❐Configurable interrupt on all GPIOs
■
■Additional system resources:
❐I2C master, slave and multi-master to 400 kHz
❐Watchdog and sleep timers
❐User-configurable low-voltage detection (LVD)
❐Integrated supervisory circuit
❐On-chip precision voltage reference
Logic Block Diagram
DIGITAL SYSTEM
SRAM
System Bus
Int er r u pt
Controller
Sleep and
Watchdog
Clock Sources
(Includes IMO and ILO)
Global Digital Interconnect Global Analog Interconnect
PSoC
CORE
CPU Core
(M8C)
SROM Flash
I2C
Internal
Voltage
Ref .
Digital
Cloc ks
POR and LVD
System Resets
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref .
Por t 1 Por t 0
Digita l
P S o C B l oc k
Array
Ana log
PSoC Block
Array
Sw itch
Mode
Pu mp
Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above 70 °C),
frequency tolerance deviates from ±2.5% to ±5%. For information on silicon errata, see “Errata” on page 43.
Document Number: 38-12022 Rev. AC Page 2 of 47
CY8C21123/CY8C21223/CY8C21323
Contents
PSoC Functional Overview .............................................. 3
PSoC Core .................................................................. 3
Digital System ............................................................. 3
Analog System ............................................................ 4
Additional System Resources ..................................... 4
PSoC Device Characteristics ...................................... 5
Getting Started .................................................................. 5
Application Notes ........................................................ 5
Development Kits ........................................................ 5
Training ....................................................................... 5
CYPros Consultants .................................................... 5
Solutions Library .......................................................... 5
Technical Support ....................................................... 5
Development Tool Selection ........................................... 6
Software ...................................................................... 6
Designing with PSoC Designer ....................................... 7
Select Components ..................................................... 7
Configure Components ............................................... 7
Organize and Connect ................................................ 7
Generate, Verify, and Debug ....................................... 7
Pin Information ................................................................. 8
8-Pin Part Pinout ......................................................... 8
16-Pin Part Pinout ....................................................... 8
20-Pin Part Pinout ..................................................... 10
24-Pin Part Pinout ..................................................... 11
Register Reference ......................................................... 12
Register Conventions ................................................ 12
Register Mapping Tables .......................................... 12
Electrical Specifications ................................................ 16
Absolute Maximum Ratings .......................................16
Operating Temperature ............................................ 17
DC Electrical Characteristics ..................................... 17
AC Electrical Characteristics ..................................... 23
Packaging Information ................................................... 31
Packaging Dimensions .............................................. 31
Thermal Impedances ................................................ 35
Solder Reflow Specifications ..................................... 35
Ordering Information ...................................................... 36
Ordering Code Definitions ........................................ 36
Acronyms ........................................................................ 37
Acronyms Used ......................................................... 37
Reference Documents .................................................... 37
Document Conventions ................................................. 38
Units of Measure ....................................................... 38
Numeric Conventions ................................................ 38
Glossary .......................................................................... 38
Errata ............................................................................... 43
Part Numbers Affected .............................................. 43
CY8C21123 Qualification Status ............................... 43
CY8C21123 Errata Summary .................................... 43
Document History Page ................................................. 44
Sales, Solutions, and Legal Information ...................... 47
Worldwide Sales and Design Support ....................... 47
Products .................................................................... 47
PSoC® Solutions ....................................................... 47
Cypress Developer Community ................................. 47
Technical Support ..................................................... 47
Document Number: 38-12022 Rev. AC Page 3 of 47
CY8C21123/CY8C21223/CY8C21323
PSoC Functional Overview
The PSoC family consists of many programmable
system-on-chip controller devices. These devices are designed
to replace multiple traditional MCU-based system components
with a low cost single-chip programmable component. A PSoC
device includes configurable blocks of analog and digital logic,
and programmable interconnect. This architecture allows you to
create customized peripheral configurations, to match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable I/O are included in a range of convenient pinouts.
The PSoC architecture, as shown in Figure 1, consists of four
main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow the combining of all device resources into a
complete custom system. Each PSoC device includes four digital
blocks. Depending on the PSoC package, up to two analog
comparators and up to 16 GPIO are also included. The GPIO
provide access to the global digital and analog interconnects.
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and internal main
oscillator (IMO), and internal low-speed oscillator (ILO). The
CPU core, called the M8C, is a powerful processor with speeds
up to 24 MHz. The M8C is a four MIPS 8-bit Harvard-architecture
microprocessor.
System Resources provide additional capability, such as digital
clocks or I2C functionality for implementing an I2C master, slave,
MultiMaster, an internal voltage reference that provides an
absolute value of 1.3 V to a number of PSoC subsystems, an
SMP that generates normal operating voltages off a single
battery cell, and various system resets supported by the M8C.
The digital system consists of an array of digital PSoC blocks,
which can be configured into any number of digital peripherals.
The digital blocks can be connected to the GPIO through a series
of global bus that can route any signal to any pin. This frees
designs from the constraints of a fixed peripheral controller.
The analog system consists of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to
10 bits of precision.
Digital System
The digital system consists of four digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user modules. Digital peripheral configurations
include:
■PWMs (8- and 16-bit)
■PWMs with dead band (8- and 16-bit)
■Counters (8- to 32-bit)
■Timers (8- to 32-bit)
■UART 8-bit with selectable parity (up to two)
■SPI master and slave
■I2C slave, master, multi-master (one available as a system
resource)
■Cyclical redundancy checker/generator (8-bit)
■IrDA (up to two)
■Pseudo random sequence generators (8- to 32-bit)
The digital blocks can be connected to any GPIO through a
series of global bus that can route any signal to any pin. The
busses also allow for signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This provides an optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 5.
Figure 1. Digital System Block Diagram
DIGITAL SYSTEM
To System Bus
Digital Clocks
From Core
Digital PSoC Block Arra y
To Analog
System
8
Row Input
Configuration
Row Output
Configuration
88
8
Row 0
DBB00 DBB01 DCB02 DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 1
Port 0
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CY8C21123/CY8C21223/CY8C21323
Analog System
The analog system consists of four configurable blocks to allow
creation of complex analog signal flows. Analog peripherals are
very flexible and may be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are:
■Analog-to-digital converters (single or dual, with 8-bit or 10-bit
resolution)
■Pin-to-pin comparators (one)
■Single-ended comparators (up to 2) with absolute (1.3 V)
reference or 8-bit DAC reference
■1.3 V reference (as a system resource)
In most PSoC devices, analog blocks are provided in columns of
three, which includes one CT (continuous time) and two SC
(switched capacitor) blocks. The CY8C21x23 devices provide
limited functionality Type “E” analog blocks. Each column
contains one CT block and one SC block.
The number of blocks on the device family is listed in Table 1 on
page 5.
Figure 2. CY8C21x23 Analog System Block Diagram
Additional System Resources
System resources, some of which listed in the previous sections,
provide additional capability useful to complete systems.
Additional resources include a switch mode pump, low voltage
detection, and power on reset. The merits of each system
resource are.
■Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■LVD interrupts can signal the application of falling voltage
levels, while the advanced POR (power on reset) circuit
eliminates the need for a system supervisor.
■An internal 1.3 V voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
■An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2 V battery cell, providing a
low cost boost converter.
AC OL 1M U X
ACE00 ACE01
Array
Array Input
Configuration
ACI0[1:0] ACI1[1:0]
ASE10 ASE11
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CY8C21123/CY8C21223/CY8C21323
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or 4
analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is
highlighted.
Getting Started
The quickest way to understand PSoC silicon is to read this
datasheet and then use the PSoC Designer Integrated Devel-
opment Environment (IDE). This datasheet is an overview of the
PSoC integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming
details, see the Technical Reference Manual for this PSoC
device.
For up to date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web
at http://www.cypress.com.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They can be found at
http://www.cypress.com.
Development Kits
PSoC Development Kits are available online from Cypress at
http://www.cypress.com and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at http://www.cypress.com. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com and refer to
CYPros Consultants.
Solutions Library
Visit our growing library of solution focused designs at
http://www.cypress.com. Here you can find various application
designs that include firmware and hardware design files that
enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at http://www.cypress.com. If you cannot find
an answer to your question, call technical support at
1-800-541-4736.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
CY8C29x66 up to 64 4 16 up to 12 4 4 12 2 K 32 K
CY8C28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to
12 + 4[1] 1 K 16 K
CY8C27x43 up to 44 2 8 up to 12 4 4 12 256 16 K
CY8C24x94 up to 56 1 4 up to 48 2 2 6 1 K 16 K
CY8C24x23A up to 24 1 4 up to 12 2 2 6 256 4 K
CY8C23x33 up to 26 1 4 up to 12 2 2 4 256 8 K
CY8C22x45 up to 38 2 8 up to 38 0 4 6[1] 1 K 16 K
CY8C21x45 up to 24 1 4 up to 24 0 4 6[1] 512 8 K
CY8C21x34 up to 28 1 4 up to 28 0 2 4[1] 512 8 K
CY8C21x23 up to 16 1 4 up to 8 0 2 4[1] 256 4 K
CY8C20x34 up to 28 0 0 up to 28 0 0 3[1,2] 512 8 K
CY8C20xx6 up to 36 0 0 up to 36 0 0 3[1,2] up to
2 K
up to
32 K
Notes
1. Limited analog functionality.
2. Two analog blocks and one CapSense®.
Document Number: 38-12022 Rev. AC Page 6 of 47
CY8C21123/CY8C21223/CY8C21323
Development Tool Selection
Software
PSoC Designer
At the core of the PSoC development software suite is
PSoC Designer. Utilized by thousands of PSoC developers, this
robust software has been facilitating PSoC designs for years.
PSoC Designer is available free of charge at
http://www.cypress.com. PSoC Designer comes with a free C
compiler.
PSoC Designer Software Subsystems
You choose a base device to work with and then select different
onboard analog and digital components called user modules that
use the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters. You configure the user modules
for your chosen application and connect them to each other and
to the proper pins. Then you generate your project. This prepop-
ulates your project with APIs and libraries that you can use to
program your application.
The tool also supports easy development of multiple configura-
tions and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time. Code Generation
Tools PSoC Designer supports multiple third-party C compilers
and assemblers. The code generation tools work seamlessly
within the PSoC Designer interface and have been tested with a
full range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all the features of C tailored to
the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write I/O
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices. The emulator consists of a
base unit that connects to the PC by way of a USB port. The base
unit is universal and operates with all PSoC devices. Emulation
pods for each device family are available separately. The
emulation pod takes the place of the PSoC device in the target
board and performs full speed (24MHz) operation.
Standard Cypress PSoC IDE tools are available for debugging
the CY8C20x36A/66A family of parts. However, the additional
trace length and a minimal ground plane in the Flex-Pod can
create noise problems that make it difficult to debug the design.
A custom bonded On-Chip Debug (OCD) device is available in a
48-pin QFN package. The OCD device is recommended for
debugging designs that have high current and/or high analog
accuracy requirements. The QFN package is compact and is
connected to the ICE through a high density connector.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube in-circuit emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com/psocprogrammer.
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CY8C21123/CY8C21223/CY8C21323
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select User Modules
2. Configure User Modules
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
PSoC Designer provides a library of pre-built, pre-tested
hardware peripheral components called "user modules." User
modules make selecting and implementing peripheral devices,
both analog and digital, simple.
Configure Components
Each of the User Modules you select establishes the basic
register settings that implement the selected function. They also
provide parameters and properties that allow you to tailor their
precise configuration to your particular application. For example,
a PWM User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to corre-
spond to your chosen application. Enter values directly or by
selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the User Module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the "Generate
Configuration Files" step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer's Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabil-
ities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events that include
monitoring address and data bus values, memory locations and
external signals.
Document Number: 38-12022 Rev. AC Page 8 of 47
CY8C21123/CY8C21223/CY8C21323
Pin Information
This section describes, lists, and illustrates the CY8C21x23 PSoC device pins and pinout configurations. Every port pin (labeled with
a “P”) is capable of Digital I/O. However, VSS, VDD, SMP, and XRES are not capable of Digital I/O.
8-Pin Part Pinout
16-Pin Part Pinout
Table 2. Pin Definitions – CY8C21123 8-Pin SOIC
Pin
No.
Type Pin
Name Description Figure 3. CY8C21123 8-Pin SOIC
Digital Analog
1I/O IP0[5] Analog column mux input
2I/O IP0[3] Analog column mux input
3I/O P1[1] I2C serial clock (SCL), ISSP-SCLK[3]
4Power VSS Ground connection
5I/O P1[0] I2C serial data (SDA), ISSP-SDATA[3]
6I/O IP0[2] Analog column mux input
7I/O IP0[4] Analog column mux input
8Power VDD Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.
Table 3. Pin Definitions – CY8C21223 16-Pin SOIC
Pin
No.
Type Pin
Name Description Figure 4. CY8C21223 16-Pin SOIC
Digital Analog
1I/O IP0[7] Analog column mux input
2I/O IP0[5] Analog column mux input
3I/O IP0[3] Analog column mux input
4I/O IP0[1] Analog column mux input
5Power SMP SMP connection to required external
components
6Power VSS Ground connection
7I/O P1[1] I2C SCL, ISSP-SCLK[3]
8Power VSS Ground connection
9I/O P1[0] I2C SDA, ISSP-SDATA[3]
10 I/O P1[2]
11 I/O P1[4] Optional external clock input (EXTCLK)
12 I/O IP0[0] Analog column mux input
13 I/O IP0[2] Analog column mux input
14 I/O IP0[4] Analog column mux input
15 I/O IP0[6] Analog column mux input
16 Power VDD Supply voltage
LEGEND A = Analog, I = Input, and O = Output.
SOIC
VDD
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
P1[4], EXTCLK
P1[2]
P1[0], I2C SDA
16
15
14
13
12
11
1
2
3
4
5
6
7
8
A, I, P0[7]
A, I, P0[5]
A, I, P0[3]
A, I, P0[1]
SMP
VSS
I2C SCL, P1[1]
VSS
10
9
Note
3. These are the ISSP pins, which are not high Z at POR (power on reset). See the PSoC Technical Reference Manual for details.
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Table 4. Pin Definitions – CY8C21223 16-Pin QFN with no E-Pad [4]
Pin
No.
Type Pin
Name Description Figure 5. CY8C21223 16-Pin QFN
Digital Analog
1I/O IP0[3] Analog column mux input
2I/O I P0[1] Analog column mux input
3I/O P1[7] I2C SCL
4I/O P1[5] I2C SDA
5I/O P1[3]
6I/O P1[1] I2C SCL, ISSP-SCLK[5]
7Power VSS Ground connection
8I/O P1[0] I2C SDA, ISSP-SDATA[5]
9I/O P1[6]
10 I/O P1[4] EXTCLK
11 Input XRES Active high external reset with internal
pull-down
12 I/O IP0[4] VREF
13 Power VDD Supply voltage
14 I/O IP0[7] Analog column mux input
15 I/O IP0[5] Analog column mux input
16 NC No Connection. Pin must be left floating
LEGEND A = Analog, I = Input, and O = Output.
QFN
(Top View)
1
2
3
4
12
11
10
9
5
6
7
813
14
15
16
P0[4], VREF
P0[5], AI
P0[7], AI
VDD
P1[3]
I2C SCL, P1[1]
VSS
I2C SDA, P1[0]
XRES
P1[4]
P1[6]
AI, P0[3]
AI, P0[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
NC
Notes
4. The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
5. These are the ISSP pins, which are not high Z at POR (power on reset). See the PSoC Technical Reference Manual for details.
Document Number: 38-12022 Rev. AC Page 10 of 47
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20-Pin Part Pinout
Table 5. Pin Definitions – CY8C21323 20-Pin SSOP
Pin
No.
Type Pin
Name Description Figure 6. CY8C21323 20-Pin SSOP
Digital Analog
1I/O IP0[7] Analog column mux input
2I/O IP0[5] Analog column mux input
3I/O IP0[3] Analog column mux input
4I/O IP0[1] Analog column mux input
5Power VSS Ground connection[6]
6I/O P1[7] I2C SCL
7I/O P1[5] I2C SDA
8I/O P1[3]
9I/O P1[1] I2C SCL, ISSP-SCLK[7]
10 Power VSS Ground connection[6]
11 I/O P1[0] I2C SDA, ISSP-SDATA[7]
12 I/O P1[2]
13 I/O P1[4] Optional EXTCLK input
14 I/O P1[6]
15 Input XRES Active high external reset with internal
pull-down
16 I/O IP0[0] Analog column mux input
17 I/O IP0[2] Analog column mux input
18 I/O IP0[4] Analog column mux input
19 I/O IP0[6] Analog column mux input
20 Power VDD Supply voltage
LEGEND A = Analog, I = Input, and O = Output.
SSOP
VDD
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], I2C SDA
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
A, I, P0[7]
A, I, P0[5]
A, I, P0[3]
A, I, P0[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, P1[1]
VSS
VSS
Notes
6. All VSS pins should be brought out to one common GND plane.
7. These are the ISSP pins, which are not high Z at POR (power on reset). See the PSoC Technical Reference Manual for details.
Document Number: 38-12022 Rev. AC Page 11 of 47
CY8C21123/CY8C21223/CY8C21323
24-Pin Part Pinout
Table 6. Pin Definitions – CY8C21323 24-Pin QFN[8]
Pin
No.
Type Pin
Name Description Figure 7. CY8C21323 24-Pin QFN
Digital Analog
1I/O IP0[1] Analog column mux input
2Power SMP SMP connection to required external
components
3Power VSS Ground connection[9]
4I/O P1[7] I2C SCL
5I/O P1[5] I2C SDA
6I/O P1[3]
7I/O P1[1] I2C SCL, ISSP-SCLK[10]
8NC No connection. Pin must be left floating
9Power VSS Ground connection[9]
10 I/O P1[0] I2C SDA, ISSP-SDATA[10]
11 I/O P1[2]
12 I/O P1[4] Optional (EXTCLK) input
13 I/O P1[6]
14 Input XRES Active high external reset with internal
pull-down
15 NC No connection. Pin must be left floating
16 I/O IP0[0] Analog column mux input
17 I/O IP0[2] Analog column mux input
18 I/O IP0[4] Analog column mux input
19 I/O IP0[6] Analog column mux input
20 Power VDD Supply voltage
21 Power VSS Ground connection[9]
22 I/O IP0[7] Analog column mux input
23 I/O IP0[5] Analog column mux input
24 I/O IP0[3] Analog column mux input
LEGEND A = Analog, I = Input, and O = Output.
QFN
(Top View)
A, I, P0[1]
SMP
VSS
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
1
2
3
4
5
6
18
17
16
15
14
13
P0[4], A, I
P0[2], A, I
NC
XRES
P1[6]
24
23
22
21
20
19
P0[3], A, I
P0[5], A, I
P0[7], A, I
VSS
VDD
P0[6], A, I
7
8
9
10
11
12
I2C SCL, P1[1]
NC
VSS
I2C SDA, P1[0]
P1[2]
EXTCLK, P1[4]
P0[0], A, I
Notes
8. The center pad on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
9. All VSS pins should be brought out to one common GND plane.
10. These are the ISSP pins, which are not high Z at POR (power on reset). See the PSoC Technical Reference Manual for details.
Document Number: 38-12022 Rev. AC Page 12 of 47
CY8C21123/CY8C21223/CY8C21323
Register Reference
This section lists the registers of the CY8C21x23 PSoC device.
For detailed register information, refer the PSoC Technical
Reference Manual.
Register Conventions
The register conventions specific to this section are listed in
Tab l e 7.
Register Mapping Tables
The PSoC device has a total register address space of
512 bytes. The register space is referred to as I/O space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines the bank you are currently in. When the XOI bit is set,
you are in Bank 1.
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Table 7. Register Conventions
Convention Description
R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific
Document Number: 38-12022 Rev. AC Page 13 of 47
CY8C21123/CY8C21223/CY8C21323
Table 8. Register Map Bank 0 Table: User Space
Name Addr
(0,Hex) Access Name Addr
(0,Hex) Access Name Addr
(0,Hex) Access Name Addr
(0,Hex) Access
PRT0DR 00 RW 40 ASE10CR0 80 RW C0
PRT0IE 01 RW 41 81 C1
PRT0GS 02 RW 42 82 C2
PRT0DM2 03 RW 43 83 C3
PRT1DR 04 RW 44 ASE11CR0 84 RW C4
PRT1IE 05 RW 45 85 C5
PRT1GS 06 RW 46 86 C6
PRT1DM2 07 RW 47 87 C7
08 48 88 C8
09 49 89 C9
0A 4A 8A CA
0B 4B 8B CB
0C 4C 8C CC
0D 4D 8D CD
0E 4E 8E CE
0F 4F 8F CF
10 50 90 D0
11 51 91 D1
12 52 92 D2
13 53 93 D3
14 54 94 D4
15 55 95 D5
16 56 96 I2C_CFG D6 RW
17 57 97 I2C_SCR D7 #
18 58 98 I2C_DR D8 RW
19 59 99 I2C_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C DC
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F DF
DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW
DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW
DBB00DR2 22 RW PWM_CR 62 RW A2 INT_VC E2 RC
DBB00CR0 23 # 63 A3 RES_WDT E3 W
DBB01DR0 24 # CMP_CR0 64 # A4 E4
DBB01DR1 25 W 65 A5 E5
DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW
DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW
DCB02DR0 28 # ADC0_CR 68 #A8 E8
DCB02DR1 29 W ADC1_CR 69 #A9 E9
DCB02DR2 2A RW 6A AA EA
DCB02CR0 2B # 6B AB EB
DCB03DR0 2C # TMP_DR0 6C RW AC EC
DCB03DR1 2D W TMP_DR1 6D RW AD ED
DCB03DR2 2E RW TMP_DR2 6E RW AE EE
DCB03CR0 2F # TMP_DR3 6F RW AF EF
Blank fields are Reserved and must not be accessed. # Access is bit specific.
Document Number: 38-12022 Rev. AC Page 14 of 47
CY8C21123/CY8C21223/CY8C21323
30 70 RDI0RI B0 RW F0
31 71 RDI0SYN B1 RW F1
32 ACE00CR1 72 RW RDI0IS B2 RW F2
33 ACE00CR2 73 RW RDI0LT0 B3 RW F3
34 74 RDI0LT1 B4 RW F4
35 75 RDI0RO0 B5 RW F5
36 ACE01CR1 76 RW RDI0RO1 B6 RW F6
37 ACE01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD FD
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Table 9. Register Map Bank 1 Table: Configuration Space
Name Addr
(1,Hex) Access Name Addr
(1,Hex) Access Name Addr
(1,Hex) Access Name Addr
(1,Hex) Access
PRT0DM0 00 RW 40 ASE10CR0 80 RW C0
PRT0DM1 01 RW 41 81 C1
PRT0IC0 02 RW 42 82 C2
PRT0IC1 03 RW 43 83 C3
PRT1DM0 04 RW 44 ASE11CR0 84 RW C4
PRT1DM1 05 RW 45 85 C5
PRT1IC0 06 RW 46 86 C6
PRT1IC1 07 RW 47 87 C7
08 48 88 C8
09 49 89 C9
0A 4A 8A CA
0B 4B 8B CB
0C 4C 8C CC
0D 4D 8D CD
0E 4E 8E CE
0F 4F 8F CF
10 50 90 GDI_O_IN D0 RW
11 51 91 GDI_E_IN D1 RW
12 52 92 GDI_O_OU D2 RW
13 53 93 GDI_E_OU D3 RW
14 54 94 D4
15 55 95 D5
16 56 96 D6
17 57 97 D7
18 58 98 D8
19 59 99 D9
1A 5A 9A DA
1B 5B 9B DB
Blank fields are Reserved and must not be accessed. # Access is bit specific.
Table 8. Register Map Bank 0 Table: User Space (continued)
Name Addr
(0,Hex) Access Name Addr
(0,Hex) Access Name Addr
(0,Hex) Access Name Addr
(0,Hex) Access
Blank fields are Reserved and must not be accessed. # Access is bit specific.
Document Number: 38-12022 Rev. AC Page 15 of 47
CY8C21123/CY8C21223/CY8C21323
1C 5C 9C DC
1D 5D 9D OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW
DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW
DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW
23 AMD_CR0 63 RW A3 VLT_CR E3 RW
DBB01FN 24 RW CMP_GO_EN 64 RW A4 VLT_CMP E4 R
DBB01IN 25 RW 65 A5 ADC0_TR E5 RW
DBB01OU 26 RW AMD_CR1 66 RW A6 ADC1_TR E6 RW
27 ALT_CR0 67 RW A7 E7
DCB02FN 28 RW 68 A8 IMO_TR E8 W
DCB02IN 29 RW 69 A9 ILO_TR E9 W
DCB02OU 2A RW 6A AA BDG_TR EA RW
2B CLK_CR3 6B RW AB ECO_TR EB W
DCB03FN 2C RW TMP_DR0 6C RW AC EC
DCB03IN 2D RW TMP_DR1 6D RW AD ED
DCB03OU 2E RW TMP_DR2 6E RW AE EE
2F TMP_DR3 6F RW AF EF
30 70 RDI0RI B0 RW F0
31 71 RDI0SYN B1 RW F1
32 ACE00CR1 72 RW RDI0IS B2 RW F2
33 ACE00CR2 73 RW RDI0LT0 B3 RW F3
34 74 RDI0LT1 B4 RW F4
35 75 RDI0RO0 B5 RW F5
36 ACE01CR1 76 RW RDI0RO1 B6 RW F6
37 ACE01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FLS_PR1 FA RW
3B 7B BB FB
3C 7C BC FC
3D 7D BD FD
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Table 9. Register Map Bank 1 Table: Configuration Space (continued)
Name Addr
(1,Hex) Access Name Addr
(1,Hex) Access Name Addr
(1,Hex) Access Name Addr
(1,Hex) Access
Blank fields are Reserved and must not be accessed. # Access is bit specific.
Document Number: 38-12022 Rev. AC Page 16 of 47
CY8C21123/CY8C21223/CY8C21323
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C21x23 PSoC device. For up to date electrical specifications,
check if you have the latest datasheet by visiting the web at http://www.cypress.com.
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted.
Refer to Table 24 on page 25 for the electrical specifications on the IMO using SLIMO mode.
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
5.25
4.75
3.00
93 kHz 12 MHz 24 MHz
CPU Frequency
Vdd Voltage
5.25
4.75
3.00
93 kHz 12 MHz 24 MHz
I M O F r e q u e n c y
Vdd Voltage
3.60
6 MHz
SLIMO Mode = 0
SLIMO
Mode=0
2.40
SLIMO
Mode=1
SLIMO
Mode=1
SLIMO
Mode=1
2.40
3 MHz
Valid
Operating
Region
SLIMO
Mode=1
SLIMO
Mode=0
Figure 10. Voltage versus CPU Frequency
Figure 11. Voltage versus IMO Frequency
Table 10. Absolute Maximum Ratings
Symbol Description Min Typ Max Units Notes
TSTG Storage temperature –55 –+100 °C
Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is +25 °C ± 25 °C.
Extended duration storage
temperatures higher than 65 °C
degrade reliability.
TBAKETEMP Bake temperature –125
See
package
label
°C
tBAKETIME Bake time
See
package
label
–72 Hours
TAAmbient temperature with power applied –40 –+85 °C
VDD Supply voltage on VDD relative to VSS –0.5 –+6.0 V
VIO DC input voltage VSS – 0.5 – VDD + 0.5 V
VIOZ DC voltage applied to tristate VSS – 0.5 – VDD + 0.5 V
IMIO Maximum current into any port pin –25 –+50 mA
ESD Electro static discharge voltage 2000 – – V Human body model ESD
LU Latch-up current – – 200 mA
Document Number: 38-12022 Rev. AC Page 17 of 47
CY8C21123/CY8C21223/CY8C21323
Operating Temperature
DC Electrical Characteristics
DC Chip-Level Specifications
Tab l e 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 11. Operating Temperature
Symbol Description Min Typ Max Units Notes
TAAmbient temperature –40 –+85 °C
TJJunction temperature –40 –+100 °C
The temperature rise from
ambient to junction is package
specific. See Table 36 on page
35. You must limit the power
consumption to comply with this
requirement.
Table 12. DC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
VDD Supply voltage 2.40 –5.25 V
See DC POR and LVD
specifications,
Table 19 on page 21.
IDD Supply current, IMO = 24 MHz – 3 4 mA
Conditions are VDD = 5.0 V,
25 °C, CPU = 3 MHz, SYSCLK
doubler disabled. VC1 = 1.5 MHz
VC2 = 93.75 kHz
VC3 = 0.366 kHz
IDD3 Supply current, IMO = 6 MHz –1.2 2mA
Conditions are VDD = 3.3 V,
25 °C, CPU = 3 MHz, clock doubler
disabled. VC1 = 375 kHz
VC2 = 23.4 kHz
VC3 = 0.091 kHz
IDD27 Supply current, IMO = 6 MHz –1.1 1.5 mA
Conditions are VDD = 2.55 V,
25 °C, CPU = 3 MHz, clock doubler
disabled. VC1 = 375 kHz VC2 =
23.4 kHz
VC3 = 0.091 kHz
ISB27
Sleep (mode) current with POR, LVD, sleep
timer, WDT, and internal slow
oscillator active. Mid temperature range.
–2.6 4µA VDD = 2.55 V, 0 °C to 40 °C
ISB
Sleep (mode) current with POR, LVD, sleep
timer, WDT, and internal slow
oscillator active.
–2.8 5µA VDD = 3.3 V, –40 °C TA 85 °C
VREF Reference voltage (bandgap) 1.28 1.30 1.32 VTrimmed for appropriate VDD. VDD
= 3.0 V to 5.25 V
VREF27 Reference voltage (bandgap) 1.16 1.30 1.330 VTrimmed for appropriate VDD. VDD
= 2.4 V to 3.0 V
AGND Analog ground VREF – 0.003 VREF VREF + 0.003 V
Document Number: 38-12022 Rev. AC Page 18 of 47
CY8C21123/CY8C21223/CY8C21323
DC GPIO Specifications
Tab l e 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C and
are for design guidance only.
Tab l e 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 3.0 V and
–40 °C TA 85 °C. Typical parameters apply to 2.7 V at 25 °C and are for design guidance only.
Table 13. 5-V and 3.3-V DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
RPU Pull-up resistor 4 5.6 8 k
RPD Pull-down resistor 4 5.6 8 k
VOH High output level VDD – 1.0 – – V
IOH = 10 mA, VDD = 4.75 to 5.25 V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])).
80 mA maximum combined IOH budget.
VOL Low output level – – 0.75 V
IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])).
150 mA maximum combined IOL budget.
IOH High level source current 10 – – mA VOH = VDD – 1.0 V, see the limitations of the
total current in the note for VOH.
IOL Low level sink current 25 – – mA VOL = 0.75 V, see the limitations of the total
current in the note for VOL
VIL Input low level – – 0.8 V VDD = 3.0 to 5.25
VIH Input high level 2.1 – V VDD = 3.0 to 5.25
VHInput hysteresis –60 –mV
IIL Input leakage (absolute value) – 1 – nA Gross tested to 1 µA
CIN Capacitive load on pins as input – 3.5 10 pF Package and pin dependent.
Temp = 25 °C
COUT Capacitive load on pins as output –3.5 10 pF Package and pin dependent.
Temp = 25 °C
Table 14. 2.7-V DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
RPU Pull-up resistor 4 5.6 8 k
RPD Pull-down resistor 4 5.6 8 k
VOH High output level VDD – 0.4 – – V
IOH = 2.5 mA (6.25 Typ), VDD = 2.4 to
3.0 V (16 mA maximum, 50 mA Typ
combined IOH budget).
VOL Low output level – – 0.75 V IOL = 10 mA, VDD = 2.4 to 3.0 V (90 mA
maximum combined IOL budget).
IOH High level source current 2.5 – – mA VOH = VDD – 0.4 V, see the limitations of the
total current in the note for VOH.
IOL Low level sink current 10 – – mA VOL = 0.75 V, see the limitations of the total
current in the note for VOL.
VIL Input low level – – 0.75 V VDD = 2.4 to 3.0
VIH Input high level 2.0 – – V VDD = 2.4 to 3.0
VHInput hysteresis – 60 – mV
IIL Input leakage (absolute value) – 1 – nA Gross tested to 1 µA
CIN Capacitive load on pins as input – 3.5 10 pF Package and pin dependent.
Temp = 2 5 ° C
COUT Capacitive load on pins as output – 3.5 10 pF Package and pin dependent.
Temp = 2 5 ° C
Document Number: 38-12022 Rev. AC Page 19 of 47
CY8C21123/CY8C21223/CY8C21323
DC Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 15. 5-V DC Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input offset voltage (absolute value) – 2.5 15 mV
TCVOSOA Average input offset voltage drift – 10 – µV/°C
IEBOA Input leakage current (port 0 analog pins) – 200 – pA Gross tested to 1 µA
CINOA Input capacitance (port 0 analog pins) – 4.5 9.5 pF Package and pin dependent.
Temp = 25 °C
VCMOA Common mode voltage range 0.0 – VDD – 1 V
GOLOA Open loop gain 80 – – dB
ISOA Amplifier supply current – 10 30 µA
Table 16. 3.3-V DC Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input offset voltage (absolute value) – 2.5 15 mV
TCVOSOA Average input offset voltage drift – 10 – µV/°C
IEBOA Input leakage current (port 0 analog pins) – 200 – pA Gross tested to 1 µA
CINOA Input capacitance (port 0 analog pins) – 4.5 9.5 pF Package and pin dependent.
Temp = 25 °C
VCMOA Common mode voltage range 0 – VDD – 1 V
GOLOA Open loop gain 80 – – dB
ISOA Amplifier supply current – 10 30 µA
Table 17. 2.7V DC Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input offset voltage (absolute value) – 2.5 15 mV
TCVOSOA Average input offset voltage drift – 10 – µV/°C
IEBOA Input leakage current (port 0 analog pins) – 200 – pA Gross tested to 1 µA
CINOA Input capacitance (port 0 analog pins) – 4.5 9.5 pF Package and pin dependent.
Temp = 25 °C
VCMOA Common mode voltage range 0 – VDD – 1 V
GOLOA Open loop gain 80 – – dB
ISOA Amplifier supply current – 10 30 µA
Document Number: 38-12022 Rev. AC Page 20 of 47
CY8C21123/CY8C21223/CY8C21323
DC Switch Mode Pump Specifications
Table 18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 18. DC Switch Mode Pump (SMP) Specifications
Symbol Description Min Typ Max Units Notes
VPUMP5V 5 V output voltage from pump 4.75 5.0 5.25 V
Configuration of footnote.[11] Average,
neglecting ripple. SMP trip voltage is set to
5.0 V.
VPUMP3V 3.3 V output voltage from pump 3.00 3.25 3.60 V
Configuration of footnote.[11] Average,
neglecting ripple. SMP trip voltage is set to
3.25 V.
VPUMP2V 2.6 V output voltage from pump 2.45 2.55 2.80 V
Configuration of footnote.[11] Average,
neglecting ripple. SMP trip voltage is set to
2.55 V.
IPUMP
Available output current
VBAT = 1.8 V, VPUMP = 5.0 V
VBAT = 1.5 V, VPUMP = 3.25 V
VBAT = 1.3 V, VPUMP = 2.55 V
5
8
8
–
–
–
–
–
–
mA
mA
mA
Configuration of footnote.[11]
SMP trip voltage is set to 5.0 V.
SMP trip voltage is set to 3.25 V.
SMP trip voltage is set to 2.55 V.
VBAT5V Input voltage range from battery 1.8 – 5.0 V Configuration of footnote.[11] SMP trip
voltage is set to 5.0 V.
VBAT3V Input voltage range from battery 1.0 – 3.3 V Configuration of footnote.[11] SMP trip
voltage is set to 3.25 V.
VBAT2V Input voltage range from battery 1.0 – 2.8 V Configuration of footnote.[11] SMP trip
voltage is set to 2.55 V.
VBATSTART
Minimum input voltage from battery to start
pump 1.2 – – V Configuration of footnote.[11] 0 °C TA
100. 1.25 V at TA = –40 °C.
VPUMP_Line Line regulation (over Vi range) – 5 – %VO
Configuration of footnote.[11] VO is the
“VDD Value for PUMP Trip” specified by the
VM[2:0] setting in the DC POR and LVD
Specification, Table 19 on page 21.
VPUMP_Load Load regulation – 5 – %VO
Configuration of footnote.[11] VO is the
“VDD Value for PUMP Trip” specified by the
VM[2:0] setting in the DC POR and LVD
Specification, Table 19 on page 21.
VPUMP_Ripple Output voltage ripple (depends on cap/load) – 100 – mVpp Configuration of footnote.[11] Load is
5 mA.
E3Efficiency 35 50 – % Configuration of footnote.[11] Load is
5 mA. SMP trip voltage is set to 3.25 V.
E2Efficiency 35 80 – %
For I load = 1 mA, VPUMP = 2.55 V,
VBAT = 1.3 V, 10 uH inductor, 1 uF
capacitor, and Schottky diode.
FPUMP Switching frequency – 1.3 – MHz
DCPUMP Switching duty cycle – 50 – %
Note
11. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. Refer to Figure 12 on page 21.
Document Number: 38-12022 Rev. AC Page 21 of 47
CY8C21123/CY8C21223/CY8C21323
Figure 12. Basic Switch Mode Pump Circuit
DC POR and LVD Specifications
Tab l e 19 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 19. DC POR and LVD Specifications
Symbol Description Min Typ Max Units Notes
VPPOR0
VPPOR1
VPPOR2
VDD value for PPOR trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
–
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
VDD must be greater than or equal to
2.5 V during startup, reset from the
XRES pin, or reset from watchdog.
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VDD value for LVD trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.45
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.51[12]
2.99[13]
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
V
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
VDD value for PUMP trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.45
2.96
3.03
3.18
4.54
4.62
4.71
4.89
2.55
3.02
3.10
3.25
4.64
4.73
4.82
5.00
2.62[14]
3.09
3.16
3.32[15]
4.74
4.83
4.92
5.12
V
V
V
V
V
V
V
V
Battery
C1
D1
+PSoCTM
Vdd
Vss
SMP
VBAT
VPUMP
L1
VDD
Notes
12. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply.
13. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply.
14. Always greater than 50 mV above VLVD 0.
15. Always greater than 50 mV above VLVD 3.
Document Number: 38-12022 Rev. AC Page 22 of 47
CY8C21123/CY8C21223/CY8C21323
DC Programming Specifications
Tab l e 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
DC I2C Specifications
Tab l e 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 20. DC Programming Specifications
Symbol Description Min Typ Max Units Notes
VDDP VDD for programming and erase 4.5 5.0 5.5 V
This specification applies to
the functional requirements
of external programmer tools
VDDLV Low VDD for verify 2.4 2.5 2.6 V
This specification applies to
the functional requirements
of external programmer tools
VDDHV High VDD for verify 5.1 5.2 5.3 V
This specification applies to
the functional requirements
of external programmer tools
VDDIWRITE Supply voltage for flash write operations 2.70 –5.25 V
This specification applies to
this device when it is
executing internal flash
writes
IDDP Supply current during programming or verify – 5 25 mA
VILP Input low voltage during programming or verify – – 0.8 V
VIHP Input high voltage during programming or verify 2.2 – – V
IILP
Input current when applying VILP to P1[0] or P1[1]
during programming or verify – – 0.2 mA Driving internal pull-down
resistor
IIHP
Input current when applying VIHP to P1[0] or P1[1]
during programming or verify – – 1.5 mA Driving internal pull-down
resistor
VOLV Output low voltage during programming or verify – – VSS + 0.75 V
VOHV Output high voltage during programming or verify VDD – 1.0 – VDD V
FlashENPB Flash endurance (per block) 50,000[16] – – – Erase/write cycles per block
FlashENT Flash endurance (total)[17] 1,800,0000–0–0–0Erase/write cycles
FlashDR Flash data retention 10 – – Years
Notes
16. The 50,000 cycle flash endurance per block is guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to 3.6 V,
and 4.75 V to 5.25 V.
17. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36 × 2
blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 36 × 50,000 and that no
single block ever sees more than 50,000 cycles).For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to
the temperature argument before writing. Refer to the application note, Design Aids — Reading and Writing PSoC® Flash – AN2015 for more information on Flash APIs.
18. All GPIO meet the DC GPIO VIL and VIH specifications mentioned in section DC GPIO Specifications on page 18. The I2C GPIO pins also meet the mentioned specs.
Table 21. DC I2C Specifications[18]
Symbol Description Min Typ Max Units Notes
VILI2C Input low level – – 0.3 × VDD V 2.4 V VDD 3.6 V
– – 0.25 × VDD V4.75 V VDD 5.25 V
VIHI2C Input high level 0.7 × VDD – – V 2.4 V VDD 5.25 V
Document Number: 38-12022 Rev. AC Page 23 of 47
CY8C21123/CY8C21223/CY8C21323
AC Electrical Characteristics
AC Chip-Level Specifications
Tab l e 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 22. 5-V and 3.3-V AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
FIMO24 [19] IMO frequency for 24 MHz 22.8 24 25.2 [20,21] MHz
Trimmed for 5 V or 3.3 V
operation using factory trim
values. Refer to Figure 11 on
page 16.
SLIMO mode = 0.
FIMO6 IMO frequency for 6 MHz 5.5 66.5[20,21] MHz
Trimmed for 3.3 V operation using
factory trim values. See Figure 11
on page 16.
SLIMO mode = 1.
FCPU1 CPU frequency (5 V nominal) 0.0937 24 24.6[20] MHz 12 MHz only for
SLIMO mode = 0.
FCPU2 CPU frequency (3.3 V nominal) 0.0937 12 12.3[21] MHz SLIMO Mode = 0.
FBLK5
Digital PSoC block frequency0
(5 V nominal) 048 49.2[20,22] MHz Refer to the section AC Digital
Block Specifications on page 26.
FBLK33
Digital PSoC block frequency
(3.3 V nominal) 024 24.6[22] MHz
F32K1 ILO frequency 15 32 64 kHz
F32K_U ILO untrimmed frequency 5 – 100 kHz
After a reset and before the M8C
starts to run, the ILO is not
trimmed. See the system resets
section of the PSoC Technical
Reference Manual for details on
this timing.
tXRST External reset pulse width 10 – – µs
DC24M 24 MHz duty cycle 40 50 60 %
DCILO ILO duty cycle 20 50 80 %
Step24M 24 MHz trim step size – 50 – kHz
Fout48M 48 MHz output frequency 46.8 48.0 49.2[20,21] MHz Trimmed. Using factory trim
values.
FMAX
Maximum frequency of signal on row input or
row output. – – 12.3 MHz
SRPOWER_UP Power supply slew rate – – 250 V/ms VDD slew rate during power-up.
tPOWERUP Time from end of POR to CPU executing code –16 100 ms
Power-up from 0 V. See the
system resets section of the
PSoC Technical Reference
Manual.
tjit_IMO
24-MHz IMO cycle-to-cycle jitter (RMS) [23] – 200 700 ps
24-MHz IMO long term N cycle-to-cycle jitter
(RMS) [23] – 300 900 ps N = 32
24-MHz IMO period jitter (RMS) [23] – 100 400 ps
Notes
19. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above
70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see “Errata” on page 43.
20. 4.75 V < VDD < 5.25 V.
21. 3.0 V < VDD < 3.6 V. Refer to the application note, Adjusting PSoC® Trims for 3.3V and 2.7V Operation - AN2012 for more information on trimming for operation at 3.3 V.
22. See the individual user module datasheets for information on maximum frequencies for user modules.
23. Refer to the application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information on jitter specifications.
Document Number: 38-12022 Rev. AC Page 24 of 47
CY8C21123/CY8C21223/CY8C21323
Table 23. 2.7-V AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
FIMO12 IMO frequency for 12 MHz 11.5 12012.7[24,25] MHz
Trimmed for 2.7 V operation
using factory trim values. See
Figure 11 on page 16.
SLIMO mode = 1.
FIMO6 IMO frequency for 6 MHz 5.5 66.5[24,25] MHz
Trimmed for 2.7 V operation
using factory trim values. See
Figure 11 on page 16.
SLIMO mode = 1.
FCPU1 CPU frequency (2.7 V nominal) 0.093 33.15[24] MHz 24 MHz only for
SLIMO mode = 0.
FBLK27 Digital PSoC block frequency (2.7 V nominal) 012 12.5[24,25] MHz Refer to the section AC Digital
Block Specifications on page 26.
F32K1 ILO frequency 832 96 kHz
F32K_U ILO untrimmed frequency 5 – 100 kHz
After a reset and before the M8C
starts to run, the ILO is not
trimmed. See the system resets
section of the PSoC Technical
Reference Manual for details on
this timing.
tXRST External reset pulse width 10 ––µs
DCILO ILO duty cycle 20 50 80 %
FMAX
Maximum frequency of signal on row input or row
output – – 12.3 MHz
SRPOWER_UP Power supply slew rate – – 250 V/ms VDD slew rate during power-up.
tPOWERUP Time from end of POR to CPU executing code –16 100 ms
Power-up from 0 V. See the
system resets section of the
PSoC Technical Reference
Manual.
tjit_IMO
12-MHz IMO cycle-to-cycle jitter (RMS)[26] – 400 1000 ps
12-MHz IMO long term N cycle-to-cycle jitter
(RMS)[26] – 600 1300 ps N = 32
12-MHz IMO period jitter (RMS)[26] – 100 500 ps
Notes
24. 2.4 V < VDD < 3.0 V.
25. Refer to the application note, Adjusting PSoC® Trims for 3.3V and 2.7V Operation - AN2012 for moreinformation on maximum frequency
for user modules.
26. Refer to the application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information on jitter specifications.
Document Number: 38-12022 Rev. AC Page 25 of 47
CY8C21123/CY8C21223/CY8C21323
AC General Purpose I/O Specifications
Tab l e 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Figure 13. GPIO Timing Diagram
AC Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical
parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the analog continuous time PSoC block.
Table 24. 5-V and 3.3-V AC GPIO Specifications
Symbol Description Min Typ Max Units Notes
FGPIO GPIO operating frequency 0 – 12 MHz Normal strong mode
tRiseF Rise time, normal strong mode, Cload = 50 pF 3 – 18 ns VDD = 4.5 V to 5.25 V, 10% to 90%
tFallF Fall time, normal strong mode, Cload = 50 pF 2 – 18 ns VDD = 4.5 V to 5.25 V, 10% to 90%
tRiseS Rise time, slow strong mode, Cload = 50 pF 10 27 – ns VDD = 3 V to 5.25 V, 10% to 90%
tFallS Fall time, slow strong mode, Cload = 50 pF 10 22 – ns VDD = 3 V to 5.25 V, 10% to 90%
Table 25. 2.7-V AC GPIO Specifications
Symbol Description Min Typ Max Units Notes
FGPIO GPIO operating frequency 0 – 3 MHz Normal strong mode
tRiseF Rise time, normal strong mode, Cload = 50 pF 6 – 50 ns VDD = 2.4 V to 3.0 V, 10% to 90%
tFallF Fall time, normal strong mode, Cload = 50 pF 6 – 50 ns VDD = 2.4 V to 3.0 V, 10% to 90%
tRiseS Rise time, slow strong mode, Cload = 50 pF 18 40 120 ns VDD = 2.4 V to 3.0 V, 10% to 90%
tFallS Fall time, slow strong mode, Cload = 50 pF 18 40 120 ns VDD = 2.4 V to 3.0 V, 10% to 90%
Table 26. 5-V and 3.3-V AC Amplifier Specifications
Symbol Description Min Typ Max Units
tCOMP1 Comparator mode response time, 50 mVpp signal centered on Ref – – 100 ns
tCOMP2 Comparator mode response time, 2.5 V input, 0.5 V overdrive – – 300ns
Table 27. 2.7-V AC Amplifier Specifications
Symbol Description Min Typ Max Units
tCOMP1 Comparator mode response time, 50 mVpp signal centered on Ref – – 600 ns
tCOMP2 Comparator mode response time, 1.5 V input, 0.5 V overdrive – – 300ns
TFallF
TFallS
TRiseF
TRi se S
90%
10%
GPIO
Pin
Document Number: 38-12022 Rev. AC Page 26 of 47
CY8C21123/CY8C21223/CY8C21323
AC Digital Block Specifications
Tab l e 28 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 28. 5-V and 3.3-V AC Digital Block Specifications
Function Description Min Typ Max Unit Notes
All functions
Block input clock frequency
VDD 4.75 V – – 50.4 MHz
VDD < 4.75 V – – 25.2 MHz
Timer
Input clock frequency
No capture, VDD 4.75 V – – 50.4 MHz
No capture, VDD < 4.75 V – – 25.2 MHz
With capture – – 25.2 MHz
Capture pulse width 50[27] ––ns
Counter
Input clock frequency
No enable input, VDD 4.75 V – – 50.4 MHz
No enable input, VDD < 4.75 V – – 25.2 MHz
With enable input – – 25.2 MHz
Enable input pulse width 50[27] ––ns
Dead Band Kill pulse width
Asynchronous restart mode 20 – – ns
Synchronous restart mode 50[27] ––ns
Disable mode 50[27] ––ns
Input clock frequency
VDD 4.75 V – – 50.4 MHz
VDD < 4.75 V – – 25.2 MHz
CRCPRS
(PRS
Mode)
Input clock frequency
VDD 4.75 V – – 50.4 MHz
VDD < 4.75 V – – 25.2 MHz
CRCPRS
(CRC
Mode)
Input clock frequency – – 25.2 MHz
SPIM Input clock frequency – – 8.2 MHz The SPI serial clock (SCLK) frequency is equal to
the input clock frequency divided by 2.
SPIS
Input clock (SCLK) frequency – – 4.1 MHz
The input clock is the SPI SCLK in SPIS mode.
Width of SS_negated between
transmissions 50[27] ––ns
Transmitter
Input clock frequency
The baud rate is equal to the input clock frequency
divided by 8.
VDD 4.75 V, 2 stop bits – – 50.4 MHz
VDD 4.75 V, 1 stop bit – – 25.2 MHz
VDD < 4.75 V – – 25.2 MHz
Receiver Input clock frequency
The baud rate is equal to the input clock frequency
divided by 8.
VDD 4.75 V, 2 stop bits – – 50.4 MHz
VDD 4.75 V, 1 stop bit – – 25.2 MHz
VDD < 4.75 V – – 25.2 MHz
Note
27. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 38-12022 Rev. AC Page 27 of 47
CY8C21123/CY8C21223/CY8C21323
Table 29. 2.7-V AC Digital Block Specifications
Function Description Min Typ Max Units Notes
All
functions Block input clock frequency – – 12.7 MHz 2.4 V < VDD < 3.0 V.
Timer Capture pulse width 100[28] – – ns
Input clock frequency, with or without capture – – 12.7 MHz
Counter
Enable input pulse width 100 – – ns
Input clock frequency, no enable input – – 12.7 MHz
Input clock frequency, enable input – – 12.7 MHz
Dead band
Kill pulse width:
Asynchronous restart mode 20 – – ns
Synchronous restart mode 100 – – ns
Disable mode 100 – – ns
Input clock frequency – – 12.7 MHz
CRCPRS
(PRS mode) Input clock frequency – – 12.7 MHz
CRCPRS
(CRC mode) Input clock frequency – – 12.7 MHz
SPIM Input clock frequency – – 6.35 MHz
The SPI serial clock (SCLK)
frequency is equal to the input clock
frequency divided by 2.
SPIS Input clock (SCLK) frequency – – 4.1 MHz
Width of SS_ Negated between transmissions 100 – – ns
Transmitter Input clock frequency – – 12.7 MHz The baud rate is equal to the input
clock frequency divided by 8.
Receiver Input clock frequency – – 12.7 MHz The baud rate is equal to the input
clock frequency divided by 8.
Note
28. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number: 38-12022 Rev. AC Page 28 of 47
CY8C21123/CY8C21223/CY8C21323
AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or
2.7 V at 25 °C and are for design guidance only.
Table 30. 5-V AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency 0.093 –24.6MHz
– High period 20.6 –5300 ns
– Low period 20.6 ––ns
– Power-up IMO to switch 150 ––µs
Table 31. 3.3-V AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency with CPU clock divide by 1 0.093 –12.3MHz
Maximum CPU frequency is 12 MHz at
3.3 V. With the CPU clock divider set to
1, the external clock must adhere to the
maximum frequency and duty cycle
requirements.
FOSCEXT
Frequency with CPU clock divide by 2 or
greater 0.186 –24.6MHz
If the frequency of the external clock is
greater than 12 MHz, the CPU clock
divider must be set to 2 or greater. In this
case, the CPU clock divider ensures
that the fifty percent duty cycle
requirement is met.
– High period with CPU clock divide by 1 41.7 –5300 ns
– Low period with CPU clock divide by 1 41.7 ––ns
– Power-up IMO to switch 150 ––µs
Table 32. 2.7-V AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency with CPU clock divide by 1 0.093 –6.06
0MHz
Maximum CPU frequency is 3 MHz at
2.7 V. With the CPU clock divider set to
1, the external clock must adhere to the
maximum frequency and duty cycle
requirements.
FOSCEXT
Frequency with CPU clock divide by 2 or
greater 0.186 –12.12MHz
If the frequency of the external clock is
greater than 3 MHz, the CPU clock
divider must be set to 2 or greater. In this
case, the CPU clock divider ensures
that the fifty percent duty cycle
requirement is met.
– High period with CPU clock divide by 1 83.4 –5300 ns
– Low period with CPU clock divide by 1 83.4 ––ns
– Power-up IMO to switch 150 ––µs
Document Number: 38-12022 Rev. AC Page 29 of 47
CY8C21123/CY8C21223/CY8C21323
AC Programming Specifications
Tab l e 33 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C
and are for design guidance only.
AC I2C Specifications
Tab l e 34 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 33. AC Programming Specifications
Symbol Description Min Typ Max Units Notes
tRSCLK Rise time of SCLK 1 – 20 ns
tFSCLK Fall time of SCLK 1 – 20 ns
tSSCLK Data set up time to falling edge of SCLK 40 – – ns
tHSCLK Data hold time from falling edge of SCLK 40 – – ns
FSCLK Frequency of SCLK 0 – 8 MHz
tERASEB Flash erase time (block) –10 –ms
tWRITE Flash block write time –80 –ms
tDSCLK3 Data out delay from falling edge of SCLK – – 50 ns 3.0 VDD 3.6.
tDSCLK2 Data out delay from falling edge of SCLK – – 70 ns 2.4 VDD 3.0.
tERASEALL Flash erase time (bulk) –20 –ms Erase all blocks and
protection fields at once.
tPROGRAM_HOT Flash block erase + flash block write time – – 180[30] ms 0 °C Tj 100 °C.
tPROGRAM_COLD Flash block erase + flash block write time – – 360[30] ms –40 °C Tj 0 °C.
Table 34. AC Characteristics of the I2C SDA and SCL Pins for VCC 3.0 V
Symbol Description Standard Mode Fast Mode Units
Min Max Min Max
FSCLI2C SCL clock frequency 0 100 0 400 kHz
tHDSTAI2C Hold time (repeated) START condition. After this
period, the first clock pulse is generated. 4.0 –0.6–µs
tLOWI2C Low period of the SCL clock 4.7 –1.3–µs
tHIGHI2C High period of the SCL clock 4.0 –0.6–µs
tSUSTAI2C Setup time for a repeated START condition 4.7 –0.6–µs
tHDDATI2C Data hold time 0 –0–µs
tSUDATI2C Data setup time02500–0100[29] –0ns0
tSUSTOI2C Setup time for STOP condition 4.0 –0.6–µs
tBUFI2C Bus free time between a STOP and START condition 4.7 –1.3–µs
tSPI2C Pulse width of spikes are suppressed by the input filter –– 0 50 ns
Notes
29. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSUDAT 250 ns must then be met. This automatically becomes
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line trmax + tSUDAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released.
30. For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the application note, Design Aids — Reading and Writing PSoC® Flash – AN2015 for more information on Flash APIs.
Document Number: 38-12022 Rev. AC Page 30 of 47
CY8C21123/CY8C21223/CY8C21323
Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus
Table 35. 2.7-V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode Not Supported)
Symbol Description Standard Mode Fast Mode Units
Min Max Min Max
FSCLI2C SCL clock frequency 0 100 ––kHz
tHDSTAI2C Hold time (repeated) START Condition. After this period, the first clock
pulse is generated.
4.0 – – –µs
tLOWI2C Low period of the SCL clock 4.7 – – –µs
tHIGHI2C High period of the SCL clock 4.0 – – –µs
tSUSTAI2C Setup time for a repeated START condition 4.7 – – –µs
tHDDATI2C Data hold time 0 – – –µs
tSUDATI2C Data setup time 250 – – –ns
tSUSTOI2C Setup time for STOP condition 4.0 – – –µs
tBUFI2C Bus free time between a STOP and START condition 4.7 –––µs
tSPI2C Pulse width of spikes are suppressed by the input filter. ––––ns
I2C_SDA
I2C_SCL
SSr SP
TBUFI2C
TSPI2C
TSUSTOI2C
TSUSTAI2C
TLOWI2C
THIGHI2C
THDDATI2C
THDSTAI2C
TSUDATI2C
START Condition Repeated START Condition STOP Condition
Document Number: 38-12022 Rev. AC Page 31 of 47
CY8C21123/CY8C21223/CY8C21323
Packaging Information
This section illustrates the packaging specifications for the CY8C21x23 PSoC device, along with the thermal impedances for each
package and minimum solder reflow peak temperature.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Packaging Dimensions
Figure 15. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066
51-85066 *I
Document Number: 38-12022 Rev. AC Page 32 of 47
CY8C21123/CY8C21223/CY8C21323
Figure 16. 16-Pin (150-Mil) SOIC
Figure 17. 16-Pin QFN with no E-Pad
51-85068 *E
001-09116 *J
Document Number: 38-12022 Rev. AC Page 33 of 47
CY8C21123/CY8C21223/CY8C21323
Figure 18. 20-pin SSOP (210 Mils) O20.21 Package Outline, 51-85077
Figure 19. 24-Pin (4 4) QFN (Punched)
51-85077 *F
51-85203 *D
Document Number: 38-12022 Rev. AC Page 34 of 47
CY8C21123/CY8C21223/CY8C21323
Figure 20. 24-Pin (4 4) QFN (Sawn)
Important Note For information on the preferred dimensions for mounting QFN packages, refer the application note,
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com.
Note that pinned vias for thermal conduction are not required for the low power 24, 32, and 48-pin QFN PSoC devices.
001-13937 *F
Document Number: 38-12022 Rev. AC Page 35 of 47
CY8C21123/CY8C21223/CY8C21323
Thermal Impedances
Solder Reflow Specifications
Tab l e 37 shows the solder reflow temperature limits that must not be exceeded.
Table 36. Thermal Impedances per Package
Package Typical JA [31]
8-pin SOIC 186 °C/W
16-pin SOIC 125 °C/W
16-pin QFN 46 °C/W
20-pin SSOP 117 °C/W
24-pin QFN[32] 40 °C/W
Table 37. Solder Reflow Specifications
Package Maximum Peak Temperature (TC)Maximum Time above TC – 5 °C
8-pin SOIC 260 °C 30 seconds
16-pin SOIC 260 °C 30 seconds
16-pin QFN 260 °C 30 seconds
20-pin SSOP 260 °C 30 seconds
24-pin QFN 260 °C 30 seconds
Notes
31. TJ = TA + POWER × JA
32. To achieve the thermal impedance specified for the QFN package, refer to “Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF)
Packages” available at http://www.amkor.com.
33. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5 °C with Sn-Pb or 245+/-5 °C with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
Document Number: 38-12022 Rev. AC Page 36 of 47
CY8C21123/CY8C21223/CY8C21323
Ordering Information
The following table lists the CY8C21x23 PSoC device’s key package features and ordering codes.
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
Table 38. CY8C21x23 PSoC Device Key Features and Ordering Information
Package Ordering Code Flash
(Bytes)
RAM
(Bytes)
Switch
Mode
Pump
Temperature
Range
Digital
PSoC
Blocks
Analog
Blocks
Digital I/O
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
8-Pin (150-Mil) SOIC CY8C21123-24SXI 4 K 256 No –40 °C to +85 °C 4 4 6 4 0 No
8-Pin (150-Mil) SOIC
(Tape and Reel) CY8C21123-24SXIT 4 K 256 No –40 °C to +85 °C 4 4 6 4 0 No
16-Pin (150-Mil) SOIC CY8C21223-24SXI 4 K 256 Yes –40 °C to +85 °C 4 4 12 8 0 No
16-Pin (150-Mil) SOIC
(Tape and Reel) CY8C21223-24SXIT 4 K 256 Ye s –40 °C to +85 °C 4 4 12 8 0 No
16-Pin (3 × 3) QFN with
no E-Pad CY8C21223-24LGXI 4 K 256 No –40 °C to +85 °C4 4 12 8 0Yes
20-Pin (210-Mil) SSOP CY8C21323-24PVXI 4 K 256 No –40 °C to +85 °C 4 4 16 8 0 Yes
20-Pin (210-Mil) SSOP
(Tape and Reel) CY8C21323-24PVXIT 4 K 256 No –40 °C to +85 °C 4 4 16 8 0 Yes
24-Pin (4 × 4) QFN
(Punched) CY8C21323-24LFXI 4 K 256 Ye s –40 °C to +85 °C 4 4 16 8 0 Yes
24-Pin (4 × 4) QFN
(Punched) (Tape and
Reel)
CY8C21323-24LFXIT 4 K 256 Ye s –40 °C to +85 °C 4 4 16 8 0 Yes
24-Pin (4 × 4) QFN
(Sawn) CY8C21323-24LQXI 4 K 256 Yes –40 °C to +85 °C 4 4 16 8 0 Yes
24-Pin (4 × 4) QFN
(Sawn) (Tape and Reel) CY8C21323-24LQXIT 4 K 256 Yes –40 °C to +85 °C 4 4 16 8 0 Yes
CY 8 C 21 xxx-24xx
Package Type: Thermal Rating:
SX = SOIC Pb-Free C = Commercial
PVX = SSOP Pb-Free I = Industrial
LGX = QFN (sawn, 3 × 3 mm), Pb-Free E = Extended
LFX = QFN (punched, 4 × 4 mm), Pb-Free
LQX = QFN (sawn, 4 × 4 mm), Pb-Free
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 38-12022 Rev. AC Page 37 of 47
CY8C21123/CY8C21223/CY8C21323
Acronyms
Acronyms Used
Tab l e 39 lists the acronyms that are used in this document.
Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x1 3, CY8C21x34,
CY8C21x23, CY7C64215, CY7C603 xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical
Reference Manual (TRM) (001-14463)
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Adjusting PSoC® Trims for 3.3V and 2.7V Operation - AN2012 (001-17397)
Understanding Datasheet Jitter Specificatio ns for Cypress Timing Products – AN5054 (001-14503)
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com.
Table 39. Acronyms Used in this Datasheet
Acronym Description Acronym Description
AC alternating current PCB printed circuit board
ADC analog-to-digital converter PGA programmable gain amplifier
API application programming interface POR power on reset
CMOS complementary metal oxide semiconductor PPOR precision power on reset
CPU central processing unit PRS pseudo-random sequence
CRC cyclic redundancy check PSoC® Programmable System-on-Chip
CT continuous time PWM pulse width modulator
DAC digital-to-analog converter QFN quad flat no leads
DC direct current SC switched capacitor
EEPROM electrically erasable programmable read-only
memory SLIMO slow IMO
GPIO general purpose I/O SMP switch mode pump
ICE in-circuit emulator SOIC small-outline integrated circuit
IDE integrated development environment SPITM serial peripheral interface
ILO internal low speed oscillator SRAM static random access memory
IMO internal main oscillator SROM supervisory read only memory
I/O input/output SSOP shrink small-outline package
IrDA infrared data association UART universal asynchronous reciever / transmitter
ISSP in-system serial programming USB universal serial bus
LVD low voltage detect WDT watchdog timer
MCU microcontroller unit XRES external reset
MIPS million instructions per second
Document Number: 38-12022 Rev. AC Page 38 of 47
CY8C21123/CY8C21223/CY8C21323
Document Conventions
Units of Measure
Tab l e 40 lists the units of measures.
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Table 40. Units of Measure
Symbol Unit of Measure Symbol Unit of Measure
dB decibels mH millihenry
°C degree Celsius µH microhenry
µF microfarad µs microsecond
pF picofarad ms millisecond
kHz kilohertz ns nanosecond
MHz megahertz ps picosecond
rt-Hz root hertz µV microvolt
kkilohm mV millivolt
ohm mVpp millivolts peak-to-peak
µA microampere V volt
mA milliampere W watt
nA nanoampere mm millimeter
pA pikoampere % percent
Glossary
active high 1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital
(ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create
software applications.
asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth 1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is
sometimes represented more specifically as, for example, full width at half maximum.
Document Number: 38-12022 Rev. AC Page 39 of 47
CY8C21123/CY8C21223/CY8C21323
bias 1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
block 1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
compiler A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.
crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less
sensitive to ambient temperature than other circuit components.
cyclic redundancy
check (CRC)
A calculation used to detect errors in data communications, typically performed using a linear feedback shift
register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band A period of time when neither of two or more signals are in their active state or in transition.
digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog
(DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)
converter performs the reverse operation.
Glossary (continued)
Document Number: 38-12022 Rev. AC Page 40 of 47
CY8C21123/CY8C21223/CY8C21323
duty cycle The relationship of a clock period high time to its low time, expressed as a percent.
emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
External Reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
Flash An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
OFF.
Flash block The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash
space that may be protected. A Flash block holds 64 bytes.
frequency The number of cycles or events per unit of time, for a periodic function.
gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated
Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in
the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building
control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high
with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage detect
(LVD)
A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold.
M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the Flash, SRAM, and register space.
master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave de vice.
Glossary (continued)
Document Number: 38-12022 Rev. AC Page 41 of 47
CY8C21123/CY8C21223/CY8C21323
microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal The reference to a circuit containing both analog and digital techniques and components.
modulator A device that imposes a signal on a carrier.
noise 1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator A circuit that may be crystal controlled and is used to generate a clock frequency.
parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
Phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port A group of pins, usually eight.
Power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is one type of
hardware reset.
PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
modulator (PWM)
An output in the form of duty cycle which varies as a function of the applied measurand.
RAM An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register A storage device with a specific capacity, such as a bit or byte.
reset A means of bringing a system back to a know state. See hardware reset and software reset.
ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial 1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
Glossary (continued)
Document Number: 38-12022 Rev. AC Page 42 of 47
CY8C21123/CY8C21223/CY8C21323
shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
slave device A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,
operating from Flash.
stop bit A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
VDD A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V.
VSS A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
Glossary (continued)
Document Number: 38-12022 Rev. AC Page 43 of 47
CY8C21123/CY8C21223/CY8C21323
Errata
This section describes the errata for the CY8C21x23 PSoC® programmable system-on-chip family. Details include errata trigger
conditions, scope of impact, available workarounds, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
CY8C21123 Qualification Status
Product Status: Production
CY8C21123 Errata Summary
The following table defines the errata applicability to available CY8C21123 family devices. An "X" indicates that the errata pertains to
the selected device.
Note Errata items, in the table below, are hyperlinked. Click on any item entry to jump to its description.
1. Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extremes
■Problem Definition
Asynchronous Digital Communications Interfaces may fail framing beyond 0 to 70 °C. This problem does not affect end-product
usage between 0 and 70 °C.
■Parameters Affected
The IMO frequency tolerance. The worst case deviation when operated below 0 °C and above +70 °C and within the upper
and lower datasheet temperature range is ±5%.
■Trigger Condition(S)
The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the data sheet limit of ±2.5% when
operated beyond the temperature range of 0 to +70 °C.
■Scope of Impact
This problem may affect UART, IrDA, and FSK implementations.
■Workaround
Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface.
■Fix Status
No silicon fix is planned. The workaround mentioned above should be used.
Part Number Ordering Information
CY8C21123
CY8C21123-24SXI
CY8C21123-24SXIT
CY8C21223-24SXI
CY8C21223-24SXIT
CY8C21323-24PVXI
CY8C21323-24PVXIT
CY8C21323-24LFXI
CY8C21323-24LFXIT
CY8C21323-24LQXI
CY8C21323-24LQXIT
Items Part Number Silicon Revision Fix Status
[1.] Internal Main Oscillator (IMO) Tolerance Deviation at
Temperature Extremes CY8C21123 ANo silicon fix is planned.
Workaround is required.
Document Number: 38-12022 Rev. AC Page 44 of 47
CY8C21123/CY8C21223/CY8C21323
Document History Page
Document Title: CY8C21123/CY8C21223/CY8C21323, PSoC® Programmable System-on-Chip™
Document Number: 38-12022
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 133248 NWJ See ECN New silicon and document (Revision **).
*A 208900 NWJ See ECN Add new part, new package and update all ordering codes to Pb-free.
*B 212081 NWJ See ECN Expand and prepare Preliminary version.
*C 227321 CMS Team See ECN Update specs., data, format.
*D 235973 SFV See ECN Updated Overview and Electrical Spec. chapters, along with 24-pin pinout.
Added CMP_GO_EN register (1,64h) to mapping table.
*E 290991 HMT See ECN
Update datasheet standards per SFV memo. Fix device table. Add part
numbers to pinouts and fine tune. Change 20-pin SSOP to CY8C21323. Add
Reflow Temp. table. Update diagrams and specs.
*F 301636 HMT See ECN DC Chip-Level Specification changes. Update links to new CY.com Portal.
*G 324073 HMT See ECN
Obtained clearer 16 SOIC package. Update Thermal Impedances and Solder
Reflow tables. Re-add pinout ISSP notation. Fix ADC type-o. Fix TMP register
names. Update Electrical Specifications. Add CY logo. Update CY copyright.
Make datasheet Final.
*H 2588457 KET / HMI /
AESA 10/22/2008 New package information on page 9. Converted datasheet to new template.
Added 16-Pin OFN package diagram.
*I 2618175 OGNE /
PYRS 12/09/2008
Added Note in Ordering Information Section. Changed title from PSoC
Mixed-Signal Array to PSoC Programmable System-on-Chip. Updated
‘Development Tools’ and ‘Designing with PSoC Designer’ sections on pages
5 and 6
*J 2682782 MAXK /
AESA 04/03/2009 Corrected 16 COL pinout.
*K 2699713 MAXK 04/29/2009 Minor ECN to correct paragraph style of 16 COL Pinout. No change in content.
*L 2762497 JVY 09/11/2009
Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as
follows:
Modified FIMO6 and TWRITE specifications.
Replaced TRAMP time) specification with SRPOWER_UP (slew rate) specifi-
cation.
Added note [11] to Flash Endurance specification.
Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, TPROGRAM_HOT, and
TPROGRAM_COLD specifications..
*M 2792630 TTO 10/26/2009 Updated ordering information for CY8C21223-24LGXI to indicate availability
of XRES pin.
*N 2901653 NJF 03/30/2010
Changed 16-pin COL to 16-pin QFN in the datasheet.
Added Contents.
Updated links in Sales, Solutions, and Legal Information
Updated Cypress website links.
Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings
Updated 5-V and 3.3-V AC Chip-Level Specifications
Updated Notes in Packaging Information and package diagrams.
Updated Ordering Code Definitions
*O 2928895 YJI 05/06/2010 No technical updates.
Included with EROS spec.
Document Number: 38-12022 Rev. AC Page 45 of 47
CY8C21123/CY8C21223/CY8C21323
*P 3044869 NJF 10/01/2010
Added PSoC Device Characteristics table.
Added DC I2C Specifications table.
Added F32K_U max limit.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Updated solder reflow specifications.
No specific changes were made to AC Digital Block Specifications table and
I2C Timing Diagram. They were updated for clearer understanding.
Updated Figure 13 since the labelling for y-axis was incorrect.
Template and styles update.
*Q 3263669 YJI 05/23/2011
Updated 16-pin SOIC and 20-pin SSOP package diagrams.
Updated Development Tool Selection and Designing with PSoC Designer
sections.
*R 3383787 GIR 09/26/2011
The text “Pin must be left floating” is included under Description of NC pin in
Table 6 on page 11.
Updated Table 37 on page 35 for improved clarity.
*S 3558729 RJVB 03/22/2012 Updated 16-pin SOIC package.
*T 3598261 LURE /
XZNG 04/24/2012 Changed the PWM description string from “8- to 32-bit” to “8- and 16-bit”.
*U 3649990 BVI / YLIU 06/19/2012 Updated description of NC pin as “No Connection. Pin must be left floating”
*V 3873870 UVS 01/18/2013
Updated Packaging Information:
spec 51-85068 – Changed revision from *D to *E.
spec 001-09116 – Changed revision from *F to *G.
spec 51-85203 – Changed revision from *C to *D.
*W 3993321 UVS 05/07/2013 Added Errata.
*X 4067216 UVS 07/18/2013
Added Errata footnotes (Note 19).
Updated Features:
Replaced 2.5% with 5% under “Precision, programmable clocking”.
Updated Electrical Specifications:
Updated AC Electrical Characteristics:
Updated AC Chip-Level Specifications:
Added Note 19 and referred the same note in FIMO24 parameter.
Updated minimum and maximum values of FIMO24 parameter.
Updated AC Digital Block Specifications:
Replaced all instances of maximum value “49.2” with “50.4” and “24.6” with
“25.2” in Ta bl e 2 8 .
Updated Packaging Information:
spec 51-85066 – Changed revision from *E to *F.
spec 001-09116 – Changed revision from *G to *H.
Updated to new template.
*Y 4479648 RJVB 08/20/2014
Updated Errata:
Updated CY8C21123 Errata Summary:
Updated details in “Fix Status” column in the table.
Updated details in “Fix Status” bulleted point below the table.
Document History Page (continued)
Document Title: CY8C21123/CY8C21223/CY8C21323, PSoC® Programmable System-on-Chip™
Document Number: 38-12022
Revision ECN Orig. of
Change
Submission
Date Description of Change
Document Number: 38-12022 Rev. AC Page 46 of 47
CY8C21123/CY8C21223/CY8C21323
*Z 4623500 DIMA 01/14/2015
Updated Pin Information:
Updated 20-Pin Part Pinout:
Updated Ta b le 5:
Added Note 6 and referred the same note in description of pin 5 and pin 10.
Updated 24-Pin Part Pinout:
Updated Ta b le 6:
Added Note 9 and referred the same note in description of pin 3, pin 9 and
pin 21.
Updated Packaging Information:
spec 51-85066 – Changed revision from *F to *G.
spec 51-85077 – Changed revision from *E to *F.
Completing Sunset Review.
AA 5090662 ARVI 01/18/2016
Updated Ordering Information, Ordering Code Definitions, and Errata.
Updated figure title in Figure 19.
Updated Ta b le 38 .
Updated Figure 15 (spec 51-85066 *G to *H) in Packaging Information.
Added Figure 20 (spec 001-13937 *F) in Packaging Information.
AB 5773393 AESATMP9 06/14/2017 Updated logo and copyright.
AC 5974328 ARVI 11/22/2017 Updated Figure 15 (spec 51-85066 *H to *I) in Packaging Information.
Document History Page (continued)
Document Title: CY8C21123/CY8C21223/CY8C21323, PSoC® Programmable System-on-Chip™
Document Number: 38-12022
Revision ECN Orig. of
Change
Submission
Date Description of Change
Document Number: 38-12022 Rev. AC Revised November 22, 2017 Page 47 of 47
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