Integrated Device Technology, Inc.
MILITARY TEMPERATURE RANGE MAY 1994
1994 Integrated Device Technology, Inc. 6.4 DSC-1027/4
CMOS STATIC RAMs
64K (16K x 4-BIT)
Added Chip Select and Output Controls
IDT7198S
IDT7198L
FEATURES:
• Fast Output Enable (
OE
) pin available for added system
flexibility
• Multiple Chip Selects (
CS
1,
CS
2) simplify system design
and operation
• High speed (equal access and cycle times)
— Military: 20/25/35/45/55/70/85ns (max.)
• Low power consumption
• Battery back-up operation—2V data retention (L version
only)
• 24-pin CERDIP, high-density 28-pin leadless chip carrier,
and 24-pin CERPACK packaging available
• Produced with advanced CMOS technology
• Bidirectional data inputs and outputs
• Inputs/outputs TTL-compatible
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT7198 is a 65,536 bit high-speed static RAM orga-
nized as 16K x 4. It is fabricated using IDT’s high-perfor-
mance, high-reliability technology—CMOS. This state-of-the-
art technology, combined with innovative circuit design tech-
niques, provides a cost effective approach for memory inten-
sive applications.
Access times as fast as 20ns are available. The IDT7198
offers a reduced power standby mode, ISB1, which is activated
when
CS
1 or
CS
2 goes HIGH. This capability decreases
power, while enhancing system reliability. The low-power
version (L) also offers a battery backup data retention capa-
bility where the circuit typically consumes only 30µW when
operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate
from a single 5V supply.
The lDT7198 is packaged in either a 24-pin ceramic DlP,
28-pin leadless chip carrier, and 24-pin CERPACK.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1
DECODER 65,536-BIT
MEMORY ARRAY
COLUMN I/O
2985 drw 01
INPUT
DATA
CONTROL
GND
A
0
WE
1
CS
1
A
13
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
OE
CS
2
FUNCTIONAL BLOCK DIAGRAM
6.4 2
IDT7198S/L
CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls MILITARY TEMPERATURE RANGE
MEMORY CONTROL
The IDT7198 64K high-speed CMOS static RAM incorpo-
rates two additional memory control features (an extra chip
select and an output enable pin) which offer additional ben-
efits in many system memory applications.
Both chip selects, Chip Select 1 (
CS
1) and Chip Select 2
(
CS
2), must be LOW to select the memory. If either chip select
is pulled HIGH, the memory will be deselected and remain in
the standby mode. This dual chip select feature (
CS
1,
CS
2)
also brings the convenience of improved system speeds to the
large memory designer by reducing the external logic required
to perform decoding.
PIN DESCRIPTIONS
Name Description
A0–A13 Address Inputs
CS
1Chip Select 1
CS
2Chip Select 2
WE
Write Enable
OE
Output Enable
I/O0–I/O3Data I/O
VCC Power
GND Ground
2985 tbl 01
TRUTH TABLE(1)
Mode
CS
1
CS
CS
2
WE
WE OE
OE
I/O Power
Standby H X X X High-Z Standby
Standby X H X X High-Z Standby
Read L L H L DOUT Active
Write L L L X DIN Active
Read L L H H High-Z Active
NOTE: 2985 tbl 02
1. H = VIH, L = VIL, X = don't care.
5
6
7
8
9
10
11
L28-2
26
25
24
23
13 14 15 16 17
32128 27
INDEX
A
5
A
6
A
12
A
11
A
10
CS
12
22
21
A
3
A
4
2985 drw 03
A
7
A
8
20
19
18
A
9
4
1
OE
GND
CS
2
WE
A
2
A
1
A
0
V
CC
NC
NC
NC
A
13
NC
I/O
3
I/O
2
I/O
1
I/O
0
LCC
TOP VIEW
PIN CONFIGURATIONS
2985 drw 02
5
6
7
8
9
10
11
12
A
01
2
3
4
24
23
22
21
20
19
18
17
D24-1
E24-1
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
CS
V
CC
WE
A
12
A
11
A
10
16
15
OE
GND
A
9
A
13
1
CS
2
16
15
I/O
3
I/O
2
I/O
1
I/O
0
DIP/SOJ/CERPACK
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Mil. Unit
VTERM Terminal Voltage –0.5 to +7.0 V
with Respect to GND
TAOperating Temperature –55 to +125 °C
TBIAS Temperature –65 to +135 °C
Under Bias
TSTG Storage Temperature –65 to +150 °C
PTPower Dissipation 1.0 W
IOUT DC Output Current 50 mA
NOTE: 2985 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
6.4 3
IDT7198S/L
CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls MILITARY TEMPERATURE RANGE
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.2 — 6.0 V
VIL Input Low Voltage –0.5(1) — 0.8 V
NOTE: 2985 tbl 05
1. VIL (min.) = -3.0V for pulse width less than 20ns, once per cycle.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade Ambient Temperature GND VCC
Military –55°C to +125°C 0V 5V ± 10%
2985 tbl 06
CAPACITANCE (TA = +25°C, f = 1.0MHz, V CC = 0V)
Symbol Parameter(1) Conditions Max. Unit
CIN Input Capacitance VIN = 0V 7 pF
CI/O I/O Capacitance VOUT = 0V 7 pF
NOTE: 2985 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10%, Military Temperature Range Only IDT7198S IDT7198L
Symbol Parameter Test Condition Min. Max. Min. Max. Unit
|ILI| Input Leakage Current VCC = Max., — 10 — 5 µA
VIN = GND to VCC
|ILO| Output Leakage Current VCC = Max.,
CS
= VIH, —10 — 5µA
VOUT = GND to VCC
VOL Output Low Voltage IOL = 10mA, VCC = Min. 0.5 — 0.5 V
IOL = 8mA, VCC = Min. — 0.4 — 0.4
VOH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — 2.4 — V
2985 tbl 07
Figure 1. AC Test Load Figure 2. AC Test Load
(for tCLZ1, 2, tOLZ, tCHZ1, 2, tOHZ, tOW and tWHZ)
*Includes scope and jig capacitances
2985 drw 06
480Ω
5pF*
255Ω
DATAOUT
5V
2985 drw 05
480Ω
30pF*
255Ω
DATAOUT
5V
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2
2985 tbl 10
6.4 4
IDT7198S/L
CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls MILITARY TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE
(L Version Only) VLC = 0.2V, VHC = VCC - 0.2V Typ. (1) Max.
VCC @VCC @
Symbol Parameter Test Condition Min. 2.0v 3.0V 2.0V 3.0V Unit
VDR VCC for Data Retention — 2.0 — — — — V
ICCDR Data Retention Current — 10 15 600 900 µA
tCDR(3) Chip Deselect to Data
CS
1 or
CS
2 ≥ VHC 0————ns
Retention Time VIN ≥ VHC or ≤ VLC
tR(3) Operation Recovery Time tRC(2) ————ns
|ILI|(3) Input Leakage Current — — — 2 2 µA
NOTES: 2985 tbl 09
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V) 7198S20 7198S25 7198S35 7198S45 7198S55/70 7198S85
7198L20 7198L25 7198L35 7198L45 7198L55/70 7198L85
Symbol Parameter Power Military Military Military Military Military Military Unit
ICC1 Operating Power S 105 105 105 105 105 105 mA
Supply Current,
CS
1 and
CS
2 ≤ VIL, Outputs Open L 80 80 80 80 80 80
VCC = Max., f = 0(2)
ICC2 Dynamic Operating S 160 155 140 140 140 140 mA
Current,
CS
1 and
CS
2 ≤ VIL, Outputs Open L 130 120 115 110 110 105
VCC = Max., f = fMAX(2)
ISB Standby Power Supply S 70 60 50 50 50 50 mA
Current (TTL Level),
CS
1
or
CS
2 ≥ VIH, VCC = Max., L 50 40 35 35 35 35
Outputs Open, f = fMAX(2)
ISB1 Full Standby Power S 25 20 20 20 20 20 mA
Supply Current (CMOS
Level)
CS
1 or
CS
2 ≥ VHC,
VCC= Max., VIN ≥ VHC or L 1.5 1.5 1.5 1.5 1.5 1.5
VIN ≤ VLC, f = 0(2)
NOTES: 2985 tbl 06
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
LOW VCC DATA RETENTION WAVEFORM
2985 drw 04
DATA
RETENTION
MODE
4.5V 4.5V
V
DR
≥
2V
V
IH
V
IH
t
R
t
CDR
V
CC
CS V
DR
6.4 5
IDT7198S/L
CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls MILITARY TEMPERATURE RANGE
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continuously selected,
CS
1 is LOW,
CS
2 is LOW.
3. Address valid prior to or coincident with
CS
1 and or
CS
2 transition LOW.
4.
OE
is LOW.
5. Transition is measured ±200mV from steady state voltage.
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS
CS
1, 2
DATAOUT
OE
2985 drw 07
tRC
tAA tOH
tACS1, 2
tCLZ1, 2 (5) tCHZ1, 2(5)
tOE
tOLZ(5) tOHZ(5)
DATA VALID
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, Military Temperature Range)
7198S20 7198S25 7198S35/45 7198S55 7198S70 7198S85
7198L20 7198L25 7198L35/45 7198L55 7198L70 7198L85
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time 20 — 25 — 35/45 — 55 — 70 — 85 — ns
tAA Address Access Time — 19 — 25 — 35/45 — 55 — 70 — 85 ns
tACS1,2(1) Chip Select-1,2 Access Time — 20 — 25 — 35/45 — 55 — 70 — 85 ns
tCLZ1,2(2) Chip Select-1,2 to Output in Low-Z 5 — 5 — 5 — 5 — 5 — 5 — ns
tOE Output Enable to Output Valid — 9 — 11 — 20/25 — 35 — 45 — 55 ns
tOLZ(2) Output Enable to Output in Low-Z 5 — 5 — 5 — 5 — 5 — 5 — ns
tCHZ1,2(2) Chip Select 1,2 to Output in High-Z — 8 — 10 — 14 — 20 — 25 — 30 ns
tOHZ(2) Output Disable to Output in High-Z — 8 — 9 — 15 — 20 — 25 — 30 ns
tOH Output Hold from Address Change 5 — 5 — 5 — 5 — 5 — 5 — ns
tPU(2) Chip Select to Power Up Time 0 — 0 — 0 — 0 — 0 — 0 — ns
tPD(2) Chip Deselect to Power Down Time — 20 — 25 — 35/45 — 55 — 70 — 85 ns
NOTES: 2985 tbl 11
1. Both chip selects must be active low for the device to be selected.
2. This parameter is guaranteed by device characterization but is not production tested.
6.4 6
IDT7198S/L
CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
ADDRESS
DATAOUT
2985 drw 08
tRC
tAA tOH
tOH
DATA VALIDPREVIOUS DATA VALID
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
DATA
OUT
CS
1,2
I
CC
I
SB
V
CC
SUPPLY
CURRENT
2985 drw 09
t
ACS1, 2
(5)
t
CLZ1, 2
(5)
t
CHZ1, 2
t
PD
t
PU
DATA VALID
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continuously selected,
CS
1 is LOW,
CS
2 is LOW.
3. Address valid prior to or coincident with
CS
1 and or
CS
2 transition LOW.
4.
OE
is LOW.
5. Transition is measured ±200mV from steady state voltage.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
7198S20 7198S25 7198S35/45 7198S55 7198S70 7198S85
7198L20 7198L25 7198L35/45 7198L55 7198L70 7198L85
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle
tWC Write Cycle Time 17 — 20 — 30/40 — 50 — 60 — 75 — ns
tCW1,2(1) Chip Select to End-of-Write 17 — 20 — 25/35 — 50 — 60 — 75 — ns
tAW Address Valid to End-of-Write 17 — 20 — 25/35 — 50 — 60 — 75 — ns
tAS Address Set-up Time 0 — 0 — 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 17 — 20 — 25/35 — 50 — 60 — 75 — ns
tWR1,2 Write Recovery Time 0 — 0 — 0 — 0 — 0 — 0 — ns
tWHZ(2) Write Enable to Output in High-Z — 5/6 — 7 — 10/15 — 25 — 30 — 40 ns
tDW Data Valid to End-of-Write 10 — 13 — 15/20 — 25 — 30 — 35 — ns
tDH Data Hold Time 0 — 0 — 0 — 0 — 0 — 0 — ns
tOW(2) Output Active from End-of-Write 5 — 5 — 5 — 5 — 5 — 5 — ns
NOTES: 2985 tbl 12
1. Both chip selects must be active low for the device to be selected.
2. This parameter is guaranteed by device characterization but is not production tested.
6.4 7
IDT7198S/L
CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
WE
CONTROLLED TIMING)(1, 2, 3, 7)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CS
CONTROLLED TIMING)(1)
NOTES:
1.
WE
,
CS
1 or
CS
2 must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW
WE
, a LOW
CS
1 and a LOW
CS
2.
3. tWR is measured from the earlier of
CS
1,
CS
2 or
WE
going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, outputs remain in the high-impedance state.
6. Transition is measured ±200mV from steady state.
7. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + t DW) to allow the I/O drivers to turn off and data
to be placed on the required tDW. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
CS
1, 2
DATA
IN
ADDRESS
WE
DATA
OUT
OE
2985 drw 10
t
AW
t
WR
t
DW
t
WC
t
WP
t
DH
t
WHZ
t
OW
t
AS
(6) (6)
(4)(4)
(7)
DATA VALID
CS
1, 2
DATAIN
ADDRESS
WE
t
tWR
2985 drw 11
tAW
tDW
tWC
tCW
tDH
tAS
DATA VALID
6.4 8
IDT7198S/L
CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls MILITARY TEMPERATURE RANGE
ORDERING INFORMATION
X
Power
XX
Speed
X
Package
B
Process/
Temperature
Range
BMilitary (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
D
L
E
300 mil Ceramic DIP (D24-1)
Leadless Chip Carrier (L28-2)
CERPACK (E24-1)
20
25
35
45
55
70
85
Military Only
Military Only
Military Only
Military Only
Military Only
Military Only
Military Only
S
LStandard Power
Low Power
IDT7198
Speed in nanoseconds
2985 drw 12
Device
Type