June 25, 2002, Issue 2 Part Numbers G2216-208-041PF B2 (SDSL 2B1Q) G2214-208-041DF B2 (SDSL CAP) G2237-208-041PT B2 (SHDSL/HDSL2) G2237-208-041PT C1 (SHDSL/HDSL2) XDSL2TM SDSL, HDSL2, or SHDSL - ILD2 Dual-Channel, Low Power, Programmable Transceiver with Integrated Framer and Line Drivers Overview Features The GlobespanVirata(R) XDSL2TM Digital Subscriber Line (DSL) chip sets provide low power, high density solutions for 2-wire DSL equipment. These chip sets are fully programmable and field upgradeable eliminating the risk of product obsolescence and accelerating the time-to-market for new network services. The GlobespanVirata(R) XDSL2TM DSL chip sets are fully interoperable with multi-vendor DSL chip set solutions. This interoperability enables dynamic interworking of multiple vendor DSL solutions with the capability to interoperate with products that conform to ANSI and ETSI DSL standards. * GlobespanVirata's unique hardware platform supports multiple dual-channel applications including SDSL, HDSL2, and SHDSL, using population options for optimization. * * The XDSL2 DSL chip sets incorporate two DSL bit pumps plus framing into a three-chip solution comprised of a dualchannel digital signal processor (DSP) with built-in framer and two Analog Front Ends each with an Integrated Line Driver (ILD2). The XDSL2 chip sets interface directly with off-the-shelf T1/ E1 transceivers and Nx64 multiplexing, eliminating the need for a separate DSL framer to combine and format the two DSL channels into a standard interface. GlobespanVirata's DSL XDSL2 chip sets deliver two channels of full duplex transmission up to 2320 kb/s, depending on the application. * * * * * * * * * * * Data Sheet Dual-channel DSP with framer that fully integrates 2 separate DSL chips into a single device Two AFEs, each with an integrated differential line driver 2B1Q, CAP, or PAM line codes Supports dual-channel symmetric data rates of 144 kb/s to 2320 kb/s (depending on the application) Supports IDSL with optional data interface rates of 64 kb/s, 128 kb/s, and 144 kb/s Offers physical layer interoperability with competitive solutions Glueless interface to popular microprocessors Transmission compliant with ETSI TS 101 135, ITU-T G.991.1, and ANSI TR-28 for single pair 2B1Q and CAP, ANSI T1.418 for HDSL2 and ITU-T G.991.2 for SHDSL Reference design compatible with Bellcore GR-1089, IEC 60950, UL 1950, ITU-T K.20 and K.21 Built-in framer provides easy access to EOC and indicator bits (framing can be bypassed completely for 2-channel independent operation) Interfaces directly with off-the-shelf single-channel T1/E1 transceivers ATM UTOPIA Level 1 and 2 interface A single oscillator and hybrid topology supports all speeds +3.3V and +5V power supplies The high density XDSL2 dual-channel DSL chip sets are ideal for CO applications, while single-channel versions with integrated framer are also available for CPE applications. TDATA (A/B) TClock (A/B) Frame Pulse (A/B) Customer Interface RDATA (A/B) Rclock (A/B) Frame Pulse (A/B) ILD2 Dual Channel DSP w/Framer Processor Interface ILD2 Figure 1. Block Diagram of XDSL2TM DSP with Two Single-Channel ILD2s GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet Introduction The GlobespanVirata DSL chip sets support applications ranging from remote network access, digital pair gain, video conferencing, and cellular base station land-line connectivity, for T1/E1 services. Up to 36 voice circuits may be provisioned over a single copper pair. June 25, 2002 GlobespanVirata Transceiver System Overview * The GlobespanVirata XDSL2TM DSL chip sets consist of a dual-channel DSP with an on-chip framer, and two single-channel AFEs (with ILD2). * The single-channel ILD2s filter and digitize the signal received on the telephone line and for the transmit side, generate analog signals from the digital data and filter the analog signals to create the 2B1Q, CAP or PAM transmit signal (depending on the line code). * The GlobespanVirata Windows-based Host Interface Program (WHIP) is offered as part of the GlobespanVirata transceiver system development package for SDSL 2B1Q, HDSL2, and SHDSL applications. WHIP allows you to test and debug your product design with the click of a mouse. This graphical interface allows you to send commands, perform trace and debug procedures, and initiate a startup on both the CO and CP units. WHIP offers complete flexibility and modularity - you can rearrange windows and toolbars to suit your preferences and design requirements. * SDSL CAP applications are offered the GlobespanVirata Host Interface Program (HIP) software as part of the GlobespanVirata transceiver system development package. The PC-based HIP software provides a PC interface to the host. HIP allows the host to run scripts to obtain and manipulate data, test performance, and debug the software. No additional software or special PC hardware or tools are required. Customers who use HIP with their host processor receive the benefits of faster diagnosis and specialized assistance from the GlobespanVirata staff. Example Applications * * * * Compatibility with voice/data pair gain systems Cellular and microcellular systems T1/E1 and fractional T1/E1 DSL transceiver Wireless base station connectivity Related Materials To accelerate time-to-market, GlobespanVirata offers our customers a comprehensive Design Guide which includes details on planning, layout, testing, debugging, and expert tips and recommendations for building a successful DSL product. The Design Guide is distributed as part of a Design Package which includes firmware, transceiver schematics, sample code, transceiver layout Gerber files, and Bill of Materials. For rapid prototyping, Quick Kits are available. These Quick Kits contain all transceiver design BOM components in kit form so there's no component lead time delay. The Super GlobespanVirata Development System (SGDSTM), an easy-to-use evaluation and development platform designed to support all GlobespanVirata xDSL transceiver solutions, is also available for early product development. The SGDS also provides an interface to the GlobespanVirata Microsoft(R) Windows(R) - based Host Interface Program (WHIP). When the SGDS is teamed with WHIP, product evaluation, testing and debugging is achieved with the click of a mouse. 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Architecture * The interface between the Host and the transceiver consists of the following: * * * * * Transmission Interface (data, clock and synchronization signals) Control Interface (microprocessor compatible) Diagnostic Interface Power Interface Loop Interface System timing is derived from a free running oscillator in the transceiver of the central office (CO). At the customer premises end (CPE), the CPE derives a clock from the received line signal and provides this clock to the CPE transmitter. The dual-channel chip set also supports Network Timing Recovery (NTR) at the CO end. With this feature enabled, the CO unit will accept a clock at 8 kHz ( 100 ppm) as an input and the STU-R will output a clock that is phase locked to the CO clock. The NTR clock should have a duty cycle of 45-55%. Note that this feature is only available with an UTOPIA interface. The DSL transceiver supports both T1 and E1 rates, and fractional rates. Transceiver States The following is a list of the possible states that the DSL transceiver can be in: * IDLE mode, where the transceiver is not attempting to start up, pass data, or perform tests * TEST mode, where the transceiver is either in local analog loopback or local digital loopback and is not passing user data * STARTUP mode (SDSL only), where the transceiver is attempting a startup of the DSL connection, prior to entering DATA mode * HANDSHAKE mode (HDSL2 and SHDSL), where a link is established between the CO unit and the CPE unit * TRAINING mode (HDSL2 and SHDSL), where the transceiver is attempting a startup, prior to entering DATA mode DO-009643-DS, Issue 2 DATA mode, where the transceiver has started up and trained and is capable of passing user data Software Interface A microprocessor interface that uses simple read/write drivers provides direct access to the GlobespanVirata chip set--eliminating the need for complicated register maps and advanced programming. These drivers allow the Host to select rates, adjust transmit power, read signal quality, and perform a variety of other tasks which include reporting the current operational status of the transceiver. To configure and control the transceiver, GlobespanVirata provides hardware-dependent driver examples and GlobespanVirata supplied transceiver software modules (TSMs). The TSMs have the ability to allow a single CPU in the Host to control multiple transceivers. This could be a potential cost savings for arrangements where it might be advantageous to put multiple transceivers on one card, such as at the CO. NOTE: You will not need a register map of the DSP, as this information is not required to successfully design and implement an STU. As discussed previously, access to the DSP is provided through hardwaredependent I/O routines and GlobespanVirata provided TSMs. GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 3 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet Transceiver Power Up Sequence Figure 2 describes a typical sequence from power up to DATA mode for a transceiver. After power is applied to both the Host and the transceiver, the Host calls the InitXCVR_CS() and InitXCVR() routines to initialize transceiver variables and to initialize the DSP/ Framer. Power Up Data Mode Power Up Activities Retrain Abort InitXCVR_CS() Reset DSP Power Up/ Reset DSP Next, the Host calls the SetParamXCVR() routine to set up the parameters that are appropriate for start up of the transceiver. InitXCVR() Idle Mode SetParamXCVR() The SetParamFramer() routine is called by the Host to initialize framer options. Idle Mode Optional SetParamFramer() Set all framer options Start Up Activities Idle Mode DSP/Framer Interrupt Received Optional SStatusXCVR() Host Processes GTI_ACTIVE ExecuteXCVR() DETAIL A GTI_COMPLETE_PASS DETAIL A: FAILED STARTUP May occur anytime before Data Mode. IDLE MODE HANDSHAKE TRAINING DSP INTERRUPTS STARTUP MODE FRAMER SYNC* After setting up the transceiver parameters, the Host calls the ExecuteXCVR() routine to execute the command that was set up using the SetParamXCVR() routine. With a successful completion of the ExecuteXCVR() routine, the transceiver will now be in DATA mode. The SStatusXCVR() routine is used to track performance and to obtain information from the transceiver about what state the transceiver is in (i.e., monitor start-up, check signal quality, etc.). Data Mode BOOT LOAD (not timed) June 25, 2002 DATA MODE FRAMER INTERRUPTS * Only if PLL is enabled Figure 2. Typical Transceiver Power Up/Start Up Sequence Setting Up the Command Parameters [SetParamXCVR()] The routine SetParamXCVR() processes the parameter array structure that will be executed when the ExecuteXCVR() routine is called. The parameter structure will be similar to the following start-up example: struct PARAM_XCVR_ARRAY Items; Items.length = GTI_NUM_OF_CMD_PARAMETERS Items.item[GTI_ACTION_ITEM]=GTI_STARTUP_REQ; Items.item[GTI_MODE_ITEM]=GTI_CO; Items.item[GTI_POWER_SCALE_ITEM]=GTI_DEFAULT_SCALE; Items.item[GTI_FRAMER_TYPE_ITEM]= GTI_UTOPIA_L2; . . . 4 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Table 1 describes the example arguments to the SetParamXCVR() routine when performing start-up. This is only a sample subset of possible parameters, provided to illustrate how easy it is to work with the GlobespanVirata chip sets. Table 1. Example SetParamXCVR() Structure Parameter GTI_ACTION_ITEM Function The action GTI_STARTUP_REQ begins start-up, which, upon successful completion, results in the transceiver changing into DATA mode. Checking the Transceiver Status [SStatusXCVR()] The SStatusXCVR() routine can be executed when in DATA mode, utilizing minimal processing power. To further illustrate the ease of programming GlobespanVirata chip sets, Table 2 supplies a few examples of SStatusXCVR(). Table 2. Example SStatusXCVR() Parameters Parameter Function GTI_XMIT_POWER This action returns the transmitted power. GTI_MODE_ITEM Mode describes which transceiver the Host is talking to, the CO or CP. GTI_START_PROGRESS The current detailed start-up state of the transceiver is returned. GTI_POWER_SCALE_ITEM Allows the transmit power to be set in small increments. GTI_BERT_ERROR The number of bit errors detected during the 511 BERT test is returned. GTI_RECEIVER_GAIN Total receiver gain setting can be calculated using the return values from this action. GTI_FRAMER_TYPE_ITEM The framing modes are interface specific. Possible arguments for framing modes, depending on the customer interface, include: No Framing, UTOPIA Level 1, UTOPIA Level 2, T1, E1, and nxDS0 (with the ability to choose continuous DS0 blocks). DO-009643-DS, Issue 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 5 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 System Power Requirements The 144-pin Dual-channel DSP/Framer chip requires +3.3V (see Table 14 on page 16 for tolerance), and the two ILD2 chips require +3.3V (5%) as well as +5V (5%). Power requirements, including transceiver power consumption, have a tolerance of 5%. The maximum peak-to-peak ripple and noise voltage is 50 mV for all supplies. The transceiver obtains its power from the power feed in the Host through the power interface. Table 3, Table 4, Table 5, and Table 7 provide power requirements for the 144-pin Dual-channel DSP. Table 3. Typical SDSL 2B1Q System Power Consumption Per Channel (DSP/Framer in a 144 LPQ2) Line Rate (Kb/s) 144 272 Drain Current (mA) 3.3VD DSP & ILD2 5VA ILD2 75 85 105 85 Table 4. Typical SDSL CAP System Power Consumption Per Channel (DSP/Framer in a 144 TQFP) Line Rate (Kb/s) Power/Port (mW) Drain Current (mA) 3.3VD DSP & ILD2 5VA ILD2 Power/Port (mW) 673 144 75 90 698 772 272 80 90 714 115 105 905 110 90 813 400 528 115 90 830 528 145 115 1055 784 160 90 978 784 145 115 1055 1011 1040 145 115 1055 1552 155 115 1087 400 1040 170 90 1168 210 90 1143 1552 235 95 1251 2064 165 120 1145 2064 250 95 1300 2320 185 120 1210 2320 280 95 1400 NOTE: NOTE: 1. Power per channel based on dual-channel operation 1. Power per channel based on dual-channel operation 2. Based on customer schematic: G-02-2302-1006C-02 using 1:2 transformer 2. Based on customer schematic: G-02-2302-1006C-03 using 1:4 transformer Add 30 mA at 5VA for unified designs based on SHDSL population option G-02-2302-1006C-03 using 1:4 transformer or HDSL2 population option G-02-2302-1006C-03 using 1:5.4 transformer 3. Transmit power: 13.5 dbm (nominal at 2320kb/s) 4. Measured during activation and data mode 3. Transmit power: 13.5 dbm (nominal at all rates) 4. Measured during activation and data mode 6 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Table 5. Typical HDSL2 System Power Consumption Per Port (DSP/Framer in a 144 LPQ2) Table 7. Typical SHDSL System Power Consumption Per Channel (DSP/Framer in a 144 LPQ2) Drain Current (mA) Line Rate (Kb/s) T1 (1.552) 3.3VD DSP & ILD2 5VA ILD2 270 150 Drain Current (mA) Power/Port (mW) 1681 NOTE: 1. Power per channel based on dual-channel operation 2. Based on customer schematic: G-02-2302-1006C-01 using 1:5.4 transformer 3. Transmit power: 16.8 dbm (nominal) Table 6. Maximum Junction Temperature TJ Maximum Line Rate (Kb/s) Power/Port (mW) 3.3VD DSP & ILD2 5VA ILD2 144 100.0 125.0 955.0 200 105.0 125.0 971.5 208 105.0 125.0 971.5 272 120.0 125.0 1021.0 392 130.0 125.0 1054.0 400 130.0 125.0 1054.0 528 135.0 125.0 1070.5 776 160.0 125.0 1153.0 784 160.0 125.0 1153.0 1040 180.0 125.0 1219.0 1168 185.0 125.0 1235.5 1552 225.0 130.0 1392.5 2056 245.0 130.0 1458.5 2064 245.0 130.0 1458.5 2312 270.0 130.0 1541.0 2320 270.0 130.0 1541.0 125 oC NOTE: 1. Power per channel based on dual-channel operation 2. Based on customer schematic: G-02-2302-1006C-03 using 1:4 transformer 3. Transmit power: 13.5 dbm (nominal at all rates) 4. Measured during activation and data mode 5. All Nx64 payload rates are supported (where N = 3 through 36). The line rates listed in Table 7 are a few typical data points Electrical Interface Specification All processor interfaces, customer clock and data, and diagnostic interface inputs and outputs associated with the 144-pin DSP Core are compatible with 5V CMOS and TTL logic, as well as 3.3V CMOS logic. While the DSP is a 3.3V device, all the above inputs are designed to be 5V tolerant. The Control Interface supports multiplexed, non-multiplexed, and Motorola processor interface modes. DO-009643-DS, Issue 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 7 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Performance GlobespanVirata has rigorously tested the performance of the DSL chip sets, with the results detailed in Table 8, Table 9, Table 10 and Table 11. Table 8. SDSL 2B1Q Performance Specifications (Reach in kft and km) Table 10. HDSL2 Performance Specifications (Reach in kft and km) No Noise Line Rate (kb/s) 24 AWG No Noise 26 AWG kft km kft km 144 25.4 7.7 21.0 6.4 272 23.6 7.2 19.5 5.9 400 22.4 6.8 17.3 5.2 528 21.3 6.5 16.1 4.9 784 19.1 5.8 15.2 4.6 1040 17.6 5.4 14.4 4.4 1168 15.9 4.8 13.8 4.2 1552 13.3 4.1 12.7 3.9 2064 11.8 3.6 11.1 3.4 2320 11.3 3.4 10.9 3.3 Line Rate (kb/s) T1 (1.552 kb/s) kft 8 km km kft km 18.0 5.5 13.5 4.1 Line Rate (kb/s) 26 AWG kft km 144 26.0 7.9 200 21.4 6.5 392 19.9 6.0 520 18.7 5.7 776 17.5 5.3 1032 16.6 5.1 1168 15.8 4.8 km 1544 14.0 4.2 13.0 3.9 12.5 3.8 26 AWG kft kft No Noise No Noise 24 AWG 26 AWG Table 11. SHDSL Performance Specifications (Reach in kft and km) Table 9. SDSL CAP Performance Specifications (Reach in kft and km) Line Rate (kb/s) 24 AWG 144 30.4 9.2 21.4 6.5 2056 272 30.3 9.2 20.3 6.1 2312 400 28.7 8.7 18.8 5.7 528 26.2 7.9 17.0 5.3 784 23.1 7.0 15.8 4.8 1040 22.4 6.8 15.5 4.7 1552 19.4 5.9 13.9 4.2 2064 17.2 5.2 12.2 3.7 2320 15.8 4.8 11.7 3.5 NOTE: All Nx64 payload rates are supported (where N= 3 through 36). The line rates listed in Table 11 are a few typical data points. GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 DO-009643-DS, Issue 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions To Data Interface B To Data Interface A Host Processor TXDB TXCKB TXSOFB RXSOFB RXDB RXCKB RXDA RXCKA TXDA TXCKA TXSOFA RXSOFA Address/ Data Bus Control Signals Framer Host Processor Interface RDN, WRN INTN AD[7:0] Level Display Monitor Diagnostic Interface DualChannel DSP BPDO5 BPDO4 APDI1 BPDO2 BPDO1 BPDO0 BPDI1 BPDI5 APDO5 APDO4 APDI0 APDO2 APDO1 APDO0 APDI5 APDI3 ILD2 DACB Q0A Q1A MCLK CSD DACA Q0B Q1B ILD2 DACB Q0A Q1A MCLK CSD DACA Q0B Q1B Transformer Transformer Loop Loop June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet Figure 3. XDSL2TM Dual-Channel DSP with Integrated Line Driver Functional Diagram 9 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 VDD XSB0A XSB1A POP2A SOCK ISO QSO PIP/POP/RXA0 PIP/POP/RXEN TXSOFB/TXEN PIP/POP/TXA0 VSS AVSS XTLO XTLI AVSS AVDD VSS RXSOFA/RXSOC TXSOFA/TXSOC DP13 DP14 DP11 DP12 DP15 TBAUD/TXCLAV DP6 DP5 DP4 DP3 DP7 DP1 RXSOFB/RXCLAV DP0 VSS VDD 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 Dual-Channel DSP/Framer Specifications D2ACKA 1 108 DP10 APDO0 2 107 DP9 APDO1 3 106 DP8 APDO2 4 105 RXCLK APDO3 5 104 DP2 APDO4 6 103 TXCLK APDO5 7 102 VDD VSS 8 101 VSS CSCKA 9 100 TA0/RXA1 CSDOA 10 99 TA1/TXA1 A2DCKA 11 98 TA2 APDI0 12 97 TA3 APDI1 13 96 TA4 APDI2 14 95 TA5 APDI3 15 94 TA6 APDI4 16 93 TA7 APDI5 17 92 TA8 CSRD 18 91 TA9 VSS 19 90 TA10 VDD 20 89 TA11 BPDI0/APDI6 21 88 VDD BPDI1/APDI7 22 87 SYTCK BPDI2/APDI8 23 86 VSS BPDI3/APDI9 24 85 P5IO BPDI4/APDI10 25 84 TA12 BPDI5/APDI11 26 83 TA13 A2DCKB 27 82 TA14 CSDOB 28 81 TA15 CSCKB 29 80 TA16 VSS 30 79 TA17 BPDO5/APDO11 31 78 TA18 BPDO4/APDO10 32 77 TA19 BPDO3/APDO9 33 76 WRN BPDO2/APDO8 34 75 RDN BPDO1/APDO7 35 74 ALE BPDO0/APDO6 36 73 VSS DSP/Framer 144 LPQ2 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VDD D2ACKB XSB0B/TXA2 XSB1B/TXA3 TXA4 VSS RXA4 RXA2 RXA3 INTA INTB MOD2 MOD1 MOD0 AVDD AVSS VDD VSS REFCK DCO A0 A1 A2 A3 A4 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 CSN PWRSTN VDD (Top View) Figure 4. 144-Pin Dual-Channel DSP/Framer Pin Diagram 10 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Table 12. 144-Pin Dual-Channel DSP/Framer Signal Descriptions Pin Name(s) Mode(s) 1 D2ACKA I/O Not used for this application. Per application schematic, do not connect. 2 APDO0 O Data Out, Channel A. Data transmitted to ILD2 from DSP/Framer. Connected to ILD2 pin DACA for channel A. 3 APDO1 O Control Output, Channel A. Control signal transmitted to ILD2 from DSP/Framer. Connected to ILD2 pin CSD for channel A. 4 APDO2 O Master Clock to ILD2, Channel A. Input to AFE PLL which generates oversampling clocks. Connected to ILD2 pin MCLK for channel A. 5 APDO3 O Not used for this application. Per application schematic, do not connect. 6 APDO4 I Data In, Channel A. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q0A for channel A. 7 APDO5 O Data Out, Channel A. Data transmitted to ILD2 from DSP/Framer. Connected to ILD2 pin DACB for channel A. 8 VSS -- Ground. O Not used for Revision "B2" DSP/Framer applications. Per application schematic, do not connect. I TMS. Boundary-scan mode select. Applicable to Revision "C1" DSP/Framer applications only, for JTAG support. 9 CSCKA Functional Description 10 CSDOA O Not used for this application. Per application schematic, do not connect. 11 A2DCKA I/O Not used for this application. Per application schematic, do not connect. 12 APDI0 I Data In, Channel A. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q1A for channel A. 13 APDI1 I Data In, Channel B. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q1A for channel B. 14 APDI2 I Not used for this application. Per application schematic, pulled low through a 1k resistor to ground. 15 APDI3 I Data In, Channel A. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q1B for channel A. 16 APDI4 I Not used for this application. Per application schematic, pulled low through a 1k resistor to ground. 17 APDI5 I Data In, Channel A. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q0B for channel A. 18 CSRD I 19 VSS -- Ground. 20 VDD P +3.3V supply. 21 BPDI0/APDI6 I Not used for this application. Per application schematic, pulled low through a 1k resistor to ground. Not used for Revision "B2" DSP/Framer applications. Per application schematic, pulled low through a 1k resistor to ground. TDI. Boundary-scan data in. Applicable to Revision "C1" DSP/Framer applications only, for JTAG support. 22 BPDI1/APDI7 I Data In, Channel B. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q0B for channel B. 23 24 25 BPDI2/APDI8 BPDI3/APDI9 BPDI4/APDI10 I Not used for this application. Per application schematic, pulled low through a 1k resistor to ground. 26 BPDI5/APDI11 I Data In, Channel B. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q1B for channel B. 27 A2DCKB I/O Not used for this application. Per application schematic, do not connect. 28 CSDOB O Not used for this application. Per application schematic, do not connect. 29 CSCKB O 30 VSS -- Ground. 31 BPDO5/APDO11 O Data Out, Channel B. Data transmitted to ILD2 from DSP/Framer. Connected to ILD2 pin DACB for channel B. 32 BPDO4/APDO10 I Data In, Channel B. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q0A for channel B. 33 BPDO3/APDO9 O Not used for this application. Per application schematic, do not connect. Not used for Revision "B2" DSP/Framer applications. Per application schematic, do not connect. DO-009643-DS, Issue 2 TDO. Boundary-scan data out. Applicable to Revision "C1" DSP/Framer applications only, for JTAG support. GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 11 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Table 12. 144-Pin Dual-Channel DSP/Framer Signal Descriptions Pin Name(s) Mode(s) Functional Description 34 BPDO2/APDO8 O Master Clock to ILD2, Channel B. Input to AFE PLL which generates oversampling clocks. Connected to ILD2 pin MCLK for channel B. 35 BPDO1/APDO7 O Control Output, Channel B. Control signal transmitted to ILD2 from DSP/Framer. Connected to ILD2 pin CSD for channel B. 36 BPDO0/APDO6 O Data Out, Channel B. Data transmitted to ILD2 from DSP/Framer. Connected to ILD2 pin DACA for channel B. 37 VDD P +3.3V supply. 38 D2ACKB O Not used for this application. Per application schematic, do not connect. 39 SERIAL I/O No Connect. For serial interface applications, this pin is used for debug purposes only. UTOPIA I/O TXA2- ATM UTOPIA Level 2 Transmit Address. (I) Driven by the ATM to PHY layer to select the appropriate PHY device and port. SERIAL I/O No Connect. For serial interface applications, this pin is used for debug purposes only. UTOPIA I/O TXA3- ATM UTOPIA Level 2 Transmit Address. (I) Driven by the ATM to PHY layer to select the appropriate PHY device and port. XSB0B/TXA2 Not used for ATM UTOPIA Level 1 applications, internally configured as output. 40 XSB1B/TXA3 Not used for ATM UTOPIA Level 1 applications, internally configured as output. 41 SERIAL I/O Not used for this application. Per application schematic, do not connect. UTOPIA I/O TXA4- ATM UTOPIA Level 2 Transmit Address. (I) Driven by the ATM to PHY layer to select the appropriate PHY device and port. TXA4 Not used for ATM UTOPIA Level 1 applications, internally configured as output. 42 43 44 45 VSS RXA4 RXA2 RXA3 -- Ground. SERIAL I/O Not used for this application. Per application schematic, do not connect. UTOPIA I/O ATM UTOPIA Level 2 Receive Address. (I) Driven by the ATM to PHY layer to select the appropriate PHY device and port. Not used for ATM UTOPIA Level 1 applications, internally configured as output. 46 INTA O Interrupt of DSP A. Carries interrupts from internal DSP core A. The polarity of the interrupt level is programmable with default to inactive open-drain. Internally generated status can be enabled to activate the interrupt pin. Used during start-up for code downloads. INTA and INTB are both required. Both can be declared open-drain and tied together, if desired. 47 INTB O Interrupt of DSP B. Carries interrupts from internal DSP core B and framer. The polarity of the interrupt level is programmable with default to inactive open-drain. Internally generated status can be enabled to activate the interrupt pin. Used during start-up for code downloads and EOC interrupts in data mode. INTA and INTB are both required. Both can be declared open-drain and tied together, if desired. 48 49 50 MOD2 MOD1 MOD0 I Host Bus Mode. Bits 2 through 0. These input pins define the host bus control modes: 000 = Non-multiplexed processor mode 001 = Motorola mode where RDN is R/W and WRN is DSN 01X = reserved for testing 100 = Multiplexed processor mode 101 = reserved for testing. 51 AVDD P AVDD. Digital +3.3V supply for VCO. 52 AVSS -- AVSS. Ground pin for VCO. Connect to digital ground as per schematic. 53 VDD P +3.3V supply. 54 VSS -- Ground. 55 REFCK I/O Reference Clock. Used to pass network timing reference. 56 DCO I/O DCO. Pull up as per application schematic. 57 58 59 60 61 A0 A1 A2 A3 A4 I 62 63 64 65 66 67 68 69 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 I/O 12 Address Bus. Bits 4 through 0. Host Address bus in the non-multiplexed mode. A[4:3] are used to select between the two internal 8 byte address spaces. Multiplexed Address and Data Bus. AD[4:0] = Address inputs in multiplexed mode. See A[4:0] for usage. GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Table 12. 144-Pin Dual-Channel DSP/Framer Signal Descriptions Pin Name(s) Mode(s) 70 CSN I Chip Select. Active low in P mode. Functional Description 71 PWRSTN I Power Reset Not. Low active. DSP hardware reset that after deactivation still leaves the internal circuits in the software reset mode. In addition, all outputs are forced into high impedance mode when active. 72 VDD P +3.3V supply. 73 VSS -- Ground. 74 ALE I Address Latch Enable. In the processor mode, this pin is an input that indicates an active address cycle on the multiplexed bus. Also functions as RSTN for JTAG control for Revision "C1" DSP/Framer applications. 75 RDN I Read Not. Active low read pulse. This signal enables data bus output buffers during read operations. 76 WRN I Write Not. Active low write pulse. This signal is used as a standard processor data write control signal. 77 78 79 80 81 82 83 84 TA19 TA18 TA17 TA16 TA15 TA14 TA13 TA12 I/O 85 P5IO I 86 VSS -- Ground. 87 SYTCK O Not used for this application. Per application schematic, do not connect. 88 VDD P 3.3V supply. 89 90 91 92 93 94 95 96 97 98 TA11 TA10 TA9 TA8 TA7 TA6 TA5 TA4 TA3 TA2 I/O External TDM. Not used for this application. Per application schematic, do not connect. Programmable Input Pin for Revision "B2" DSP/Framer applications. TCK. Boundary-scan clock. Applicable to Revision "C1" DSP/Framer applications only, for JTAG support. 99 External TDM. Not used for this application. Per application schematic, do not connect. SERIAL I/O Not used for this application. Internally configured as output. UTOPIA I/O TXA1 - ATM UTOPIA Level 2 Transmit Address. (I) Driven by the ATM to PHY layer to select the appropriate PHY device and port. SERIAL I/O Not used for this application. Internally configured as output. UTOPIA I/O RXA1 - ATM UTOPIA Level 2 Receive Address. (I) Driven by the ATM to PHY layer to select the appropriate PHY device and port. TA1/TXA1 Not used for ATM UTOPIA Level 1 applications, internally configured as output. 100 TA0/RXA1 Not used for ATM UTOPIA Level 1 applications, internally configured as output. 101 VSS -- 102 VDD P 103 104 105 106 Ground. +3.3V supply. SERIAL I/O UTOPIA I SERIAL I/O UTOPIA I TXDT2 - ATM UTOPIA Level 1 and 2 Transmit Data. Byte-Wide True Data from the ATM to the PHY device. SERIAL O RXCKA - Receive clock for channel A. UTOPIA I RXCLK - ATM UTOPIA Level 1 and 2 Receive Clock. Synchronizes all signal transfers from the ATM to the PHY device. SERIAL O RXDA - Receive serial data for channel A. UTOPIA O RXDT0 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM device. TXCLK DP2 RXCLK DP8 DO-009643-DS, Issue 2 TXCKA - Transmit clock for channel A. Framed = I; unframed = O. TXCLK - ATM UTOPIA Level 1 and 2 Transmit Clock. Synchronizes all signal transfers from the ATM to the PHY device. TXCKB - Transmit clock for channel B. Framed = I; unframed = O. GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 13 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Table 12. 144-Pin Dual-Channel DSP/Framer Signal Descriptions Pin 107 108 Name(s) 110 VSS 113 114 115 116 117 118 119 120 121 122 123 124 125 14 RXDB - Receive serial data for channel B. UTOPIA O RXDT1 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM device. SERIAL O RXCKB - Receive clock for channel B. This pin is the same as BRXCK for applications bypassing the on-chip framer. UTOPIA O RXDT2 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM device. DP10 VDD 112 Functional Description O DP9 109 111 Mode(s) SERIAL P +3.3V supply. -- Ground. SERIAL I TXDA - Serial transmit data for channel A. UTOPIA I TXDT0 - ATM UTOPIA Level 1 and 2 Transmit Data. Byte-Wide True Data from the ATM to the PHY device. SERIAL O RXSOFB - Receive start of frame for channel B. UTOPIA O RXCLAV - ATM UTOPIA Level 1 and 2 Receive Cell Available Signal. Used by the PHY layer device to indicate that the receive buffer has a new cell. SERIAL I TXDB - Serial transmit data for channel B. UTOPIA I TXDT1 - ATM UTOPIA Level 1 and 2 Transmit Data. Byte-Wide True Data from the ATM to the PHY device. SERIAL I/O UTOPIA I SERIAL I/O UTOPIA I SERIAL I/O UTOPIA I SERIAL I/O UTOPIA I SERIAL I/O UTOPIA I SERIAL I/O Not used for this application. Per application schematic, do not connect. UTOPIA O TXCLAV - ATM UTOPIA Level 1 and 2 Transmit Cell Available Signal. Used by the PHY layer device to indicate that there is space available for a new cell. SERIAL I/O Not used for this application. Per application schematic, do not connect. UTOPIA O RXDT7 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM device. SERIAL I/O Not used for this application. Per application schematic, do not connect. UTOPIA O RXDT4 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM device. SERIAL I/O Not used for this application. Per application schematic, do not connect. UTOPIA O RXDT3 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM device. SERIAL I/O Not used for this application. Per application schematic, do not connect. UTOPIA O RXDT6 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM device. SERIAL O Not used for this application. Per application schematic, do not connect. UTOPIA O RXDT5 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM device. SERIAL I TXSOFA - Transmit Start of frame for channel A. UTOPIA I TXSOC - ATM UTOPIA Level 1 and 2 Transmit Start of Cell (active high). This bit is true on the first byte of the transmitted cell from the ATM to the PHY. DP0 RXSOFB/RXCLAV DP1 DP7 DP3 DP4 DP5 DP6 TBAUD/TXCLAV DP15 DP12 DP11 DP14 DP13 TXSOFA/TXSOC Not used for this application. Internally configured as output. TXDT7 - ATM UTOPIA Level 1 and 2 Transmit Data. Byte-Wide True Data from the ATM to the PHY device. Not used for this application. Per application schematic, do not connect. TXDT3 - ATM UTOPIA Level 1 and 2 Transmit Data. Byte-Wide True Data from the ATM to the PHY device. Not used for this application. Per application schematic, do not connect. TXDT4 - ATM UTOPIA Level 1 and 2 Transmit Data. Byte-Wide True Data from the ATM to the PHY device. Not used for this application. Per application schematic, do not connect. TXDT5 - ATM UTOPIA Level 1 and 2 Transmit Data. Byte-Wide True Data from the ATM to the PHY device. Not used for this application. Per application schematic, do not connect. TXDT6 - ATM UTOPIA Level 1 and 2 Transmit Data. Byte-Wide True Data from the ATM to the PHY device. GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Table 12. 144-Pin Dual-Channel DSP/Framer Signal Descriptions Pin 126 Name(s) Mode(s) Functional Description SERIAL O RXSOFA - Receive Start of frame for channel A. UTOPIA O RXSOC - ATM UTOPIA Level 1 and 2 Receive Start of Cell (active high). This bit is true on the first byte of the transmitted cell from the PHY to the ATM. RXSOFA/RXSOC 127 VSS -- Ground. 128 AVDD P AVDD. Digital +3.3V supply for VCO. 129 AVSS -- AVSS. Ground pin for VCO. Connect to digital ground as per schematic. 130 XTLI I Crystal Oscillator Input. Oscillator input. It accepts a free running external clock at subrate of the internal VCO/PLL (see board recommendations). 131 XTLO O Crystal Oscillator Output. Connects to one crystal terminal and capacitor. 132 AVSS -- AVSS. Ground pin for VCO. Connect to digital ground as per schematic. 133 VSS -- Ground. 134 SERIAL I/O Not used for this application. Per application schematic, do not connect. UTOPIA I/O TXA0 - ATM UTOPIA Level 2 Transmit Address. (I) Driven by the ATM to PHY layer to select the appropriate PHY device and port. SERIAL I TXSOFB - Transmit Start of Frame for channel B. UTOPIA I TXEN - ATM UTOPIA Level 1 and 2 Transmit Enable (active low). The ATM layer device uses this pin to throttle the rate at the octet boundary. SERIAL I Not used for this application. Terminate with a pull-up resistor. UTOPIA I RXEN - Receive Enable (active low). The ATM layer device uses this pin to throttle the rate at the octet boundary. SERIAL I/O Not used for this application. Internally configured as output. UTOPIA I/O RXA0 - ATM UTOPIA Level 2 Receive Address. (I) Driven by the ATM to PHY layer to select the appropriate PHY device and port. PIP/POP/TXA0 Not used for ATM UTOPIA Level 1 applications, internally configured as output. 135 136 137 TXSOFB/TXEN PIP/POP/RXEN PIP/POP/RXA0 Not used for ATM UTOPIA Level 1 applications, internally configured as output. 2B1Q and PAM: QSOA, QSOB - Level Display 2 Serial Data Output. Serial data for level display 2. Data format the same as ISO. 138 QSO O CAP: QSOA, QSOB - Quadrature Serial Output. Quadrature constellation display serial output. Data format the same as ISO. 2B1Q and PAM: ISOA, ISOB - Level Display 1 Serial Data Output. Serial data for level display 1. Data format is asynchronous with 12 bits of data and start and stop bits. 139 ISO O CAP: ISOA, ISOB - In-phase Serial Output. In-phase constellation display serial output. Data format is asynchronous with 12 bits of data and start and stop bits. 2B1Q and PAM: Serial Data Clock. For ISO and QSO data outputs. 140 SOCK O 141 POP2A O POP2A - Configured as a programmable output after power-up for Channel A. 142 XSB1A O External Strobe1 of DSP A. One of two strobes from the DSP that are synchronized with the internal signal processing clock. 143 XSB0A O External Strobe0 of DSP A. One of two strobes from the DSP that are synchronized with the internal signal processing clock. 144 VDD P +3.3V supply. CAP: Serial Data Clock. For ISO and QSO constellation data outputs. DO-009643-DS, Issue 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 15 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Boundary-Scan Testing Four pins are provided for compliance to IEEE Standard 1149.1 (JTAG) for boundary scan testing. These DSP pins are used to control and communicate with the boundary-scan logic. JTAG support is available only in Revision "C1" of the DSP/Framer. Table 13 provides a list of the four JTAG pins: Table 13. Boundary-Scan Pins 144-Pin DSP/Framer Revision "C1" Pin # JTAG Description 9 TMS - Test Mode Select 18 TDI - Test Data Input 29 TDO - Test Data Output 85 TCK - Test Clock Table 14. Dual-Channel DSP/Framer Electrical Characteristics Parameters Min Nom Max Unit Power Supply Voltage, VDD -- -- 3.6 V Power Supply Voltage, AVDD -- -- 3.6 V GND - 0.3 -- 5.5 V Storage Temperature -40 -- 125 C Junction Temperature -- -- 125 C Power Supply Voltage, VDD 3.13 3.3 3.47 V Power Supply Voltage, AVDD 2.75 3.3 3.47 V GND - 0.3 3.3 5.5 V -40 25 85 C Test Conditions/Comments Absolute Maximum Ratings Input Voltage Recommended Operating Conditions Input Voltage Operating Temperature Digital Specifications I/O Levels TTL and/or CMOS compatible Digital Inputs For all inputs except XTLI. For XTLI, the maximum VIL is VDD/2. Input Low Voltage, VIL -0.3 0 0.8 V Input High Voltage, VIH 2.0 3.3 5.25 V Output Low Voltage, VOL -- 0 0.4 V Current sink, IOL, 3.5 mA Output High Voltage, VOH for Rev. B2 of the DSP 2.4 3.3 -- V Current load, IOH, 6 mA for all pins Output High Voltage, VOH for Rev. C1 of the DSP 2.4 3.3 -- V Current load, IOH, 6 mA for all non-UTOPIA pins Current load, IOH, 10 mA for all UTOPIA pins Input Leakage Current, ILI 10 -- -- A Input voltage, VI, between 0 volts and VDD High-Z Leakage Current, ILO 10 -- -- A Output voltage, VO, between 0 volts and VDD Input Capacitance, CIN (fc = 1 MHz) -- 6 -- pF I/O Capacitance, CIO (fc = 1 MHz) -- 10 -- pF Digital Outputs DC Specifications Note: All of the following pins are 5V tolerant: All Input (I) signal pins except XTLI All Input/Output (I/O) signal pins No Output (O) signal pins except INTA, INTB, and POP2A 16 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Table 15. Clock Specifications for XTLI Pin Timing Parameters Voltage Duty Cycle Rise Time Maximum (nsec) Fall Time Maximum (nsec) Overshoot Maximum Undershoot Maximum 40 - 60% 4 4 3.3V + 5% 100 mV below ground Note the following layout guidelines: 1. We recommend not more than 4 DSPs per clock source. 2. The clock source distribution network should be routed in a star pattern ensuring equal distances to all DSPs. 3. Place a series termination resistor as close to the clock source as possible. 4. Refer to the "Critical Clock and Signal Layout Guidelines" section in Chapter 3 of the Design Guide for further information. DO-009643-DS, Issue 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 17 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Customer Data Interface The customer data interface includes data signals, control signals, and address signals. The GlobespanVirata 144pin DSP has an on-chip programmable framer for handling multiple TC layer framing formats. The supported, software selectable, framing formats include Serial Mode and Asynchronous Transfer Mode (ATM) UTOPIA Level 1 and Level 2. Please note only one UTOPIA Level 1 interface is supported per dual channel DSP/Framer. Table 16 lists corresponding pins for both Serial and UTOPIA Modes. Table 16. 144-Pin DSP Data Interface Pin Usage Pin Name Pin Number DP0 111 UTOPIA Mode I TXDT0 Serial Mode I TXDA DP1 113 I TXDT1 I TXDB DP2 104 I TXDT2 I/O TXCKB DP3 115 I TXDT3 I/O Not used DP4 116 I TXDT4 I/O Not used DP5 117 I TXDT5 I/O Not used DP6 118 I TXDT6 I/O Not used DP7 114 I TXDT7 I/O Not used DP8 106 O RXDT0 O RXDA DP9 107 O RXDT1 O RXDB DP10 108 O RXDT2 O RXCKB DP11 122 O RXDT3 I/O Not used DP12 121 O RXDT4 I/O Not used DP13 124 O RXDT5 O Not used DP14 123 O RXDT6 I/O Not used DP15 120 O RXDT7 I/O Not used TXCLK 103 I TXCLK I/O TXCKA TXSOFA/TXSOC 125 I TXSOC I TXSOFA TBAUD/TXCLAV 119 O TXCLAV I/O Not used RXCLK 105 I RXCLK O RXCKA RXSOFA/RXSOC 126 O RXSOC O RXSOFA RXSOFB/RXCLAV 112 O RXCLAV O RXSOFB PIP/POP/TXA0 134 I TXA0* I/O Not used TA1/TXA1 99 I TXA1* I/O Not used XSB0B/TXA2 39 I TXA2* I/O Not used XSB1B/TXA3 40 I TXA3* I/O Not used TXA4 41 I TXA4* I/O Not used PIP/POP/RXA0 137 I RXA0* I/O Not used TA0/RXA1 100 I RXA1* I/O Not used RXA2 44 I RXA2* I/O Not used RXA3 45 I RXA3* I/O Not used RXA4 43 I RXA4* I/O Not used TXSOFB/TXEN 135 I TXEN I TXSOFB PIP/POP/RXEN 136 I RXEN I Not used * Not used for UTOPIA Level 1 applications. 18 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 ATM UTOPIA Level 1 and Level 2 Figure 5 and Figure 6 detail the interface for standard ATM UTOPIA Level 1 and Level 2. Dual-channel ATM over UTOPIA Level 2 or single-channel ATM over UTOPIA Level 1 is supported for SHDSL, SDSL 2B1Q, and HDSL2. TXDT[7:0] TXCLK TXSOC TXEN TXCLAV ATM layer device RXDT[7:0] Globespan Virata DSP/Framer RXCLK RXSOC RXEN RXCLAV NTR (CO) Figure 5. UTOPIA Level 1 Signals TXDT[7:0] TXCLK TXSOC TXEN TXCLAV TXA[4:0] Globespan Virata DSP/Framer ATM layer device RXA[4:0] RXDT[7:0] RXCLK RXSOC RXEN RXCLAV NTR (CO) NOTE: RXSOC, RXCLAV, and TXCLAV are tri-state active high signals and need appropriate pull-down terminations. Figure 6. UTOPIA Level 2 Signals DO-009643-DS, Issue 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 19 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Transmit, receive, and tri-state timing is shown in Figure 7, Figure 8, and Figure 9. Timing parameters are shown in Table 17. Tcyc TXCKA TXDT[7:0] TXA[4:0] TXSOC TXEN TAsu TAhld TXCLAV TAdel Figure 7. Transmit ATM Timing Tcyc RXCKA RXEN RXA[4:0] TAsu TAhld RXDT[7:0] RXSOC RXCLAV TAdel Figure 8. Receive ATM Timing TXCK RXCK TXDT[7:0] RXSOC RXCLAV TXCLAV TAdel TAdel Figure 9. Tri-State ATM Timing 20 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Table 17. ATM Timing Parameters Specification DO-009643-DS, Issue 2 Description Min Tcyc Clock Period 40 ns TAsu Input Setup to Clock Rising Edge 4 ns TAhld Input Hold from Clock Rising Edge 1 ns TAdel Output Delay from Clock Rising Edge GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions Max 15 ns 21 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Supported Serial Interfaces The following serial interfaces are supported per application: SHDSL: Dual or single-channel Slotted E1, Slotted T1, and Nx64 Interfaces (refer to the SHDSL Design Guide, GSDG-0014, for a detailed description). HDSL2: Single-channel Fixed T1 Interface (refer to the HDSL2 Design Guide, GSDG-0013, for a detailed description). SDSL CAP: Single-channel Slotted E1, Slotted T1, and Nx64 Interfaces (refer to the SDSL CAP Design Guide, GSDG-0012 for a detailed description). Dual-channel supported in unframed mode only (no physical layer framing). Table 18. Summary of Transceiver Serial Interface Leads Name Type CO/Framer Type CO/Framer Bypass Type CP/Framer Type CP/Framer Bypass Description Transmission Interface TXD[A,B] I I I I Transmit Data for channels A and B TXCK[A,B] I O I O Transmit Bit Clock for channels A and B (see NOTE) RXD[A,B] O O O O Receive Data for channels A and B O O Receive Bit Clock for channels A and B (see NOTE) RXCK[A,B] O O TXSOF[A,B] I N/C I N/C Transmit start of Frame for channels A and B RXSOF[A,B] O N/C O N/C Receive start of Frame for channels A and B NOTE: Each Type field shows the directional flow for the CO/CP with Framer, or CO/CP without the integrated Framer (Bypass mode) from the view of the DSP/Framer. Figure 10 and Figure 11 depict the directions of the framed and unframed serial data/clock interfaces. 22 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 TXD[A/B] TXCK[A/B] TXSOF[A/B] RXD[A/B] DSL Termination Unit DSL Termination Unit RXD[A/B] RXCK[A/B] RXCK[A/B] RXSOF[A/B] TXD[A/B] Central Office Remote RXSOF[A/B] TXCK[A/B] TXSOF[A/B] Figure 10. *Framed Serial Data/Clock Interface TXD[A/B] RXD[A/B] TXCK[A/B] DSL Termination Unit DSL Termination Unit RXD[A/B] Central Office Remote RXCK[A/B] RXCK[A/B] TXD[A/B] TXCK[A/B] Figure 11. *Unframed (Framer Bypass Mode) Serial Data/Clock Interface. * Note that TX and RX clocks must have the same frequency at both the CO and CPE. DO-009643-DS, Issue 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 23 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 The relationship between the data and the Start Of Frame signal (SOF) to the clock pulse is illustrated below. Figure 12 and Figure 13 depict E1, which has sync byte in time slot 0. Figure 14 and Figure 15 depict T1, which has an Fbit signifying the start of time slot 0. For unframed mode, the SOF is not applicable. Figure 16 and Figure 17 depict Nx64 operation. 254 255 0 1 2 3 7 8 9 TXCKA/B TXSOFA/B TS31 TXDA/B (32 TS) TS0 TS1 NOTE: The transmit start of frame pulse (TXSOFA/B) must be low for at least 8 clock cycles. Figure 12. Transmit Slotted E1 Interface Timing 254 255 0 1 2 3 7 8 9 RXCKA/B RXSOFA/B RXDA/B (32 TS) TS31 TS0 TS1 Figure 13. Receive Slotted E1 Interface Timing 24 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 191 192 0 1 2 3 7 8 9 10 HTXCKA, HTXCKB HTXSOFA, HTXSOFB HTXDA, HTXDB (24 TS) F bit TS23 TS0 TS1 NOTE: The transmit start of frame pulse (TXSOFA) must be low for at least 8 clock cycles. Figure 14. T1 Interface Transmit Timing for HDSL2 191 192 0 1 2 3 7 8 9 10 HRXCKA, HRXCKB HRXSOFA, HRXSOFB HRXDA, HRXDB (24 TS) TS23 F bit TS0 TS1 Figure 15. T1 Interface Receive Timing for HDSL2 DO-009643-DS, Issue 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 25 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet 0 1 June 25, 2002 2 3 7 2 3 7 8 9 TXCKA/B TXDA/B Figure 16. Transmit Nx64 Interface Timing 0 1 8 9 RXCKA/B RXDA/B Figure 17. Receive Nx64 Interface Timing 26 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Figure 18 and Figure 19 show serial transmit and receive timing. This timing applies to all products (SDSL, HDSL2, and SHDSL - ILD2). Tcyc TXCKA/B TFsu TFhld TXDA/B TXSOFA/B Figure 18. Serial Transmit Timing Tcyc RXCKA/B TRdelLH TRdelHL RXDA/B RXSOFA/B Figure 19. Serial Receive Timing Table 19. Serial Timing Parameters Specification Description Min Max Tcyc Clock Period 50 ns TFsu Input Setup to Clock Falling Edge 10 ns TFhld Input Hold from Clock Falling Edge 5 ns TRdelLH Output Delay From Low to High 20 ns TRdelHL Output Delay From High to Low 20 ns DO-009643-DS, Issue 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 27 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Input Timing Parameters Specifications are defined in terms of setup and hold times of the data inputs relative to a reference clock. Table 20. Input Timing Parameters Input Signal TxDA TxDB Pin Edge Setup (nsec) Hold (nsec) TXCKA (103) TXCKB (104) +/- 10 5 setup Data input, relative to the falling edge hold Reference clock + - setup Data input, relative to the rising edge hold This timing applies to ALL data inputs and their respective clocks Figure 20. Input Timing Diagram 28 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Output Timing Parameters Specifications are defined in terms of propagation delay from a reference clock edge to the data output stable condition. NOTE: All loads are 35 pF, unless noted otherwise. Add 1.5 nsec per 10 pF of additional loading. Rise and fall times are 5 nsec. Table 21. Output Timing Parameters Output Pin Edge Min (nsec) Max (nsec) All outputs to high-Z PWRSTN (71) + 50 RxDA RxDB RXCKA (105) RXCKB (108) +/- 20 ISO/QSO SOCK (140) + 10 Data output, relative to the falling edge delay Reference clock + - Data output, relative to the rising edge delay This timing applies to ALL data outputs and their respective clocks Figure 21. Output Timing Diagram DO-009643-DS, Issue 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 29 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Host Processor Interfaces GlobespanVirata chip sets easily interface with multiplexed (Intel style), generic non-multiplexed, and nonmultiplexed Motorola style host processors. The MOD pins on the DSP must be set according to Table 22 for the type of processor interface required. These pins should be set (pulled high or low) using the resistor values shown in the Customer Schematics. Table 22. MOD Settings Processor MOD2 MOD1 MOD0 RDN Function WRN Function ALE Use Multiplexed 1 0 0 RDN WRN ALE Motorola 0 0 1 RD/WRN DSN n/a (pulled low) Other non-multiplexed 0 0 0 RDN WRN n/a (pulled low) NOTE: A value of 1 refers to pulled high and 0 refers to pulled low. Table 23. Summary of Transceiver Host Interface Leads Name Type CO/Framer AD[0-7] I/O CSN I DSP Chip Select ALE I Multiplexed Processor Address Latch Enable WRN I Write Strobe Description 8 Bit Multiplexed Address/Data Bus RDN I Read Strobe PWRSTN I Power Reset Not INTNA, INTNB O DSP/Framer Interrupts MOD[2,1,0] I Host Bus Control Modes A[0-4] I Non-multiplexed Address Bus NOTE: Each Type field shows the directional flow for the CO/CP with Framer, or CO/CP without the integrated Framer (Bypass mode) from the view of the DSP/Framer. Figure 10 and Figure 11 depict the directions of the framed and unframed serial data/clock interfaces. 30 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Multiplexed Bus Mode Timing Requirements and Characteristics Table 24. Read Cycle Timing Characteristics Parameter Symbol Max (ns) Test Conditions/Comments Capacitive load on HAD[7:0] is 100 pF Address valid to data valid tHAVDV 35 Read strobe active to data valid tHRDNLDV 25 Bus active after read tHRDNHDX 10 Active HCSNA overlap with active HRDN defines the effective HRDN pulse Capacitive load on HAD[7:0] is 100 pF Active HCSNA overlap with active HRDN defines the effective HRDN pulse Table 25. Read Cycle Timing Requirements Parameter Symbol Min (ns) Test Conditions/Comments Chip select setup time before read strobe tHCSNLHRDNL 0 Active HCSNA overlap with active HRDN defines the effective HRDN pulse Chip select hold time after read strobe tHRDNHHCSNH 0 Active HCSNA overlap with active HRDN defines the effective HRDN pulse Address setup time before latch strobe low tHAVHALEL 10 Address hold time after latch strobe low tHALELHAX 5 Address latch strobe width tHALEHHALEL 10 Address setup time before read strobe tHAVHRDNL 10 Read strobe inactive before next cycle tHRDNLHHALEH 10 Inter-access cycle time (not shown) tHALEHHALEH 200 The minimum time between successive reads Table 26. Write Cycle Timing Requirements Parameter Inter-access cycle time (not shown) Symbol Test Conditions/Comments 200 The minimum time between successive writes Chip select setup time before write strobe low tHCSNLHWRNL 10 Active HCSNA overlap with active HWRN defines the effective HWRN pulse Write strobe width tHWRNLHWRNH 20 Chip select hold time after write strobe high tHWRNHHCSNH 0 Address setup time before latch strobe low tHAVHALEL 10 Address hold time after latch strobe low tHALELHAX 5 Data setup time before write strobe tHDVHWRNH 10 Data hold time after write strobe tHWRNHHDX 2 Address latch strobe width tHALEHHALEL 10 Address setup time before write strobe tHAVHWRNL 0 Write strobe inactive before next cycle tHWRNHHALEH 10 DO-009643-DS, Issue 2 tHALELHALEL Min (ns) Active HCSNA overlap with active HWRN defines the effective HWRN pulse GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 31 32 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions HCSNA HWRN HRDN HAD HALE tHAVHALEL tHAVDV tHALELHAX tHCSNLHRDNL tHAVHRDNL Addr. Data tHRDNHHCSNH tHRDNLDV READ tHALEHHALEL tHRDNHHALEH tHRDNHHDX tHAVHALEL Addr. tHCSNLHWRNL tHWRNHHCSNH tHWRNLHWRNH tHDVHWRNH tHAVHWRNL Data WRITE tHALELHAX tHALEHHALEL tHWRNHHALEH tHWRNHHDX XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Figure 22. Multiplexed Bus Mode Timing Diagram DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Non-multiplexed Bus Mode Timing Requirements and Characteristics Table 27. Read Cycle Timing Characteristics Parameter Symbol Max (ns) Test Conditions/Comments Capacitive load on HD[7:0] is 100 pF Address valid to data valid tHAVHDV 35 Read strobe active to data valid tHRDNLHDV 25 Bus active after read tHRDNHHDZ 10 Active HCSNA overlap with active HRDN defines the effective HRDN pulse Capacitive load on HD[7:0] is 100 pF Active HCSNA overlap with active HRDN defines the effective HRDN pulse Table 28. Read Cycle Timing Requirements Parameter Symbol Min (ns) Test Conditions/Comments Chip select active before read tHCSNLHRDNL 0 Active HCSNA overlap with active HRDN defines the effective HRDN pulse Chip select hold time after read tHRDNHHCSNH 0 Active HCSNA overlap with active HRDN defines the effective HRDN pulse Address setup time before read tHAVHRDNL 5 Address hold time after read tHRDNHHAX Inter-access cycle time (not shown) tHRDNLHRDNL 5 200 The minimum time between successive reads Table 29. Write Cycle Timing Requirements Parameter Inter-access cycle time (not shown) Symbol Min (ns) Test Conditions/Comments tHWRNLHWRNL 200 The minimum time between successive writes Chip select setup time before write strobe low tHCSNLHWRNL 10 Active HCSNA overlap with active HWRN defines the effective HWRN pulse Write strobe width tHWRNLHWRNH 20 Chip select hold time after write tHWRNHHCSNH 0 Address setup time before write tHAVHWRNL 10 Address hold time after write tHWRNHHAX 5 Data setup time before write tHDVHWRNH 10 Data hold time after write tHWRNHHDX 2 DO-009643-DS, Issue 2 Active HCSNA overlap with active HWRN defines the effective HWRN pulse GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 33 tHWRNHHCSNH HCSNA HWRN HRDN tHCSNLHRDNL tHRDNLDV HD tHAVDV tHAVHRDNL Address HA READ Data tHRDNHDZ tHRDNHHCSNH tHCSNLHWRNL tHWRNLDV tHWRNLHWRNH Data tHAVHWRNL tRDNHHAXH Address WRITE June 25, 2002 tHWRNHHDX tHWRNHHAX XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet Figure 23. Non-multiplexed Bus Mode Timing Diagram 34 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Motorola Bus Mode Timing Requirements and Characteristics Table 30. Read Cycle Timing Characteristics Parameter Address valid to data valid Data set (DSN) strobe active to data valid Bus active after data set strobe inactive Symbol Min (ns) Max (ns) tHAVDV 20 tDSNLDV 10 tDSNHHDX 6 Test Conditions/Comments Table 31. Read Cycle Timing Requirements Parameter Symbol Inter-access cycle time (not shown) Min (ns) Max (ns) - 200 tHAVHCSNL 5 R/Wn setup before chip select low tHRWNHHCSNL 5 R/Wn hold time after chip select inactive tHCSNHHRWNL 0 Address setup time before chip select low Address hold time after chip select inactive tDSNHHAX 5 Chip select setup time before data set strobe tHCSNLDSNL 5 Chip select hold time after data set strobe tDSNHHCSNH 0 Test Conditions/Comments The minimum time between successive reads Table 32. Write Cycle Timing Requirements Parameter Inter-access cycle time (not shown) Address setup time before chip select low Symbol Min (ns) Max (ns) - 200 tHAVHCSNL 5 R/Wn setup before chip select low tHRWNHHCSNL 5 R/Wn hold time after chip select inactive tHCSNHHRWNH 0 tDVDSNL 5 tDSNLDSNH 5 tDSNHHAX 5 Chip select setup time before data set strobe tHCSNLDSNL 5 Chip select hold time after data set strobe tDSNHHCSNH 0 Data setup time before data set strobe active Data set strobe width for write operation Address hold time after chip select inactive DO-009643-DS, Issue 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions Test Conditions/Comments The minimum time between successive writes 35 36 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions HCSNA tHCSNLDSNL Address tDSNLDV tHAVDV tHAVHCSNL tHRWNHHCSNL HDSN (HWRN) R/W (HRDN) HD HA READ Data tDSNHHCSNH tDSNHHDX tHCSNHHRWNL tDSNHHAX tHCSNLDSNL tHRWNLDSNL tDVDSNL tHAVHCSNL Address WRITE Data tDSNHHCSNH tDSNLDSNH tHCSNHHRWNH tDSNHHDX tDSNHHAX XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Figure 24. Motorola Bus Mode Timing Diagram DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 GS3137 ILD2 Specifications Q1B Q0B VDDD GNDD MCLK CSD DACA DACB Q0A Q1A RBIAS GNDA VDDA HYBN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GS3137 VDDD GNDA LDOUTP VDDA LDOUTN GNDA VDDA VREFN VCM VREFP GNDA RCVP RCVN HYBP Figure 25. GS3137 28-pin ILD2 Pin Diagram NOTE: The EPTSSOP is required to support a transmit power of higher than 15 dbm (HDSL2 and asymmetric PSD options for SHDSL). Table 33. GS3137 ILD2 Signal Descriptions Pin Symbol Type Name / Function 1 Q1B O 2 Q0B O 3 VDDD P Digital Supply. +3.3V. 4 GNDD P Digital Ground. 5 MCLK I Master Clock from DSP. Input to PLL which generates oversampling clocks. 6 CSD I Control Input from DSP. Configures the device. 7 DACA I 8 DACB I Data Output to DSP. Data Input from DSP. 9 Q0A O 10 Q1A O 11 RBIAS I External Bias Resistor Connection. 12 GNDA P Analog Ground. 13 VDDA P Analog Supply. +5V. 14 HYBN I Negative Input from Hybrid Network. See NOTE. 15 HYBP I Positive Input from Hybrid Network. See NOTE. 16 RCVN I Negative Input from Line Transformer. See NOTE. 17 RCVP I Positive Input from Line Transformer. See NOTE. Data Output to DSP. DO-009643-DS, Issue 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 37 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Table 33. GS3137 ILD2 Signal Descriptions Pin Symbol Type 18 GNDA P Analog Ground. Name / Function 19 VREFP I Positive Reference Voltage. 20 VCM I Common-mode Reference Voltage. 21 VREFN I Negative Reference Voltage. 22 VDDA P Analog Supply. +5V. 23 GNDA P Analog Ground. 24 LDOUTN O Negative Line Driver Output. See NOTE. 25 VDDA P Analog Supply. +5V. 26 LDOUTP O Positive Line Driver Output. See NOTE. 27 GNDA P Analog Ground. 28 VDDD P PLL Supply 3.3V. See NOTE. NOTE: Refer to your application schematics for all application-specific pin assignments. Table 34. GS3137 ILD2 Electrical Characteristics Parameter Conditions Min Nom Max Unit 5V supply 7.0 V 3.3V supply 3.6 V Absolute Maximum Ratings Power Supply Voltages Recommended Operating Conditions Power Supply Voltages 5V supply 4.75 5 5.25 V 3.3V supply 3.135 3.3 3.465 V - -40 - 85 C Input Logic High VIH IIH<10A DVDD-1 - - V Input Logic Low VIL IIH<10A - 0.3 - 0.8 V Output Logic High, VOH IOH=-20A DVDD-0.5 - - V Output Logic Low, VOL IOL=20A - - 0.4 V Operating Temperature Digital Inputs Digital Outputs 38 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 Manufacturing Information Table 35. Device Manufacturing Characteristics Parameter Chip(s) Conditions JEDEC Moisture Sensitivity Class 3 * Maximum Temperature Gradient Unsealed parts may be exposed to 30 C 60% relative humidity for up to one week DSP and AFE * If exposed more than one week, parts must be baked at 125 C for 7 hours * Solder Profile * DSP and AFE 6 C/second maximum temperature ramp rate 10-40 seconds at 220 C-225 C (do not exceed 225 C) * 120-180 seconds above solder liquidus (approximately 183 C) Thermal Performance Table 36. Thermal Resistance Product jA at 0 LPM Air Velocity (oC/W) jA at 200 LPM Air Velocity (oC/W) 144 LPQ2 DSP 16.0 13.6 28 SSOP AFE 49.8 43.9 28 EPTSSOP AFE 37.9 32.5 NOTE: oC/W = oC/Watts LPM = Linear Feet Per Minute (LPM/196.8 = Meter/Second) JA= Thermal Resistance - Junction to Ambient Thermal data is obtained by mounting the chip set to a JEDEC standard board. The thermal performance in a custom board may vary. The following describes JEDEC standards: In August (1996), the Electronics Industries Association released Standard EIA/JESD51-3 titled, "Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages." This Standard provides guidelines for design of the test board used in taking thermal resistance measurements of integrated circuit packages. Prior to release of this Standard, thermal resistance data for similar packages varied greatly across the industry because of the use of different test board designs. In particular, the characteristics of the test board were found to have a dramatic impact on the measured Theta JA (JA). As the industry converts to using this standard test board design, the variation in thermal resistance data caused by the board should be minimized. Key features of the standard test board design are: * Board thickness: 0.062" * Board dimension: 3.0" x 4.5" for packages < 27.0 mm * Board dimension: 4.0" x 4.5" for packages > 27.0 mm The JEDEC method for specifying the thermal performance of ICs does not reflect thermal performance at the line card or system level. Equipment OEMs must take thermal management into account in the design of systems featuring high-density line cards. DO-009643-DS, Issue 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 39 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 DSL Chip Set Outline Diagrams 22.0 BSC 20.0 BSC 20.0 BSC SEE DETAIL A 0.50 BSC 1.60 MAX 0.19/0.27 DETAIL A 1.35/1.45 0.25 0-7o 0.05/0.15 0.45/0.75 1.0 REF Note: All dimensions are in millimeters. Figure 26. 144 LPQ2 and TQFP Dual-Channel DSP/Framer Outline Diagram NOTE: 144 TQFP DSP/Framer is for dual-channel SDSL CAP unframed applications only. 40 DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 22.0 BSC 20.0 BSC 2.90 x 45o 4 PLACES 20.0 BSC 15.0 REF 15.0 REF Note: All Dimensions are in millimeters (mm). Figure 27. Bottom View of an LPQ2 Package NOTE: Refer to Application Note AN-026, "Differences Between TQFP and LPQ2 Packages for GlobeSpan G22xx-series DSP/Framers," for details on the use of the LPQ2 package. DO-009643-DS, Issue 2 GlobespanVirata, Inc. -- Proprietary Use pursuant to Company Instructions 41 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 10.50 MAX. 28 15 o o 0 -8 0.55 - 0.95 DETAIL A 1 14 1.85 MAX. 5.60 MAX. DETAIL A 2.00 MAX. 0.65 TYP. 0.22 - 0.38 7.40 - 8.20 NOTE: All dimensions are in millimeters. Figure 28. GS3137-08F ILD2 in 28 SSOP package 42 DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 9.7 0.1 28 15 1.0 TYP. 0O - 8O 0.50 - 0.75 1 DETAIL A 14 6.1 0.1 0.90 0.05 DETAIL A 1.10 MAX. 0.65 BSC 0.245 0.055 Seating Plane 0.10 0.05 8.10 BSC 7.1 4.4 NOTE: All dimensions are in millimeters. EXPOSED PAD (BOTTOM) VIEW Figure 29. GS3137-08T ILD2 in 28 EPTSSOP package (Required to support HDSL2 and asymmetric PSD options for SHDSL). NOTE: Please make sure your PCB design takes into consideration the exposed PAD at the bottom of this package, which will need to be connected to the analog ground plane. The dimensions for this exposed pad are 7.1 mm x 4.4 mm located at the center of the device, as shown in the Bottom View above. Refer to Application Note AN-022, "Mounting Guidelines for GlobeSpan GS3137-08T in a 28-pin EPTSSOP Package," for detailed mounting guidelines for this package. 43 DO-009643-DS, Issue 2 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002 XDSL2TM SDSL, HDSL2 and SHDSL - ILD2 Chip Set Order Information Table 37. DSL Chip Set Part Number Product Supports Chip Set DSP/Framer ILD2 SDSL 2B1Q Only Up to 2320 kb/s G2216-208-041PF B2 144 LPQ2 GS2216-208-001P B2 28 SSOP GS3137-08F* (QTY 2) SDSL CAP Only Up to 2320 kb/s G2214-208-041DF B2 144 TQFP GS2214-208-001D B2 28 SSOP GS3137-08F* (QTY 2) G2237-208-041PT B2 144 LPQ2 GS2237-208-001P B2 G2237-208-041PT C1 144 LPQ2 GS2237-208-001P C1 SHDSL/HDSL2 Up to 2320 kb/s 28 EPTSSOP GS3137-08T (QTY 2) * The exposed PAD TSSOP (EPTSSOP) is required for designs that are upgradeable to SHDSL or HDSL2. Table 38. Device Packaging Preproduction Orders Device Part Number Package Production Orders Minimum Order Quantity Quantity Multiples Minimum Order Quantity Quantity Multiples 240 DSP GS2216-208-001P B2 144 LPQ2 60 60 240 DSP GS2214-208-001D B2 144 TQFP 60 60 240 240 DSP GS2237-208-001P B2 144 LPQ2 60 60 240 240 DSP GS2237-208-001P C1 144 LPQ2 60 60 240 240 AFE GS3137-08F 28 SSOP 50 50 500 500 AFE GS3137-08T 28 EPTSSOP 50 50 500 500 For additional information, contact GlobespanVirata, Inc. at 1-888-855-4562 (toll-free within the U.S. and Canada) or 1-732-345-7500. Visit the GlobeSpan Internet site at www.globespan.net. This GlobespanVirata, Inc. proprietary document is intended for use as specified in the Non-Disclosure Agreement (NDA). Reproduction is not permitted. Specification subject to change without notice. Printed in USA (c) GlobespanVirata, Inc. 2002. GlobespanVirata is a trademark of GlobespanVirata, Inc. All other products or services mentioned are the trademarks, service marks, or registered service marks of their representative owners. 44 DO-009643-DS, Issue 2