02172-DSH-001-E Mindspeed Technologies®December 2010
Mindspeed Proprietary and Confidential
M02172
11.3 Gbps EML Driver with Integrated Micro Controller
Features
• Data Rates to 11.3 Gbps. Single 3.3V supply
• Programmable laser bias current to 150mA
• Programmable laser modulation voltage to 2.5Vpp
• Integrated mode supports SFF-8472/SFP/SFP+ Requirements
• External micro controller mode supports SFF-8472/XFP/SFP/SFP+
requirements
• SFP/XFP compliant safety circuitry
• Provides internal Vcc switch for single point faults
• Supports both CA and CC laser configurations
• Input equalization for SFP+ requirements
• 2-wire or SPI serial interface available
• Programmable GPIO, selectable 6 bit or 10 bit DAC, output offset
control via serial interface
• Five user configurable General purpose I/Os
The M02172 is designed to drive Electroabsorption Modulated Lasers with a 50 ohm characteristic impedance
used in Transmitter optical sub-assemblies. In EML applications, the programmable offset adjustment is integrated
into the signal output. Output bias (offset) voltage which varies linearly as a function of temperature is provided as
required by some EML devices. The M02072 combines a diagnostic monitoring interface compliant with XFP, or
SFP+ and a EML driver in a compact 5mm x 5mm QFN package.
Integrated safety circuitry provides latched bias current and modulation voltage shutdown if a fault condition is
detected. In addition, external micro mode allows external micro controller to take control of the driver operation,
bypassing the internal 8051 micro controller. The device comes with firmware required for diagnostic monitoring,
offering a seamless interface for calibration and setup.
Other available solutions: M02170 - 11.3Gbps Dual Loop DML Driver with Integrated Micro Controller
M02171 - 11.3Gbps Dual Loop VCSEL Driver with Integrated Micro Controller
M02172 Interface (Integrated Mode) in SFP+ Module
SFP+ Module
10Gbe, 8G FC
TX_DIS
Rate_Sel
(AS0)
RD+
RD-
TD+
TD-
MOD DEF2
RX_LOS
Limiting Amplifier
Post Amp
Laser Driver
Micro
controller
A/ D RXP
M02172
IMOD
LOS
TIA
RD+
RD-
TX_DIS
IPIN
PD
PD
TD +
TD -
IBIAS
NVRAM
Controller
EEPROM
NVRAM1
NVRAM2
HOST CPU
/ TEST PC
ASIC / SerDes
2Wire
Interface
ROSA
RX_LOS
TX_Fault
TX_Fault
TX_Fault
Rate_sel (AS0)
MOD DEF1
MOD DEF1
MOD DEF2
Atm el
AT 24C 128
Rx_LOS
Rate_sel(AS1)
TX_DIS
TD -
Rate_sel (AS0)
R ate_s el(AS1 )
TD +
Rate_Sel
(AS1)
MOD DEF1
MOD DEF2
IPIN
+5V
SV
CC
/IBOUT
CC
Vsens /I_Offset
• Two available auxiliary 12 bit ADC inputs
• Provides complete Calibration and Firmware setup
• 86 mA typical supply current
• Operating Temperature: -40 °C to +95 °C
• 5mm x 5mm QFN package
Applications
• IEEE802.3ae 10GBASE-LR
• SFP/SFP+/XFP MSA Modules
• 10 Gigabit Ethernet Modules
• 8G Fiber Channel Modules
• SONET OC-192 Optical Transmitters
• SDH STM-64 Optical Transmitters
02172-DSH-001-E Mindspeed Technologies®2
Mindspeed Proprietary and Confidential
Ordering Information
Part Number Package Operating Temperature
M02172G-12* 32 pin, 5mm x 5mm QFN -40°C to +95°C
*The G in the part number indicates that this is an RoHS compliant package. Refer to www.mindspeed.com for additional information.
Revision History
Revision Level Date ASIC
Revision Description
E Release December 2010 -12 Update Ordering Information. Remove 8k EEPROM download option as it is
not required to meet the SFP t_init and t_serial timing requirements.
D Release June 2009 -12 Final characterization results included in specifications. Applications figure
added for Cyotpics 10T3082 EML. Minor corrections made to text
explanations.
C Advanced April 2007 -11P Added SPI, Functional description and Applications Information
B Advanced March 2007 -11P Changed pins 9,10 and 29. Updated to meet SFP+ latest Revisions
A Advanced December 2006 -11P Initial
02172-DSH-001-E Mindspeed Technologies®3
Mindspeed Proprietary and Confidential
M02172 Block Diagram
Modulation
Control
OUT+
OUT-
IPIN
Input
EQ
D
IN
-
D
IN
+
2.6V Regulator
(Analog Cir cuitr y )
RESET
Watchdog
Timer
V
CC
SRAM
NVRAM1
SDA
NVRAM2
SCL
Laser
Driver
D/A
Register
MODDEF1
/ SPI_O
MODDEF2
/ SPI _I
Registers
2-Wire
Or SPI
Precision
Analog
Bias
BIAS_R
GND
Open Loop /
Closed Loop Select
Supply_Mon
A/D
RxP
A/D
AUX1
A/D
AUX2
Cy cl ing
MUX
Supply _Mon
TxPwrMon
BIAS_Mon
MOD_Mon
DV
DD
MOD_Mon
BIAS_Mon
TxPwrMon
Soft_TxFault
10 bit
D/A
10 bit
Polarity_Control
NVRAM
Controller
Safety
Circuitry with
Latched Fault
Digital Laser
Power State
Machine
TX_POW_MON
APCSET
EN_APC_ CTRL
MODSET
DAC Loopback
D/A
MODSET
D/A
APCSET
A/D
Register
12 Bit
A/D
1.8V Regulator
(Digital Circuitry)
8051
Controller
Laser Power Control
D/A
PWA
OutBuff
/ PWA
MODSET
APCSET
PWA
OFFSET
10 bit, 6bit
GND
D/A
OFFSET
Offset
Amp
EEPROM +5V
TX_DIS
Fault
Registers
Soft_DIS
Fail
TX
Disable
Temp
Sensor
RxLOS
Main
Bias
6 bit
D/A
6 bit
GPIO(0)
10 bit
GPIO(4)
Pwdn/Rst Main
Bias
50
50
SPI_Sel
TX_Fault
GPIO (1)
/SPI_ CK
/SS /PWA
GPIO(2 )
GPIO(3)
/RS1
6 bit-1
OFFSET
OFF SET
TEST
GND
0
Vsens/I_Offset
Data_Detected
Data
Det
Compare
logic
Vsense
PD_Polarity_Swap
IBOUT
CA
IBOUT
CA
SVcc/IBOUTcc
IBOUT
CC
IBOUT
CC
PWA
Vsense
V
CC
LD
02172-DSH-001-E Mindspeed Technologies®4
Mindspeed Proprietary and Confidential
1.0 Product Specification
1.1 Absolute Maximum Ratings
These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged.
Reliable operation at these extremes for any length of time is not implied.
1.2 Recommended Operating Conditions
Table 1-1. Absolute Maximum Ratings
Symbol Parameter Rating Units
VCC 3.3 V power supply voltage -0.4 to +4.0 V
TAOperating Ambient Temperature -40 to +95 °C
TSTG Storage temperature -65 to +150 °C
IBOUT(MAX) Maximum bias output current at IBOUT 180 mA
VMOD(MAX) Max. modulation voltage 2.5 VPP
Table 1-2. Recommended Operating Conditions
Parameter Rating Units
Power supply (VCC-GND) 3.3 ±7.5% V
Operating ambient -40 to +95 (1) °C
NOTE:
1. Operating temperature is 95°C for IBIAS = 100 mA and 90°C for IBIAS = 150 mA
Product Specification
02172-DSH-001-E Mindspeed Technologies®5
Mindspeed Proprietary and Confidential
1.3 DC Characteristics
VCC = 3.05 to 3.55V, TA = -40°C to +95°C, unless otherwise noted. Typical values are VCC = 3.3V, TA = 25°C,
VMOD = 1Vpp, IBIAS = 40mA, unless otherwise noted.
Table 1-3. DC Characteristics
Symbol Parameter Conditions Minimum Typical Maximum Units
VCC V
CC operating voltage 3.05 3.3 3.55 V
ICC ICC supply current (1) High-rate mode
Low-rate mode
Increase due to enabling Pulse Width Adjust
–
–
–
86
80
2
134
–
–
mA
ICC_DIS ICC when part Disabled Device is disabled – 36 48 mA
VCCTHL 3.3 V supply detection (low voltage)
threshold
Minimum of either VCC supply low detection
voltage or internal Power on Reset voltage
–2.62.85V
VCCTHH 3.3 V supply detection (high voltage)
threshold
3.55 3.8 4.00 V
VFAULTL Low fault voltage detection threshold
(IBOUTCA, BIAS_R)
Fault condition occurs when voltage drops
below this level
– 400 600 mV
VFAULTH High fault voltage detection threshold
(IBOUTcc)
Fault condition occurs when voltage exceeds
this level
VCC - 0.6 VCC - 0.4 – V
IBIAS Bias current adjust range (2)
At IBOUTCA, V(IBOUTCA) > 1.5 V
At IBOUTCC., V(IBOUTCC) < 2.5 V 5 – 150 mA
IBIAS(OFF) Bias current with output disabled
TX_DIS = high and/or SOFT_DIS = high;
V(IBOUTCA) = VCC for common anode and
V(IBOUTCC)= 0V for common cathode
- 5 150 μA
BIASRATIO
CA
Ratio of bias current to BIASMON
current in common anode mode
V(IBOUTCA) = 1.5 V 102 113 124 A/A
BIASRATIO
CC
Ratio of bias current to BIASMON
current in common cathode mode
V(IBOUTCC) = 2.0 V 103.5 115 126 A/A
VMD Monitor diode reverse bias voltage Minimum is with maximum IPIN current 1.5 2.0 VCC V
IMD Monitor diode current adjustment
range
For stable APC loop operation 10 – 1400 μA
CMDMAX Maximum monitor photodiode
capacitance (3)
For stable APC loop operation in analog
closed mode; includes any additional
parasitic capacitance
– – 100 pF
VIH_DIS TTL/CMOS input high voltage
(TX_DIS, Pwdn/Rst, SPI_sel, Test)
2.0 – VCC V
VIL_DIS TTL/CMOS input low voltage (TX_DIS,
Pwdn/Rst, SPI_sel, Test)
0–0.8V
VIH_I0 GPIO input high voltage
When configured as a digital input
2.0 – VCC V
VIL_IO GPIO input low voltage 0 – 0.8 V
ILK_IO_0-4 GPIO 0-4 leakage current When configured as a tristated digital input -10 0 10 μA
VIH_LOS LOS input high voltage 2.0 – VCC V
VIL_LOS LOS input low voltage 0 – 0.8 V
Product Specification
02172-DSH-001-E Mindspeed Technologies®6
Mindspeed Proprietary and Confidential
VOH_FAIL Logic output high voltage (FAIL) With external 10 kΩ pull-up to VCC VCC - 0.6 – – V
VOL_FAIL Logic output low voltage (FAIL) IOL = 1.2 mA – – 0.4 V
VOH_IO GPIO output high voltage When configured as a digital output
IOH = -2 mA.
2.4 – VCC V
VOL_IO GPIO output low voltage When configured as a digital output
IOL = 2 mA
0–0.4V
RIN Differential input resistance 85 100 115 Ω
ROUT Output Resistance 42 52 62 Ω
VCMSELF Self-biased common mode input
voltage
–V
CC - 1.3 – V
VINCM Common-mode input compliance
voltage
Data inputs VCC - 1.5 – VCC
-VIN(Diff)/4
V
VIN(Diff) Differential input voltage Peak to Peak, Equalizer off 80 – 1000 mV
For SFP+ applications. (Refer to the Signal
compliance mask in Figure 1-1) Equalizer on
X1:SFP+ Eye Mask compliance
X2: SFP+ Eye Mask compliance
Y1:SFP+ Eye Mask compliance
Y2: SFP+ Eye Mask compliance
75
0.14
0.35
400
UI
UI
mV
mV
NOTES:
1. Excludes bias and modulation currents delivered to the laser. ICC maximum is for IBIAS = 150 mA and IMOD = 2.2 VPP
2. The M02172 is designed to support either common anode and common cathode lasers. Once deployed, it is not intended to be switched
between laser types.
Figure 1-1. Differential Input signal Compliance mask at the input of SFP+ module
Table 1-3. DC Characteristics
Symbol Parameter Conditions Minimum Typical Maximum Units
Product Specification
02172-DSH-001-E Mindspeed Technologies®7
Mindspeed Proprietary and Confidential
1.4 AC Characteristics
VCC = 3.05 to 3.55V, TA = -40°C to +95°C, unless otherwise noted. Typical values are VCC = 3.3V, TA = 25°C,
VMOD = 1Vpp, IBIAS = 40mA, unless otherwise noted.All values measured with the input equalizer on and using
6 inches (15 cm) of FR4 (4000-6/8) non-back drilled stripline trace length.
Table 1-4. AC Characteristics
Symbol Parameter Conditions Minimum Typical Maximum Units
VMOD Modulation voltage adjust range Vmax= Vmod + Voffset < 2.2VPP
OUTP > 0.8V to keep sufficient head room
0.5 – 2.2 VPP
Output offset adjust range Output terminated into 50 Ω0–1 V
VMOD_RATIO Ratio of modulation voltage to
MODMON current
= (VMOD)/IMODMON –1.6–V/mA
PWA Pulse width adjustment range 50% crossing point at DAC mid range 20 – 80 %
tR / tFModulation output rise / fall times (1) 20% to 80% into 50 Ω load. Measured
using alternating 1-0 pattern at 2.5 Gbps
–
–
28 (2)
40 (3)
37
75
ps
ps
OS Overshoot of modulation output Into 50 Ω load – 5 – %
RJ Random jitter Measured by 7.5 GHz Bessel filter at output – 0.4 psRMS
DJ Modulation output deterministic jitter (2) Peak-to-peak into 50 Ω load using
215-1 PRBS at 10.3 Gbps
815ps
NOTES:
1. With RS1=1, For Tx Signalling rates > 4.25Gb/s
2. With RS1=0, For Tx Signalling rates ≤ 4.25Gb/s
3. Includes Duty Cycle Distortion
Product Specification
02172-DSH-001-E Mindspeed Technologies®8
Mindspeed Proprietary and Confidential
1.5 Soft Control Timing Management
VCC = 3.05 to 3.55V, TA = -40°C to +95°C, unless otherwise noted. Typical values are VCC = 3.3V, TA = 25°C unless
otherwise noted using internal micro controller.
Table 1-5. I/O Timing for Soft Control and Status Functions
Symbol Parameter Conditions Typ Max Units
t_off Tx_DIS assert time Time from TX_DIS bit set (1) until optical output falls below
10% of nominal
– 100 ms
t_on TX_DIS deassert time Time from TX_DIS bit cleared (1) until optical output rises
above 90% of nominal
– 100 ms
t_init Time to initialize, including
reset of TX_Fault
Time from power on or negation of TX_FAULT using
TX_DISABLE until transmitter output is stable
300 ms
t_fault TX_Fault assert time Time from fault to TX_FAULT bit set 100 ms
t_loss_on RX_LOS assert time Time from LOS state to RX_LOS bit set 100 ms
t_loss_off LOS deassert time Time from non-LOS state to RX_LOS bit cleared 100 ms
t_serial Serial bus hardware ready Time from power on until host can read from the serial bus 300 ms
NOTE:
1. Measured from falling clock edge after stop bit of write transaction
Product Specification
02172-DSH-001-E Mindspeed Technologies®9
Mindspeed Proprietary and Confidential
1.6 Monitors ADC Specifications
VCC = 3.05 to 3.55V, TA = -40°C to +95°C, unless otherwise noted. Typical values are VCC = 3.3V, TA = 25°C unless
otherwise noted.
Table 1-6. A/D Electrical Specifications
Input Type
Range Accuracy
Notes
Minimum Maximum Units Minimum Maximum Units
Tx Power Monitor (Internal)
Current Sinking
10 1400 μA -10 +10 % 1,2,3
Bias Current Monitor (Internal)
Current Sinking
10 1400 μA -10 +10 % 1,2,3
Modulation Current Monitor (Internal)
Current Sinking
10 1400 μA -10 +10 % 1,2,3
Rx Power Monitor
(External)
Current Sinking
3 1400 μA -10 +10 % 1,2,3,4
Voltage mode 0 2.3 V -15 +15 mV 2,8,9
Power Supply Monitor (Internal)
Voltage
2.85 3.6 V -25 +25 mV 2,6
Internal Temperature Monitor (Internal)
Temperature
-40 +105 °C -3 +3 °C 2,7
AUX1, AUX2
Current Sinking 10 1400 μA -10 +10 % 1,2,3,4
Current Sourcing 10 1400 μA -10 +10 % 1,2,4,5
Voltage 0 2.3 V -15 +15 mV 2,8,9
Update Rate All ADCs 1 kHz – – – –
NOTES:
1. For definition of sourcing and sinking see Figure 1-2.
2. Module calibration required for valid units.
3. Code 000h means 0 μA, code FFFh means 1600 μA when sinking current. However, the result is only valid in the range specified.
4. Minimum value of monitored current is achieved with internal digital filter (default setting).
5. Code 000h means 0 μA, code FFFh means 1500 μA when sourcing current. However, the result is only valid in the range specified
6. Code 000h means 0 V, code FFFh means 6.55 V. However, the supply monitoring value is only valid in the range specified.
7. ADC output will be offset binary. Code 000h means the lowest temperature the ADC can measure, while FFFh means the highest temperature the
ADC can measure.
8. Input impedance of ADC is larger than 100 kΩ.
9. Code 000h means 0 V, code FFFh means 2.3 V. However, the result is only valid in the range specified.
Product Specification
02172-DSH-001-E Mindspeed Technologies®10
Mindspeed Proprietary and Confidential
1.7 DAC Specifications
VCC = 3.05 to 3.55V, TA = -40°C to +95°C, unless otherwise noted. Typical values are VCC = 3.3V, TA = 25°C.
1.7.1 Bias and Modulation Current DAC Specifications
1.7.2 Internal 6 bit DAC (PWA and Offset) Specifications
Table 1-7. Laser Driver Bias and Modulation Current D/A
Parameter Minimum Typical Maximum Units
Resolution –12–bits
Table 1-8. Internal 6 bit DAC (1)
Parameter Minimum Typical Maximum Units
Resolution – 6 – bits
Full scale output (current sinking) 1.01 – 1.13 mA
Linearity
DNL
INL
-1
-1
–
–
+1
+1
LSB
LSB
Offset -5 – +5 μA
Settling time – 10 – μs
Compliance (voltage for sinking current) 1.1 – 2.6 V
NOTE:
1. The pulse width adjust DAC is mapped to GPIO(2) and the Offset DAC is mapped to GPIO(4).
Figure 1-2. DAC Output Definitions
I
SINK
DAC_OUT
DAC Sinking
Current
DAC Sourcing
Current
V
CC
DAC_OUT
I
SOURCE
Product Specification
02172-DSH-001-E Mindspeed Technologies®11
Mindspeed Proprietary and Confidential
1.7.3 General Purpose 6 bit DAC Specifications
VCC = 3.05 to 3.55V, TA = -40°C to +95°C, unless otherwise noted. Typical values are VCC = 3.3V, TA = 25°C.
1.7.4 General Purpose 10 bit DAC Specifications
VCC = 3.05 to 3.55V, TA = -40°C to +95°C, unless otherwise noted. Typical values are VCC = 3.3V, TA = 25°C.
Table 1-9. General Purpose 6 bit DAC (1)
Parameter Minimum Typical Maximum Units
Resolution – 6 – bits
Full scale output current (current sourcing or sinking) 1.01 1.07 1.13 mA
Linearity
DNL
INL
-1
-1
–
–
+1
+1
LSB
LSB
Offset
Current source
Current sink
–
-5
–
-
+5
+5
μA
μA
Settling time – 10 – μs
Voltage Compliance
Current source
Current sink
0
1.1
–
-
1.1
2.6
V
V
NOTE:
1. The General purpose 6 bit DAC is mapped to GPIO(1).
Table 1-10. General Purpose10 bit DAC (1) (1 of 2)
Parameter Minimum Typical Maximum Units
Resolution –10–bits
Voltage Mode Operation (2)
Full scale output voltage 1.37 1.45 +1.53 V
Linearity
DNL
INL
-1
-4
–
–
+1
+4
LSB
LSB
Offset – – +1.5 mV
Settling time – 10 – μs
Output Resistance 0.8 1 1.2 kΩ
Current Mode Operation (2, 3)
Full scale output current (current sourcing) 1.40 1.48 +1.56 mA
Linearity
DNL
INL
-1
-4
–
–
+1
+4
LSB
LSB
Offset – – +1.5 μA
Product Specification
02172-DSH-001-E Mindspeed Technologies®12
Mindspeed Proprietary and Confidential
1.8 Inrush Current Specification
VCC = 3.05 to 3.55V, TA = -40°C to +95°C, unless otherwise noted. Typical values are VCC = 3.3V, TA = 25°C.
1.9 Host two-wire Timing Specifications
VCC = 3.05 to 3.55V, TA = -40°C to +95°C, unless otherwise noted. Typical values are VCC = 3.3V, TA = 25°C.
(MODDEF(1)/SCL and MODDEF(2)/SDA) (Standard Mode or Fast Mode two-wire serial) and NVRAM Controller
Timing Specifications (NVRAM1 (SDA) AND NVRAM2 (SCL)) (Fast Mode two-wire serial).
Settling time – 10 – μs
Compliance (voltage for sourcing current) 0 – 1.1 V
NOTE:
1. The General Purpose 10 bit DAC is mapped to GPIO(0).
2. Output may either be a current or a voltage. User selectable.
3. In current mode, DAC output can only source current. See Figure 1-2.
Table 1-11. XFP/SFP+ POR Characteristics
Parameter Minimum Typical Maximum Units
ICC Peak Inrush (ICC_peak)––50%
ICC Ramp rate (dICC/dt) (2) SFP+
XFP
50
100
mA/μs
mA/μs
NOTE:
1. Excludes external capacitors. Modules which present a small capacitive load to the host during hotplug are exempt from the inrush current
requirements since they limit the total in rush charge.
Table 1-12. Host and NVRAM Controller Timing Specifications (see Figure 1-3) (1 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Units
fSCL_HOST Clock Frequency, SCL (1) ––400kHz
fSCL_NVRAM Clock Frequency, SCL 530 – 900 kHz
tLOW Clock Pulse Width Low 1.3 – – μs
tHIGH Clock Pulse Width High 1.0 – – μs
tAA Clock Low to Data Out Valid 0.05 – 0.9 μs
tBUF Time the bus must be free before a new
transmission can start
1.3 – – μs
tHDSTA Start Hold Time 0.6 – – μs
tSUSTA Start Set-up Time 0.6 – – μs
tHDDAT Data In Hold Time 3 – – ns
Table 1-10. General Purpose10 bit DAC (1) (2 of 2)
Parameter Minimum Typical Maximum Units
Product Specification
02172-DSH-001-E Mindspeed Technologies®13
Mindspeed Proprietary and Confidential
tSUDAT Data In Set-up Time 100 – – ns
tSUSTO Stop Set-up Time 0.6 – – μs
tf_HOST Host Output fall time (2) 20-80%. Capacitive load for each bus line =
10 to 400 pF; RPULL-UP = 4.7 to 10 kΩ
––100ns
RPULL-UP_EE Outputs (NVRAM1 and NVRAM2)
internal pull-up resistor value (3)
–8–kΩ
tf_NVRAM NVRAM Controller Output fall time (3) 20-80%. No external pull-up resistor; 13 pf
loading
– – 50 ns
tr_NVRAM NVRAM Controller Output rise time (3) 20-80%. No external pull-up resistor; 13 pf
loading
––300ns
Time bus must be free before a new
transmission start.
Between STOP and START 20 μs
tDH Data Out Hold Time 50 – – ns
NOTES:
1. The host two wire bus is fully compliant with SFP timing requirements to run at 400 kHz.
2. For the host interface, the output rise time is determined by user selection of RPULL-UP and the total line capacitance.
3. NVRAM two-wire bus only. Since the M02170 NVRAM1/NVRAM2 is a dedicated two-wire serial bus to the external EEPROM, the M02170
internally includes RPULL-UP to eliminate adding these extra external components.
Figure 1-3. Host and NVRAM Controller Timing Diagrams
Table 1-12. Host and NVRAM Controller Timing Specifications (see Figure 1-3) (2 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Units
Product Specification
02172-DSH-001-E Mindspeed Technologies®14
Mindspeed Proprietary and Confidential
1.10 SPI Electrical Timing Specifications
VCC = 3.05 to 3.55V, TA = -40°C to +95°C, unless otherwise noted. Typical values are VCC = 3.3V, TA = 25°C.
Table 1-13. SFP Electrical Timing Specifications
Symbol Parameter Min Typ Max Units
SPI_CK Frequency 10 MHz
SPI_CK Pulse Width 50% duty cycle %
Rise/Fall time 3.6 ns
tsu Setup time 10 ns
thd Hold time 10 ns
tout_ck Out to SPI_CK 0.5 x tsck ns
tck_out SPI_CK to Out 10 ns
tck_outhigh SPI_CK to Out high 10 ns
Figure 1-4. SPI Timing Diagram. External controller is Master and M02172 is Slave.
SCK
MSB
MSB LSB
LSB
tsu
SS
(Low)
MOSI
MISO
thd
tck_out
tout_ck
tck_outhigh
SCK Freq SCK pw
Product Specification
02172-DSH-001-E Mindspeed Technologies®15
Mindspeed Proprietary and Confidential
1.11 Control and Status I/O Timing
VCC = 3.05 to 3.55V, TA = -40°C to +95°C, unless otherwise noted. Typical values are VCC = 3.3V, TA = 25°C,
unless otherwise noted. Timing values are for hardware pins.
Table 1-14. Timing Requirements of SFP/XFP/SFP+ Control and Status I/O
Symbol Parameter Conditions Minimum Typical Maximum Units
t_off TX_DIS assert time Rising edge of TX_DIS to fall of output signal
below 10% of nominal
–10μs
t_on TX_DIS negate time Falling edge of TX_DIS to rise of output signal
above 90% of nominal
–1ms
t_init(1) Time to initialize, including reset of
TX_Fault
Time from power on or negation of Tx_Fault
using TX_DIS until laser driver output is stable
– 300 ms
t_fault TX_Fault assert time From occurrence of fault condition to TX_Fault
high
– 100 μs
t_reset TX_DIS time to start reset Time TX_DIS must be held high to reset
TX_Fault.
TX_DIS pulse width required to initialize safety
circuitry or reset a latched fault.
10 μs
P-Down/
RST_on
P_Down /RST assert delay From power down initiation 100 μs
P_down reset time Min length of P_down assert to initiate reset 10 μs
NOTE:
1. From power on or hotplug after supply OK or from falling edge of P_Down/Rst
02172-DSH-001-E Mindspeed Technologies®16
Mindspeed Proprietary and Confidential
2.0 Pin Definitions
Table 2-1. Pin Descriptions
QFN Pin
Number Name Function
1 NVRAM1 (SDA) SDA interface to external EEPROM (internally pulled up to VCC with 8 kΩ)
2 NVRAM2 (SCL) SCL interface to external EEPROM (internally pulled up to VCC with 8 kΩ)
3 MODDEF(1) /
SPI_O
For 2-wire: MODDEF1 is the serial clock
For SPI: SPI_O is slave output
4 MODDEF(2) /
SPI_I
For 2-wire: MODDEF2 is the serial data
For SPI: SPI_I is slave input
5V
CC 3.3V power supply.Connect to 3.3V
6 Pwdn/Rst Control input. 60 kΩ internal pull up to VCC. When held high, forces the part into a power down standby mode. The
negative edge of Pwdn/Rst signal initiates a complete part (POR) reset. Ground for normal operation
7 DINP Positive Data Input
8 DINN Negative Data Input
9 SPI_sel Control input. When held high indicates SPI is selected (internally pulled down with 60 kΩ). When low I2C is
selected
10 VCCLD VCC for the Laser Driver section. Connect to VCC
11 TX_Fault Safety circuit fault indicator. Open collector output, external resistor pull up to host_VCC required
12 TX_DIS Control input for Transmit disable. When high or left floating, shuts off both bias and modulation outputs. Set low
for normal operation. 7 kΩ internal resistor pull-up to VCC
13 GND Ground. Must be connected to ground for proper device operation
14 IPIN Monitor photodiode input
15 IBOUTCA Laser bias current output
16 GND0 Ground for modulation output stage. Must be connected to ground for proper device operation
17 Vsense Can be input or output. For Apogee Imon current sense (Input). For non Apogee, offset control (output)
18 OUTP Positive modulation output
19 OUTN Negative modulation output
20 GPIO(4) /
Offset DAC
Analog General Purpose I/O. Input or Output or 6 bit DAC (current sinking only)
21 SVCC/IBOUTCC Safety logic controlled VCC to laser anode
22 A/DAUX2 Auxiliary A/D input. Should be left floating when using Vsense or (Apogee mode) feature
23 BIAS_R External resistor for precision bias reference
24 A/DAUX1 Auxiliary A/D input
Pin Definitions
02172-DSH-001-E Mindspeed Technologies®17
Mindspeed Proprietary and Confidential
25 A/DRxP A/D input for received power monitor
26 TEST Input for self test. When high, self test is initiated. Connect to ground for normal operation. (internally pulled down
with 60 kΩ)
27 RxLOS Can be selectable Input or Output. If used as input pin, it is Loss of signal from limiting amp (internally pulled down
with 60 kΩ). If used as output, it is an open collector output
28 GPIO(3)/RS1 For SFP+: Can be configured as RS1 rate select (internally pulled down with 60 kΩ using an internal switch)
For non SFP+: General purpose I/O
29 GPIO(2)/SS/
PWA
For SPI interface: Slave Select is input to M02172 (should be externally terminated with resistor required for
application). Must be low before the data transaction and stay low for the duration of the transaction.
For non-SPI: General purpose I/O or 6 bit DAC. Current sink only
30 GPIO(1)/
SPI_CK/ 6 bit
DAC
For SPI interface: SPI_CK is the clock input (10MHz)
For non SPI: General purpose I/O or 6 bit DAC (current sourcing or sinking)
31 GPIO(0)
/10 bit DAC
General purpose I/O or 10 bit DAC. Output can be current or voltage. In current mode, DAC output can only source
current
32 DVDD Internally regulated to 1.8V for Digital circuitry. Typically connect a 10nF capacitor to ground
Paddle GND Ground. Must be connected to ground for proper device operation
Table 2-2. GPIO PIN Mapping
QFN Pin
Number Pin Name Integrated Mode
SFP Function
External Micro mode
SFP Function
External Micro mode
XFP Function
20 GPIO(4)/ OFFSET DAC GPIO or DAC GPIO or DAC GPIO or DAC
28 GPIO(3)/ RS1 RS1 or GPIO RS1 or GPIO GPIO
29 GPIO(2)/ SS /PWA DAC GPIO or DAC GPIO or DAC GPIO or DAC
30 GPIO(1)/ SPI_CK/ 6 bit DAC GPIO or DAC GPIO or SPI or DAC GPIO or SPI or DAC
31 GPIO(0)/ 10 bit DAC GPIO or DAC GPIO or DAC GPIO or DAC
Table 2-1. Pin Descriptions
QFN Pin
Number Name Function
Pin Definitions
02172-DSH-001-E Mindspeed Technologies®18
Mindspeed Proprietary and Confidential
Figure 2-1. Pin Assignments for M02172 Device
NOTE: The package bottom must be adequately grounded to ensure correct thermal and electrical performance.
Please reference the Amkor Application Note “Application Notes for Surface Mount Assembly of Amkor’s
MicroLeadFrame (MLF) Packages” at www.amkor.com
(http://www.amkor.com/products/notes_papers/MLFAppNote.pdf).
M02172 8/10G EML Driver + Micro Controller Pinout
1
2
3
4
11
10
9
8
7
6
5
27 26 25
18
17
16
15
141312
31 30 28
5mm X 5mm QFN
package
Ground Downbond to
Center Paddle
BIAS_R
SVCC
OUTN
GNDO
IB
OUTA
IPIN
21
20
19
23
22
24
2932
NVRAM1
SDA
RxLOS
DVDD
A/D
RXP
GND
A/D
AUX2
DINP
NVRAM2
SCL
VCC
DINN
TX_DIS
Pwdn/Rst
TX_Fault
OUTP
A/D
AUX1
GPIO(4)
/Offset
Vsense
/I_
Offset
MOD-DEF1
/SPI_O
MOD-DEF2
/SPI_I
SPI_Sel
Test
GPIO(3)
/AS1
GPIO(0)
/10bit-DAC
GP IO(1)
/SPI_CK
/6bit DAC
VccLD
GPIO(2)
/SSB
/PWA
02172-DSH-001-E Mindspeed Technologies®19
Mindspeed Proprietary and Confidential
3.0 Functional Description
3.1 Overview
The M02172 combines a EML Driver with a SFF-8472 compliant Digital Diagnostic Monitoring Interface for fiber
optic transceivers.
The M02172 monitors temperature, voltage, bias and modulation current, transmit and receive power, and other
user-defined external parameters. Internal ADCs and comparators allow each parameter to be compared against
user-defined threshold levels to provide indication of a fault condition. Integration of the laser driver provides digital
control of the laser bias and modulation currents in addition to pulse width control of the modulation current.
Integrated safety circuitry provides latched bias and modulation current shutdown if a fault condition is detected
and provides an internal VCC switch.
Figure 3-1. M02172 Architecture
GPIOs Microprocessor
System
Program
/Data
Memory
Device
Registers
SFP
Memory
(2 port)
DDMI
Memory
(2 port)
User/
Vendor
Memory
mux
mux
mux
mux
mux
NVRAM
Controller
Two-Wire
Interface
Controller
Laser
Controller
Laser
Driver
SRAM
External
EEPROM
Functional Description
02172-DSH-001-E Mindspeed Technologies®20
Mindspeed Proprietary and Confidential
3.2 Features
• Laser Driver with integrated digital diagnostic functions
• 155 Mb/s – 11.3 Gb/s operation
• Integrated power supply switch for redundant shutdown
• Dual closed-loop OMA control, single-closed-loop and open-loop operation with independently programmable
bias and modulation currents
• Compliant with SFF-8431, Rev 3.1 “SFP+” standard for 8.5 and 10.3Gbps
• Compliant with SFF-8472, Rev 10.3: Diagnostic Monitoring Interface for Optical Transceivers
•Temperature
• Bias current
• TX Optical Power
• RX Optical Power
• Supply voltage
• Software control of Rate Select, Tx Fault, Tx Disable and Rx LOS
• Alarm/Warning flags are implemented for monitored quantities
• Supports Internal test and calibration
• Automatic power control
• SFP/SFP+ compliant safety circuitry with user selectable bypass
• Pulse width adjustment compensates for asymmetrical laser rise and fall times
• Five user configurable General Purpose I/Os
•Up to four user configurable DAC outputs
• Two available auxiliary 12 bit ADC inputs
• SPI or 2-wire interface, compatible with Serial ID, as defined in the SFP MSA
• Internal A/D – D/A loopback for real time diagnostics
• User and OEM password protection
• Power-on meter (journal timer)
• 12 bit ADC resolution results in exceptional monitor accuracies
• Compact: 32 pin QFN, 5mm x 5mm
• Operating Temp: -40 °C to +95 °C
3.3 General Description
3.3.1 Overview
The M02172 integrates the digital diagnostic monitoring requirements of SFF-8472 with a highly integrated laser
driver intended for applications to 11.3 Gbps. The level of integration allows easy set up and calibration of laser
power and extinction ratio. The timing requirements of SFF-8472 and the SFP/SFP+ MSA are met when using the
M02172 including soft control timing and status functions of both standards. In addition, integration allows the
modulation current monitor to be available digitally and two auxiliary A/Ds are available for customer use in
providing features beyond the standards requirements.
Functional Description
02172-DSH-001-E Mindspeed Technologies®21
Mindspeed Proprietary and Confidential
The M02172 provides a turn-key solution for SFF-8472 and SFP/SFP+ compliant modules by including firmware
that provides the mandatory features of both and enables the manufacturer to easily implement any optional
features of their choosing using a simple GUI interface. The M02172 enables automatic module calibration and test
that allows for a significant reduction in test cost and complexity.
Many features are user-adjustable, including the APC loop bias control, modulation current including temperature
compensation control of the modulation current and laser pulse width adjustment. The M02172 utilizes control of
both the bias and modulation currents which allows for management of the optical extinction ratio by compensating
for the effects of temperature and aging of the laser.
Safety circuitry is also included to provide a latched shut-down of laser bias and modulation current if a fault
condition occurs. An internal VCC switch provides redundant shutdown when operating the device. Safety logic
behavior is user configurable.
3.3.2 DDMI Features
This section provides detail on how the Digital Diagnostic Monitoring Interface specified in SFF-8472 is supported
in the M02172. The DDMI data is stored in an external EEPROM and accessed through the two-wire serial
interface. EEPROM memory is also required to store SFP data, microprocessor code and initial device register
values. In order to minimize the additional module complexity and expense of multiple external EEPROMs, the
M02172 employs internal memory caches to store the SFP and DDMI data on-chip.
There are two serial interfaces. One (pins MODDEF2_SDA and MODDEF1_SCL) provides access by the host to
the stored data. The other (pins NVRAM1_SDA and NVRAM2_SCL) is the interface to the single external
EEPROM. Upon power-up, when the device comes out of reset, the device register values are downloaded,
followed by the SFP and DDMI data and finally, the microprocessor program code is downloaded and the
microprocessor enabled. The timing requirements are given in the Product Specifications Section 1.5, “Soft Control
Timing Management,” on page 8.
Two time-stamped versions of the DDMI data are stored in the EEPROM (DDMI 0 and DDMI 1, see Figure 4-4) to
ensure that at least one valid data set is available in the event that a module failure occurred when the M02172 was
in process of writing data from the on-chip cache memory to the external EEPROM. Each data set (DDMI 0 and
DDMI 1) has a checksum for the purpose of determining data integrity. The most recent valid data set is copied to
the cache. The SFP data and the microprocessor program code each have their own checksum to determine their
integrity similar to the DDMI data.
While the module is in an active state, the data in the DDMI cache is updated by the microprocessor at intervals in
compliance with the timing requirements of SFF-8472. The host also has access through the serial interface. To
comply with the data integrity requirement, the microprocessor first checks to determine if the host is accessing
data before updating the memory. In that event, the update is delayed until the activity ceases. Before the update
occurs, the microprocessor also disables the acknowledgement signal of the two-wire interface to prevent the host
from initiating a memory access while the cache is being updated.
3.3.2.1 DDMI Real-Time Diagnostic Monitoring
Each monitor is independently enabled (to conserve power) by programming the corresponding bit of the ADC_EN
register to a 1. The M02172 DDMI memory is updated by the internal M02172 controller with an update interval of
< 100 ms (typically 30 ms). The internal M02172 controller must supply the appropriate password before it is
allowed to update the DDMI information to prevent corruption of the data if the controller arrives at an unstable
state.
The “Ack” of the two-wire interface is disabled during DDMI update. To minimize the duration of the interruption of
host access, the internal M02172 controller writes the updated information to shadow registers which is then burst-
loaded into the DDMI memory. The interruption of host access will be < 1.2 μs.
Functional Description
02172-DSH-001-E Mindspeed Technologies®22
Mindspeed Proprietary and Confidential
The DDMI information is periodically copied back to the external EEPROM for protection against loss due to events
such as power outages. The frequency of backup is once every twelve hours (derived from the journal timer).
Backup of serial ID, diagnostic and other on-chip memory can be initiated by the host through the two-wire
interface.
Having separate on-chip and external nonvolatile storage of the DDMI data is a distinct advantage of the M02172
because it allows rapid update of the DDMI data available to the host without exhausting the write endurance of the
EEPROM in a short time period. The two most recent backups of the DDMI data are maintained in the external
EEPROM at all times. This ensures that a valid data set remains if there is a module failure during the backup
operation. Each version has a checksum and a time stamp which determines the most current version. If the
information must be reloaded to the on-chip memory, the most recent version with a valid checksum is copied from
the EEPROM. The backup operation is transparent to the host with no access interruption.
3.3.3 Calibration
The M02172 supports both internal and external calibration as defined by SFF-8472. For internal calibration, the
calibration is performed by the M02172 internal controller under software control. For external calibration, the
controller simply writes the ADC values to the DDMI memory. One of the two calibrations modes must be enabled
to achieve the accuracy specifications.
3.3.4 Alarm and Warning Thresholds
The M02172 supports all the alarm and warning indications defined in SFF-8472. Each A/D quantity has a
corresponding high alarm, low alarm, high warning and low warning threshold. These values are defined by the
module manufacturer during module initialization and/or calibration and allow the module user to determine when a
particular value is outside of “normal” limits as determined by the module manufacturer. For these indications to be
active the thresholds defined in Table 3.15 of SFF-8472 Rev 10.3 “Alarm and Warning Thresholds (2-Wire Address
A2h)” must be set. The nominal response time from an alarm or warning condition to the update of the
corresponding status bit is 100 msec.
The M02172 provides very accurate indication of the present conditions of the module. The sampled diagnostic
monitoring signals are stored in device registers. The comparison of each to the corresponding stored threshold
values is performed under program control of the microprocessor. Using firmware it is possible to compensate the
alarm and warning indications for temperature variations.
3.3.5 Optional Status and Control Bits
The M02172 supports all optional status and control bits (byte 110 of 2 Wire address A2h)defined in Table 3.17 of
SFF-8472 Rev 10.3.
3.3.6 Data Inputs
The inputs to the internal data buffer are self-biased through resistors to an internal reference voltage VTT
. Input
signals can be AC coupled to the part by allowing VTT to float, which sets the common mode input voltage to
approximately VCC - 1.3V. Both CML and PECL input signals can be AC coupled to the M02172.
3.3.7 Equalization
For SFP+ applications, the input data can be equalized by enabling the equalizer. SFP+ specifies the jitter
requirements at the input of the transmitter under various host board transmission line lengths for both microstrip
and stripline. Table 3-1 shows common host board configurations with maximum recommended SFP+ host board
trace lengths.
Functional Description
02172-DSH-001-E Mindspeed Technologies®23
Mindspeed Proprietary and Confidential
3.3.8 Data Polarity / Pulse Width Adjust
After the data passes through the data input buffer, it enters the pulse width adjust buffer. It incorporates a polarity
selection as well as a pulse width adjustment control to compensate for laser pulse width distortion. By adjusting
the current from the PWA DAC, pulse width can be adjusted from 20% to 80%. Pulse width control can be disabled
by setting the PWA_EN bit low, resulting in approximately 50% crossing point at the output and reduces the supply
current by 2mA.
3.3.9 Output Buffer
After the data passes through the pulse width adjust buffer, it enters the output buffer. The output buffer reshapes
and ground reference the signal in order to drive the output stage with enough speed and correct output levels.
3.3.10 Photodiode polarity
M02172 supports common anode or common cathode photodiode independently from the laser mode.
3.3.11 Rate select function
To comply with the SFP+ rate select requirement, when the device in low rate mode, power is reduced in the signal
path and the compensation is switched on at the outputs.
3.3.12 Pwdn/Rst
This is a multifunction input pin for module power down and reset. When held “high”, in order to meet the power
dissipation requirements of XFP applications, the laser is forced to low rate mode and the modulation and bias
currents are not set by the DAC. They are set by an internal current reference of low value in order to reduce the
power dissipation of the module.
3.3.13 Laser Driver Output Stage
The output stage incorporates feedback to maintain performance over the range of laser modulation current. The
output stage is nominally configured to drive EML and DML with 50Ω characteristic impedance. The M02172 has
internal 50Ω terminations between the outputs OUTP, OUTN and the internal supply. In EML applications,
programmable offset adjustment is integrated into the signal output.
The laser driver output stage is separately grounded from the rest of the circuitry (through GNDO) for optimum
performance and control of output characteristics.
Two independent high-frequency compensation networks are included to allow additional flexibility with setting the
output response characteristics. A binary network and an additional three bits (OC0, OC1, OC2) can be used to
Table 3-1. Host board PCB maximum trace lengths
Type Material Trace Width (mm) Loss Tan Trace Length (mm)
Microstrip Standard FR4 (4000-6/8) 0.3 0.022 200
Nelco (4000-13) 0.3 0.016 300
Stripline Standard FR4 (4000-6/8) 0.125 0.022 150
Nelco (4000-13) 0.125 0.016 200
Functional Description
02172-DSH-001-E Mindspeed Technologies®24
Mindspeed Proprietary and Confidential
tune two separate internal RC networks at the M02172 output providing control of output stage damping in order to
optimize the optical eye diagram.
Laser modulation current is controlled by adjusting the MODSET DAC current. The modulation current can be
temperature compensated in the digital state machine by changing the MODSET DAC current by a programmed
ratio to the temperature ADC reading. Refer to Section 3.3.16, “Modulation Current Control,” on page 27.
When Pwdn/Rst is high, the MODSET DAC is disconnected and the modulation is set below its lowest value.
3.3.14 GPIO Operation
The M02172 has five GPIOs that can individually be configured as a digital input, a digital input with an interrupt, a
digital output, or the output of a DAC. When configured as a digital input the device firmware responds to the signal
level on the GPIO. The rate of polling of the GPIO configured as a digital input is defined within the firmware which
if implemented, would typically result in polling intervals of 20 ms. The digital input with an interrupt is used in the
same way, but as an interrupt the response time to a signal change is typically 3 ms. The interrupt method is
completely configurable as one of the four following formats: low level or high level causes the interrupt, or rising or
falling edge causes the interrupt. As a digital output, the level can be fixed during device initialization/calibration or
can be varied by the device firmware (i.e. as a rate select output to a limit amp responding to the module rate select
input). Finally, each GPIO can be the output of one of the internal DACs. The DAC mapping is shown in the block
diagram and similar to a digital output, the level can be fixed during device initialization/calibration or can be varied
by the device firmware changing the DAC setting in response to a defined event.
3.3.15 Automatic Power Control
The M02172 incorporates unique and innovative options for controlling the transmitted laser power. Control
mechanisms are provided for controlling both the bias current and the modulation current. Each includes multiple
techniques which can be independently enabled or disabled. This allows maximum configurability in a wide variety
of applications and choice of laser.
3.3.15.1 Bias Current Control
The M02172 allows two methods of controlling the laser bias current: closed loop digital control and open loop
control. Each mode is enabled by selections made within the device register settings.
Control of the bias current is illustrated in Figure 3-3. TxPwrMon is an internally mirrored replica of the current
flowing into IPIN. The updated TxPwrMon value is written to the TX_POW_MON registers. All modes start with
setting the target output power by writing to the APC_SET registers.
Functional Description
02172-DSH-001-E Mindspeed Technologies®25
Mindspeed Proprietary and Confidential
3.3.15.1.1 Closed loop Digital Control
M02172 includes circuitry to automatically maintain laser average output power with use of a monitor photodiode.
Figure 3-3 shows various photo diode connection and PD polarity swap configuration examples.
Closed loop digital control is configured by setting EN_APC_CTL high. In closed loop digital control mode the
APC_SET registers are the uncalibrated reference level for the average optical power. Closed loop digital control
varies the bias current (using the APC_SET_DAC value) to maintain the measured TX_POW_MON equal to the
value stored in the TX_POW_MON_CAL registers during module calibration.
Closed loop digital control is a state machine that utilizes the laser monitor photodiode and requires the desired
average value of the output optical power to be stored in the TX_POW_MON_CAL registers. An internal current
mirror mirrors the monitor photodiode current at IPIN and is labelled TxPwrMON. The most recent value of
TxPwrMon is stored in the TX_POW_MON register. The M02172 utilizes a precision integrator (low pass filter) on
TX_POW_MON. The output of the integrator is compared to the desired average value of optical power in the
TX_POW_MON_CAL registers and the resulting 12 bits adjusts the bias current up or down accordingly through
the APC_SET_DAC registers.
Figure 3-2. Bias Current Control
TX_POW_MON
APC_SET
> APC_GAIN < FDB_REG_APC
APC_SET_DAC
+
0
1
1
0
+ +
EN_APC_CTL
DIS_TPM_2_CAL
-
+-
+
APC_CLIP
APC CONTROL
++
APC_CLIP
(0,MAX_POS)
>> 8
FDB_REG_APC_CLEAR
DIS_AUTO_FREEZE_APC
FDB_REG_APC_FREEZE
Laser_Status
TX_POW_MON_CAL
Digital Loop
Functional Description
02172-DSH-001-E Mindspeed Technologies®26
Mindspeed Proprietary and Confidential
3.3.15.1.2 Open loop Control
With open loop control there is no feedback from the laser output to the bias control. A value is simply written that
corresponds to the desired value of the output bias current. The bias current maintains this output level regardless
of laser performance unless a fault condition occurs whereby the safety loop disables the bias current output.
Open loop control of the bias current is achieved by setting EN_APC_CTL low and writing the desired value of the
APC_SET DAC input to the APC_SET register.
Even though the bias current is operating open loop, it is possible to implement temperature compensation under
firmware control by using either a look-up table or a polynomial to modify the value with temperature.
Figure 3-3. PD polarity swap configuration examples
PD_polarity_swap = 0:
PD_polarity_swap = 1:
IB
OUT_CC
IPIN
Vcc
Monitor photodiode
sources current into IPIN
IB
OUT_CA
IPIN Vcc
Monitor photodiode
sinks current from IPIN
IB
OUT_CA
IPIN
Vcc
Monitor photodiode
sources current into IPIN
IB
OUT_CC
IPIN
Monitor photodiode
sinks current from IPIN
Functional Description
02172-DSH-001-E Mindspeed Technologies®27
Mindspeed Proprietary and Confidential
3.3.16 Modulation Current Control
Control of the modulation current is open loop with programmable compensation for changes in the bias current
and for changes in the temperature. This is illustrated in Figure 3-4.
The target modulation current is set by writing to the MOD_SET register.
3.3.16.1 BIAS-Adjusted Compensation of Modulation Current
This form of compensation is configured by setting EN_BIAS_COMP high and EN_TEMP_COMP low. The
BIAS_MON ADC is periodically sampled. The new MOD_SET_DAC value is computed based on a ratio set in the
BA_COMP_GAIN register.
The register BA_COMP_GAIN is equivalent to “percent bias current slope” factor adjustment on the modulation
current. If BIAS_MON (the present bias monitor output) is larger than the BIAS_MON_CAL value (established
during module calibration) the modulation current is increased proportionally to their differences (times the
programmable constant BA_COMP_GAIN). If the BIAS_MON is smaller than BIAS_MON_CAL then the
modulation current is decreased. In this sense, compensation using bias is different from compensation using
Figure 3-4. Modulation Current Control
Functional Description
02172-DSH-001-E Mindspeed Technologies®28
Mindspeed Proprietary and Confidential
temperature since BIAS_MON_CAL is a reference current and all modulation current adjustments are made based
on any change from this current rather than only by temperature alone.
3.3.16.2 Temperature Compensation of Modulation Current
This form of compensation is configured by setting EN_TEMP_COMP high (default). When enabled, temperature
compensation takes precedence over bias-adjusted compensation. The temperature reading can come either from
the internal temperature ADC or an external temperature sensor connected to the auxiliary A/DAUX2 input, and is
selectable by the TEMP_SEL register.
The temperature threshold at which temperature compensation is to start is written into TEMP_START. The first
order temperature compensation coefficient TEMP_COEF1 is programmable between -12 to +11. The difference
between TEMP_START and the current temperature is multiplied by 2^(TEMP_COEF1). The product is then added
to the input MOD_SET and the MOD_SET_DAC value is the result.
The TEMP_START value is in terms of the 12 bit temperature value out of the temperature monitor whether it is
based on the internal or an external sensor. The register Temp_Coef1 is the gain applied to the difference between
xxx_TEMP_MON (internal or external) and Temp_Start. The result is the modulation current compensation.
Second order temperature compensation is provided by the internal device controller through the register
uP_TEMP_COEF by enabling uP_TEMP_EN. If uP_TEMP_EN is high then temperature compensation will come
from the firmware through uP_TEMP_COEF. Through the use of firmware compensation, both look-up tables and
higher order compensation are possible and can be used to compensate for modulation current versus
temperature.
3.3.17 Current Monitors
Internal monitors are provided for transmit power (TxPwrMON), bias (BIASMON) and modulation current (MODMON).
These are reported through the TxPwrMON, BIASMON and MODMON A/D registers.
3.3.18 Laser Eye Safety
Using this laser driver in the manner described herein does not ensure that the resulting laser transmitter complies
with established standards such as IEC 825. Users must take the necessary precautions to ensure that eye safety
and other applicable standards are met. Note that determining and implementing the level of fault tolerance
required by the applications that this part is going into is the responsibility of the transmitter designer and
manufacturer since the application of this device cannot be controlled by Mindspeed.
Functional Description
02172-DSH-001-E Mindspeed Technologies®29
Mindspeed Proprietary and Confidential
3.3.19 Safety Circuitry
Comparators at VCCLD, IBOUTCA, IBOUTCC, IPIN and OUTP will assert the TX_Fault output (and will set the
appropriate bit in the Diagnostics 2 area of the DDMI memory map Table 4 - 1) indicating that a fault condition has
occurred. This condition is latched and requires SOFT_DIS or TX_DIS to be toggled or device should be power
cycled before device reset occurs. SVCC is opened during a fault or disable condition.
By setting either TX_DIS high or SOFT_DIS high, the bias and modulation output currents are disabled. TX_DIS
will disable laser bias and modulation current if left floating. TX_DIS must be forced to a low state to enable the
outputs.
Safety Circuitry in the M02172 will disable the modulation and bias current and assert the TX_Fault output
immediately upon detecting a fault condition. In addition, the supply voltage that sources the laser current (SVCC)
will immediately go open circuit and prevent any current from passing through the laser.
Fault conditions checked by the M02172 include shorts to ground or VCC of all pins which can increase the laser
power directly or indirectly (i.e. control circuitry).
For an initialization or power-up sequence to be successful, all the fault detection monitors must signal that the
device is “healthy”, unless bypassed (see Section 3.3.19.1).
When TX_DIS goes low, pins are checked for shorts to ground or VCC and a TX_Fault condition is latched if there
is a fault.
If the state of the pins is OK, a one-shot at the reset pin begins a countdown which will latch a TX_Fault condition if
the bias current has not stabilized to an acceptable level during the one-shot time.
The one-shot width is approximately 3 ms.
Figure 3-5. M02172 Safety Logic (Safety Circuit Bypass Function not Shown)
For information on bypassing the safety logic, see Section 3.3.19.1, “Safety Circuitry Bypass,” on page 30.
TX_DIS
Soft _ DIS
Fault _OK
3.3V_OK
Q
Q
SET
CL R
S
R
~900
μ
S typical TX_Fault
Output _Enable
Fault_OK
* Fault_OK indicates that no fault is
detected at any of the fault sense nodes
~3 mS typical
Functional Description
02172-DSH-001-E Mindspeed Technologies®30
Mindspeed Proprietary and Confidential
3.3.19.1 Safety Circuitry Bypass
The M02172 provides the module vendor the ability to change the behavior of the safety logic. As described above,
and shown in Figure 3-5, the default operation is that when a fault is detected, the TX_Fault output is asserted and
latched and the laser modulation current is disabled.
There are two registers: Laser Driver Control Register 0 and Laser Driver Control Register 1 that allow the module
vendor to determine how the M02172 responds to a fault condition. The soft_scb bit of LD Control Register 0
allows the safety circuitry bypass to be enabled.
When safety circuitry bypass is enabled, a fault condition no longer immediately disables the laser modulation
current but will assert the TX_Fault output (and set the appropriate bit in the Diagnostics 2 area of the DDMI
memory map Ta b l e 4 - 2 ) indicating that a fault condition has occurred. This condition is latched and can be cleared
by toggling either SOFT_DIS or TX_DIS or power cycling the device. However, the result is that laser modulation is
interrupted. An alternative method to reset the TX_Fault latch is available when bypass is enabled, the reset_fail bit
of LD Control Register 1 will reset the TX_Fault latch and not interrupt the laser output.
Additionally, there is the provision to disable the latching of the TX_Fault output completely. This is accomplished
using Latch_override bit in LD Control Register 1. When enabled, it disables the latching of the TX_Fault output
meaning that the TX_Fault output will only remain asserted as long as a fault condition persists. If the fault
condition is transient, the TX_Fault output will de-assert when the transient condition causing the fault passes.
3.3.19.2 Fault Conditions
This section describes the M02172 operating modes during fault conditions. Over voltage, under voltage, pins
shorted to VCC and pins shorted to ground are included in the fault Table 3-2.
Table 3-2. Circuit Response to Single-Point Fault Conditions
Pin Number Pin Name Circuit Response to Over-voltage Condition
or Short to Vcc
Circuit Response to Under-Voltage Condition
or Short to Ground
1-4 NVRAM1,
NVRAM2,
MOD-DEF(1)
MOD-DEF(2)
Does not affect laser power. Does not affect laser power.
5V
CC Outputs are disabled if VCC exceeds the supply
detection (high level) threshold.
Outputs are disabled if VCC voltage is below the
supply detection (low level) threshold.
6 Pwdn/Rst Module stays in power down mode Does not affect laser power.
7, 8 DIN+, DIN- The APC loop will attempt to compensate for the
change in output power. If the APC loop can not
maintain the set average power, a fault state
occurs.(1, 2)
The APC loop will attempt to compensate for the
change in output power. If the APC loop can not
maintain the set average power, a fault state
occurs.(1, 2)
9 SPI_sel Does not affect laser power. Does not affect laser power.
10 VccLD Laser bias current will be shut off, then a fault state
occurs.(1)
A fault state occurs.(1)
11 TX_FAULT Does not affect laser power. Does not affect laser power.
12 TX_DIS Bias and modulation outputs are disabled and SVcc
is opened.
Does not affect laser power (normal condition for
circuit operation).
13 GND A fault state occurs.(1) Normal operation.
14 IPIN A fault state occurs. (1, 3) A fault state occurs. (1, 3)
15 IBOUTCA No safety circuitry on this output No safety circuitry on this output
Functional Description
02172-DSH-001-E Mindspeed Technologies®31
Mindspeed Proprietary and Confidential
16 GNDO A fault state occurs.(1) Normal operation.
17 Vsense Does not affect device operation.(4) Does not affect device operation.(4)
18 OUTP Does not affect laser power during common cathode
operation. During common anode operation, laser
modulation is prevented; the APC loop will increase
bias current to compensate for the drop in laser
power. If the set output power can not be obtained, a
fault state occurs.(1,2)
A fault state occurs.(1)
19 OUTN Does not affect laser power during common anode
operation; does not affect laser power during
common cathode operation since output is AC
coupled.
Does not affect laser power during common anode
operation; does not affect laser power during
common cathode operation since output is AC
coupled.
20 GPIO(4) Does not affect laser power. Does not affect laser power.
21 SVCC/IBOUTCC Does not affect laser power if output is configured for
common anode. If output is configured for common
cathode operation, a fault state occurs.(1)
In either common anode or common cathode
configuration, the laser is turned off and a fault state
occurs.(1)
22 A/DAUX2 Does not affect laser power. Does not affect laser power.
23 BIAS_R Turns off internal reference current for laser driver
bias and modulation; no laser output.
A fault state occurs.(1)
24 A/DAUX1 Does not affect laser power. Does not affect laser power.
25 A/DRxP Does not affect laser power. Does not affect laser power.
26 TEST Laser Driver is Disabled Does not affect laser power.
27-31 RxLOS,
GPIO(0-3)
Does not affect laser power. Does not affect laser power.
32 DVDD A fault state occurs. (1) Disables laser driver.
NOTES:
1. Unless the safety circuitry is bypassed, a Fault state will assert the TX_Fault output, disable bias and modulation outputs and open the switch at
SVCC.
2. Does not affect laser power when the modulation output is AC coupled to the laser.
3. Does not affect laser power in open loop mode.
4. While the device operation is not affected by voltage applied at pin 17, any external circuitry connected to this pin must also be considered.
Table 3-2. Circuit Response to Single-Point Fault Conditions
Pin Number Pin Name Circuit Response to Over-voltage Condition
or Short to Vcc
Circuit Response to Under-Voltage Condition
or Short to Ground
02172-DSH-001-E Mindspeed Technologies®32
Mindspeed Proprietary and Confidential
4.0 Applications Information
4.1 Applications
• 300 Pin, X2, XFP and SFP/SFP+ Optical Transceivers
• SONET/SDH Transceivers
• 1/10 Gigabit Ethernet Modules
• 1G/2G/4/8/10G Fibre Channel Modules
4.2 Configuring the M02172 for Typical Applications
Because of its versatile architecture, the M02172 is easily adapted for a variety of applications. Several typical
combinations are presented here, but there is much flexibility for module vendors to create their own variations.
The pulse width adjustment (PWA) DAC, as well as a 10-bit auxiliary DAC and the two 6-bit auxiliary DACs are
each connected to one of the four GPIOs to enable their use for external purposes. The received average power
(RxP) ADC and the two auxiliary ADCs are external inputs.
Figure 4-1. M02172 Placement in SFP+ Module
Atmel
AT24C128
or
Equivalent
(on back)
SCL
SDA
Top-side module
connections
Bottom-side module
connections
Tx
Rx
V
EE
T
V
EE
R
V
EE
T
V
EE
R
V
CC
R
V
CC
T
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
Tx_Fault
VEET
Tx_Disable
SDA
SCL
MOD-ABS
RS0
Rx_LOS
RS1
VEER
TOSA
ROSA with
M02XXX TIA
TD-
TD+
RD+
RD-
M0214X
M02172
Applications Information
02172-DSH-001-E Mindspeed Technologies®33
Mindspeed Proprietary and Confidential
Application: M02172 with Externally Modulated Laser
The primary applications for this configuration are OC-192 SONET, 10GFC Fibre Channel, and 10Gigabit Ethernet
long-reach (> 80km) transceivers in either 300Pin, X2, XFP and SFP+ form factors. Figure 4-2.
Figure 4-2. M02172 with EML Laser
TIALimit Amp
M02172
ST
SET
(Internal Pulse Width
Adjust )
Mon
I
PIN
RSSI
PP
RxLOS
OUT
A/D
AUX1
A/D
RxP
GPIO
(DAC)
Data In
Data Out
LOS
EML
PD
Temp
Sensor
TEC
APD
Detector
Boost
Converter
IB
OUT
A/D
AUX2
APD bias control
GPIO
(DAC)
GPIO
(DAC)
(Optional Temp Sensor)
Rate_sel /GPIO
Applications Information
02172-DSH-001-E Mindspeed Technologies®34
Mindspeed Proprietary and Confidential
Output Schematic with Cyoptics 10T3082-3 EML TOSA
Below is show the output schematic for the actual SFP+ implemented reference design on an SFP+ form factor
PCB using the Cyoptics 10T3082-3 TOSA. Other reference designs are available. Please contact your local sales
representative for information.
Figure 4-3. M02172 with Cyotpics 10T3082-3 EML
Applications Information
02172-DSH-001-E Mindspeed Technologies®35
Mindspeed Proprietary and Confidential
4.3 Device Monitors Calibration
This section describes how the device, using Mindspeed supplied firmware, supports the device monitors
calibration requirements of SFF-8472. The standard uses the term calibration to refer to the conversion of the raw
monitor ADC values to actual temperature, voltage, power, etc. values. This should not be confused with the
module calibration (and configuration) features.
4.3.1 Internal and External Calibration of Monitored Parameters
As specified in SFF8472, the monitored parameters can be calibrated either externally or internally. With internal
calibration the measurements are calibrated over the operating temperature and voltage and are interpreted in real
world units versus raw A/D values. External calibration stores raw A/D values which must be converted to real
world units by the host using calibration constants given in Table 3-16 of SFF-8472, Rev 10.3.
4.3.2 Additional or Reserved Monitors
The M02172 incudes two auxiliary ADCs for monitoring purposes in addition to the modulation current monitor.
Provisions exist in SFF-8472 for two more internally calibrated monitor values with associated alarm and warning
levels. However, note that an insufficient number of bytes have been reserved by SFF-8472 to support external
calibration for these additional monitored values. Therefore the additional Aux_ADC monitors and/or the
modulation current monitor can only be mapped to the reserved locations for internally calibrated monitors and
warning levels. If these monitors are not mapped to the reserved locations, the values and alarm/warning levels are
still stored in PDRAM.
4.3.3 Real Time Module Diagnostic Miscellaneous Status Bits
The device firmware also monitors the status of the module and updates the miscellaneous status bits stored in
(A2h, 110). The status bits include:
• Tx Disable
• Soft Tx Disable
• Rx Rate Select
• Soft Rx Select
• Tx Fault
• Rx LOS
• Data_Ready_Bar
4.4 Two-wire Host Memory Access Model
All on-chip memories can be accessed via the host two-wire interface using serial device addresses A0h and A2h.
The on-chip memory is partitioned into 128 byte tables accessed using 8-bit addresses and a programmable table
select byte where the memory partition is configurable to comply with the SFP/SFP+/DDMI standards. The table
select byte defaults upon power up to 00h. The table select byte is used as the MSB address bits and if the host
attempts to write an invalid table select byte, nothing will be written and if an attempt is made to read using an
invalid table select byte, the return value will be zero. The host interface memory map is defined in Tabl e 4- 1 .
Note that the information at both two-wire addresses (A0h and A2h) may be accessed by using the appropriate
address without the need for a special address change sequence. This means that accessing information at either
address can be accomplished by the host at any time.
Applications Information
02172-DSH-001-E Mindspeed Technologies®36
Mindspeed Proprietary and Confidential
Figure 4-4 describes the device memory map to the EEPROM, internal device controller and the host two-wire
serial interface.
Section 4.4.3, “Host Two-wire Serial Interface Block (see Table 1-12 and Table 1-14 for specifications),” on page 37
describes the DDMI and SFP/SFP+ memory maps in more detail.
.
4.4.1 NVRAM Controller Initial Data Download
(see Table 1-12 and Table 1-14 for specifications)
The NVRAM Controller block is used to download all the 16 k external RAM from the NVRAM to the internal device
registers and memories after power on reset.
During NVRAM download, the M02172 internal uC8051 is disabled while the NVRAM Controller is the master
driving the 2-wire EEPROM (NVRAM1 and NVRAM2) bus. The NVRAM Controller first downloads the 256 byte
device register data along with the SFP, DDMI and the program and data RAM (PDRAM) checksums (see the
“EEPROM download order” column in Figure 4-4). The NVRAM Controller then downloads the 256 byte SFP data
image. The SFP checksum is recomputed and compared with the downloaded checksum. (The checksum is
defined as the modulo 256 sum of the SFP data.) If the two checksums are not equal, the SFP Checksum Error
register bit is set. The M02172 SFP checksum data is held in the Device Registers section of its registers.
The download of the DDMI data is slightly different. The controller reads both data images DDMI 0 and DDMI 1.
Each checksum is recomputed and compared with the downloaded checksum from the Device Register section.
The controller also polls the DDMI status register STAT_DDMI to determine which DDMI is the most recent write
back to the EEPROM. The DDMI data image containing the most recent data (based on STAT_DDMI) with a valid
checksum is loaded into the DDMI memory. If neither checksum is correct the DDMI 0 and DDMI 1 Checksum Error
register bit is set and the 256 bytes of data are still loaded into the internal DDMI memory based on the timestamp
status bit.
Finally, the NVRAM Controller downloads the program and data image to the internal device RAM. If the checksum
comparison fails, the download will be attempted two more times. If all three attempts fail, the download will remain
in the internal RAM, the PDRAM Checksum Error register bit is set and the device will be put into host mode in
which the device uC8051 is disabled and the only way to control the device is through the host two-wire serial
Figure 4-4. Memory Mapping Table
PDRAM
(program and data
RAM)
15k bytes
0000h
3BFFh
DEVICE REGS
256 bytes
3C00h
3CFFh
SFP
256 bytes
3D00h
3DFFh
DDMI 0
256 bytes
3E00h
3EFFh
EEPROM
address map
DDMI 1
256 bytes
PDRAM
15k bytes
0000h
DEVICE REGS
256 bytes
SFP
256 bytes
DDMI
256 bytes
M02172 uC
address map
RAM
registers
RAM
RAM
3F00h
3FFFh
3BFFh
3C00h
3CFFh
3D00h
3DFFh
3E00h
3EFFh
EEPROM
download order
5
1
2
3
PDRAM
15k bytes
DEVICE REGS
256 bytes
SFP
256 bytes
DDMI
256 bytes
Two-Wire
address map
(A2h)
(A2h)
(A0h)
(A0h)
(A2h)
(A2h)
(A2h)
(A2h)
USER/VENDOR
256 bytes
3B00h
3AFFh
USER/VENDOR
256 bytes
3B00h
3AFFh
RAM4USER/VENDOR
256 bytes
(A2h)
(A2h)
DDMI 0 or 1 with
most recent time
stamp 256 bytes
Applications Information
02172-DSH-001-E Mindspeed Technologies®37
Mindspeed Proprietary and Confidential
interface. The download can also be initiated by a signal from uC watchdog timers and from the NVRAM Controller
control register (02, 80h).
4.4.2 Uploading the Device Registers and Internal Memories (SFP, DDMI, 15
kbyte PDRAM) to the External EEPROM
The NVRAM Controller is allowed to write back device registers and internal memories to the external EEPROM. It
can be initiated by either the device uC8051 or through the host two-wire serial interface. This is accomplished by
writing to the NVRAM Controller control register.
The uC8051 and the host can be enabled to initiate a W/R backup of the SFP data, the DDMI data, and the device
registers. Only the host is allowed to initiate a backup of the 15 k PDRAM, user memory and vendor memory.
During the backup of the SFP data, the DDMI data, and the device registers, the finite state machine controller will
send an interrupt to the uC8051 forcing the microcontroller into a wait state. To accomplish this, the uC memory
bus has to communicate with the 15 k PDRAM memory program code. During this time, the uC and the host are
able to read the device register section. At the end of the backup, the interrupt is released, bringing the uC out of
the wait state. During the write back operation, new checksums of the SFP data, the DDMI data and the 15 k
PDRAM have to be computed either by the device firmware or by the host controller.
A special case exists for updating the DDMI memory with calibration information. When either the device uC or
host sends a command to write back the DDMI data, the NVRAM Controller toggles the STAT_DDMI status bit and
writes the DDMI data into the corresponding image in the external EEPROM. The timestamp and checksum are
also written to the appropriate locations in the EEPROM. During the backup time to the EEPROM, the host will
have read only access (with the appropriate password) of the DDMI and SFP dual-port memories. At the end of the
backup mode, the interrupt is released, bringing the uC out of the wait state and the clear on read status bit
eeprom_access_done will be asserted when the EEPROM access is complete.
Whenever the host or device initiates a write back of the DDMI memory data to the external EEPROM, a dummy
read should follow the write operation to force the device to increment the DDMI memory location in the EEPROM
(DDMI 0 or 1) that it will next write back to. (The Mindspeed supplied firmware performs this function whenever it
writes to the EEPROM DDMI memory).
4.4.3 Host Two-wire Serial Interface Block (see Table 1-12 and Table 1-14 for
specifications)
• Slave operation only
• Supports 7-bit addressing on the two-wire serial bus
• Supports Standard and Fast Mode transfer rates
• During write back to the 15 k program and data RAM (PDRAM), user memory and vendor memory, the
NVRAM Controller will send a signal to disable the host acknowledge signal
• Reprogramming the Serial (Slave) device address is described in Section 4.7
The host accesses internal memories using serial device addresses A0h and A2h. Since the host has an 8 bit
address interface, to access to all 16 k memory locations, the memory is partitioned into 128-byte tables. A table
select byte (TSB) is used to provide indirect addressing to each table. The TSB must proceed each read or write
access except when a consecutive read or write occurs within the same table already accessed.
The host interface memory map is defined in Tabl e 4 -1.
Applications Information
02172-DSH-001-E Mindspeed Technologies®38
Mindspeed Proprietary and Confidential
For serial device address A2h, the lower data addresses always reference the same information regardless of the
actual Table Select Byte value (i.e., the diagnostic information is always accessible). The default table for serial
device address A2h (or whatever it may be reprogrammed to be) is 00h (i.e. the DDMI specified data fields).
The memory is further partitioned into functional groups, each of which has configurable access permissions and
password protection. There are four programmable password configurations. This flexible access methodology
allows the module manufacturer to customize access models for a variety of purposes or intended users.
Table 4-1. SFP/DDMI Memory Map
Serial Device
Address Table Data Address
(decimal) SFF-8472 Description M02172 Description
A0h
(SFP)
00h Lower
0-95 Serial ID Serial ID
96-127 Vendor Specific Vendor Specific
00h Upper 128-255 Reserved SFF-8079 Reserved SFF-8079
A2h
(DDMI)
00h Lower
0-55 Alarm and Warning Thresholds
Diagnostics 1
56-95 Calibration Constants
96-119 Real Time Diagnostic Interface Diagnostics 2
120-122
Vendor Specific
Firmware Revision
123-126 Password Entry
127 Table Select Byte
00h Upper 128-247 User Writable Memory User Memory
248-255 Vendor Specific Vendor Specific
A2h
(DDMI)
01h Upper 128-255 N/A User Memory
02h Upper 128-255 N/A Vendor Memory
03h - 04h Upper 128-255 N/A Device Registers
05h - 7Ah Upper 128-255 N/A Program and Data Memory
Applications Information
02172-DSH-001-E Mindspeed Technologies®39
Mindspeed Proprietary and Confidential
Each memory partition is assigned a bit in the read and write access permission registers for each password level.
4.5 Password Protection
Passwords are entered by writing to the password entry bytes (see address A2h 123-126d in Ta bl e 4 - 1 ). These
along with the table select byte are accessible without a password. The on-chip memory is protected from
unauthorized access from the host interface by four levels (lowest to highest, 0 - 3) of 32-bit passwords.
The access restrictions for each password level is configurable to allow read or write access to different blocks of
memory. The memory is partitioned into nine sections as listed in Ta bl e 4 -3 with each level allowing unique
password access.
Table 4-2. M02172 DDMI Memory Partitioning (default serial device address A2h)
Data Address
(decimal)
Table Select Byte (TSB)
00 01 02 03-04 05-7Ah
00
95
Diag 1
DDMI
Diagnostics
All lower 128 bytes with table select byte > 0 map to the lower 128 bytes at TSB 00
96
119
Diag 2
120
127
Vendor Specified
(used by Mindspeed)
128
247
Reserved
User
Memory
Vendor
Memory
Device
Registers
...Program/Data...
(PDRAM)
248
255
Vendor Specified
Applications Information
02172-DSH-001-E Mindspeed Technologies®40
Mindspeed Proprietary and Confidential
For each access level, there are internal configuration registers for read access and for write access. The control of
access to the on-chip memory is illustrated in Figure 4-5. To access the memory, the host must write a 32-bit
password to the appropriate DDMI memory location (see address A2h 123-126d in Ta bl e 4 - 1 ). The entered
password is compared to the four passwords (one for each access level) stored internally. The current access level
is defined as that corresponding to the matching password. If the entered password matches none of the stored
passwords, access defaults to the lowest level (level 0 is the lowest level, level 3 is the highest level).
The access configuration registers for the current access level defines whether access is enabled to a given
memory partition. When the host attempts to access the on-chip memory, the data address is first mapped to a
memory partition number. The corresponding bit of the access configuration registers for the current access level
are then checked to determine if access should be enabled for this partition. If access is enabled, the memory
interface is then allowed to perform the requested access. An example of access definition, using the Mindspeed
supplied software the vendor could configure the level 0 access for read-only for Diagnostics 1 and Diagnostics 2
while all memory is write protected.
Note that the vendor is given complete password control with the Mindspeed supplied M02172 configuration
software. Using the supplied software, the vendor defines the password for each access level and the level of
access for the nine SFP/DDMI Memory Password Protection Partitions shown in Ta bl e 4 - 3 .
Table 4-3. The Nine SFP/DDMI Memory Password Protection Partitions
Memory Section
Data Address
Allowable Password
Control Level
Serial Device
Address Table Address
(decimal)
Diagnostics 1 A2 00h Lower 0-95
0-3
Diagnostics 2 A2 00h Lower 96-119
Serial ID A0 00h Lower 0-95
User
A2 00h Upper 128-247
A2 01h Upper 128-255
Vendor
A0 00h Lower 96-127
A2 00h Lower 120-122
A2 00h Upper 248-255
A2 02h Upper 128-255
Reserved A0 00h Upper 128-255
Program/Data A2 ≥05h Upper 128-255
Device Registers 1 A2 03h Upper 128-255
Device Registers 2 A2 04h Upper 128-255
Applications Information
02172-DSH-001-E Mindspeed Technologies®41
Mindspeed Proprietary and Confidential
4.6 Two-Wire Serial Interface
4.6.1 SFP/SFP+ Compliant interface
• SFP/SFP+SFP/SFP+ data read accessible via two-wire serial interface with serial device address A0h
(reprogrammable).
• SFP/SFP+ data writable via two-wire serial interface with multiple levels of password protection.
• SFP/SFP+ data downloaded from external EEPROM to on-chip RAM after module powers up.
• M02172 internal device controller does not alter SFP/SFP+ data.
• 15Mhz maximum clock rate.
• If the host alters the SFP/SFP+ data, it must supply a checksum at address 3Fh (automatic backup to external
EEPROM initiated without interruption access from the host).
4.6.2 DDMI Compliant interface
• Fully SFF-8472 compliant.
• DDMI data read accessible via two-wire interface with serial device address A2h (reprogrammable).
• DDMI data writable via two-wire serial interface with multiple levels of password protection.
• DDMI data downloaded from external EEPROM to on-chip RAM after module powers up.
• 400Khz maximum clock rate.
• If the host alters the DDMI data, it must supply a checksum at address 3Fh and 5Fh (automatic backup to
external EEPROM initiated without interruption access from the host).
Figure 4-5. Password Access Control Architecture
Two-wire Data
Two-wire Data
Address
Password
Map to
Partition
Number
Password
Compare
Logic
Memory
Access
Enable
Logic
Access
Configuration
Registers
Memory
Interface
Two-wire R/W
Access Enable Signal
Partition
Number
Valid
Password
Number
M02172
Memory
Password
Registers
Applications Information
02172-DSH-001-E Mindspeed Technologies®42
Mindspeed Proprietary and Confidential
4.6.3 HOST Interface Details
In accordance with SFP/SFP+ MSA and SFF-8472, the M02172 incorporates a two-wire interface that uses the
serial EEPROM protocol defined for the Atmel AT24C01A/02/04 family of products. The interface consists of a
serial input clock line (SCL, Mod Def 1) and a serial, bi-directional data line (SDA, Mod Def 2). SCL and SDA are
each pulled up with an external resistor.
During data transmission, SDA can only transition while SCL is low. Changes on SDA when SCL is high indicates a
start or stop condition which initiates or terminates the transmission. A start condition occurs when SDA transitions
from high to low when SCL is high. Conversely, a low to high transition on SDA when SCL is high indicates a stop
condition. The start condition is followed by the device address (A0h for SFP/SFP+ and A2h for DDMI). The data
address is transmitted following the device address which is followed by transmission of the data. The M02172
responds to each byte of data with an acknowledgement which is a zero following the received byte. The device
can receive data a byte at a time or in sixteen byte sequences (page mode). The transmission is then terminated
with the stop condition.
4.6.4 Four-wire SPI Interface Details
For those applications requiring faster programming and read back than an I2C interface can provide, an SPI
interface is also provided. When SPI_Sel is high, the 4-wire SPI interface is selected. If SPI_Sel =0, the device
returns to the existing 2-wire Interface (MOD_DEF1 and MOD_DEF2) with GPIO[1] and SS inputs ignored.
After the transition high-to-low of SS, the SPI Master will transfer a1 byte instruction (one of 4 instructions at table
1) following by a 1-byte address and 1-byte data for write mode and so forth. SI is sampled by the rising edge of
SCK and SO is clocked out by falling edge of SCK. For an SPI Master, SO is sampled by the rising edge of SCK
and SI is clocked out by the falling edge of SCK.
Table 4-4. Two-Wire Interface
Pin Function Description
MD1/SCL Mod-Def 1/Serial Clock Clock input (open drain)
MD2/SDA Mod-Def 2/Serial Data Data input/output (open drain)
Table 4-5. Four-Wire Serial Interface Description
Pin Function Description
SS Slave Select Active Low. Allowing SS to return high, changes communication backhoe I2C
SCK Serial Clock 10MHz maximum
SI Slave Input MOD_DEF2 (Data input)
SO Slave Output MOD_DEF1 (Data output)
Table 4-6. SPI Instructions
Instruction Name Instruction Format SS at end of current read/write operation Operation
R-Read PDDDDx11 H Random Read
R-Write xxxxxx10 H Random Write
S-Read PDDDDx11 L Sequential Read
S-Write xxxxxx10 L Sequential Write
Applications Information
02172-DSH-001-E Mindspeed Technologies®43
Mindspeed Proprietary and Confidential
As a result, the read command changes to: “PDDDD_X11; the Random/Sequence Read command. Where the P
bit refers to whether or not the programmable delay mode is turned on or off. The DDDD bits represent the number
of cycles by which the read is delayed. For reliable operation, it is recommended that 3 to 8 SPI clock cycles be
programmed. (With a 10 MHZ SPI clock). The X’s are don't cares. When P=1, the programmable delay is turned
on, and the read value is delayed by the number represented by DDDD bits. For example: If DDDD = 0100, then
the read value is output after a 4 cycle delay. DDDD = 1000 means that the read value is output after an 8 cycle
delay. When P = 0, the programmable mode is turned off, and the read value is output after a default 8 cycles delay.
SPI Timing Application Notes:
• If the two LSB of the instruction byte are not 11 or 10, no read/write cycle is executed and the SO pin remains
tri-stated.
• There are no different instructions for Random R/W and sequential R/W. When slave select, SS is extended by
n*8-spi clock cycles, and a Random R/W becomes a sequential R/W as in the sequential write timing diagram.
• The sequential R/W continues to roll over the 256 byte addresses if SS is extended low.
• A minimum of one SPI clock cycle pulse width is required for Slave Select (SS) to be deselected between
Read-Read, Read-Write, Write-Read, or Write-Write modes.
• At least one SPI clock cycle is required after Slave select SS is deasserted.
• As in the two wire slave interface, the SPI interface reserves HOST address 7Fh for table select. Each 128-byte
table definition remains as before (at two wire slave address A2h). For example, writing 03h to table select
address $7F, selects table #3, following by a R/W to any address from $80 to $FF, giving access to Host
locations $80 to $FF.
• SPI Host Read/Writes to any lower addresses ($00 to $7E and $7F) are mapped to the 128 byte common area
of Diagnostics 1, Diagnostics 2, Vendor specific, Password Entry and Table Select defined in the lower page.
• To access the 256-byte SFP (former two wire slave) address A0h(from two wire interface mode), writing 80h
(for the lower 128 bytes) and 81h (for the upper 128 bytes) to table select is required. After writing 80h or 81h
to table select, SPI host addresses ($80 to $FF) are mapped to the lower 128 bytes or upper 128 bytes of SFP
memory.
• Note: it is up to the user to terminate the extension of SS in sequential write and change the table select since
it can be rolled over 256 bytes address which can roll to lower addresses and data are written to the common
area. For example, start writing at address $C0 in sequential Write: $C0, #C1 …….#FF, #00, #01 ……….#7E
(table select), #7F, #80, ……. #C0, #C1 …. #FF…….
Applications Information
02172-DSH-001-E Mindspeed Technologies®44
Mindspeed Proprietary and Confidential
Figure 4-6. SPI Random Read
Figure 4-7. SPI Random Write
Trdd
TenhTens
1 2 7 8 9 10 15 16 17 20 21 27 28
8-bits addresses8-bits instruction
8-bits MISO
SCK
!SS
SI
SO
sampled SI
TdhTds
1 2 7 8 9 10 15 16 17 20 23 24
addresses_N 8bits dataW instruction
TRI-STATETRI-STATE
SCK
!SS
SI
SO (TRISTATE)
Applications Information
02172-DSH-001-E Mindspeed Technologies®45
Mindspeed Proprietary and Confidential
Figure 4-8. SPI Sequential Read
Figure 4-9. SPI Sequential Write
TddTddTdd
1 2 7 16 17 20 21 28 29 36 37 44
8-bits instruction & 8-bits addresses
first byte second byte third byte MSIO
SCK
!SS
SI
SO
SI sampled
1 2 7 8 9 10 15 16 17 24 25 32
addresses_N 8bits data_NWrite instruction
TRI- STATETRI- STATE
8bits data_N+1
8bi t s dat
a
SCK
!SS
SI
S
O (TRISTATE)
Applications Information
02172-DSH-001-E Mindspeed Technologies®46
Mindspeed Proprietary and Confidential
4.7 Reprogramming the Serial Device Address
When more than one device is sharing the two-wire interface it will be necessary to change the serial device
address of each module to allow the host independent access to each module. This is accomplished using the
Two-wire Serial Control Register that when set, redefines how the TX_DIS pin is interpreted by the M02172. In this
mode, if TX_DIS is high, the M02172 will not respond to any serial device address from the host interface. If
TX_DIS is low, the M02172 will respond when the serial device address is its own, allowing the particular device to
be accessed (TX_DIS is performing as a device select pin).
When the host sets this control bit, all modules will be placed in this reprogramming mode. Individually selecting a
module through an individual module’s TX_DIS pin allows the modules address to be uniquely programmed.
Module addresses are 8 bit words. The LSB selects a read or write operation and is not part of the address. The
second bit is defined to be a zero for SFP and a one for DDMI, thus DDMI addresses are always 2 greater than the
SFP addresses in a module (e.g. A0h and A2h the default SFP and DDMI addresses). This means that the first six
MSBs are what constitute the unique module address. The serial device address is held in the Physical Address
Control Register. Only one address is written. The reprogrammed address is now the SFP serial device address.
As detailed above, the DDMI serial device address is now an increment of 2 greater than the SFP address.
Once each module has had its address reprogrammed, to exit this reprogramming mode is accomplished by again
using the Two-wire Serial Control Register to define the TX_DIS pin to its normal function. This operation must be
performed on each module as they now each possess a unique serial device address.
02172-DSH-001-E Mindspeed Technologies®47
Mindspeed Proprietary and Confidential
5.0 Package Specification
Figure 5-1. QFN32 Package Information (Amkor)
Note: View is for a 28 pin package. All dimensions in the
tables apply for the 32 pin package
3.5
3.5
3.6
3.6
3.4
3.4
0.70
0.90
Package Specification
02172-DSH-001-E Mindspeed Technologies®48
Mindspeed Proprietary and Confidential
Figure 5-2. QFN32 Package Information (ASEM)
www.mindspeed.com
General Information:
Telephone: (949) 579-3000
Headquarters - Newport Beach
4000 MacArthur Blvd., East Tower
Newport Beach, CA 92660
© 2010 Mindspeed Technologies®, Inc. All rights reserved.
Information in this document is provided in connection with Mindspeed Technologies® ("Mindspeed®") products.
These materials are provided by Mindspeed as a service to its customers and may be used for informational
purposes only. Except as provided in Mindspeed’s Terms and Conditions of Sale for such products or in any
separate agreement related to this document, Mindspeed assumes no liability whatsoever. Mindspeed assumes
no responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications and
product descriptions at any time, without notice. Mindspeed makes no commitment to update the information and
shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its
specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document.
THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR
IMPLIED, RELATING TO SALE AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL
DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR
COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE
MATERIALS. MINDSPEED SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS,
WHICH MAY RESULT FROM THE USE OF THESE MATERIALS.
Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed
customers using or selling Mindspeed products for use in such applications do so at their own risk and agree to
fully indemnify Mindspeed for any damages resulting from such improper use or sale.
02172-DSH-001-E Mindspeed Technologies®49
Mindspeed Proprietary and Confidential