IDT71024S12TY8 - Integrated Device Technology

AUGUST 2009

DSC-2964/18

1

Features

◆◆

◆128K x 8 advanced high-speed CMOS static RAM

◆◆

◆Commercial (0°C to +70°C), Industrial (–40°C to +85°C)

◆◆

◆Equal access and cycle times

— Commercial and Industrial: 12/15/20ns

◆◆

◆Two Chip Selects plus one Output Enable pin

◆◆

◆Bidirectional inputs and outputs directly

TTL-compatible

◆◆

◆Low power consumption via chip deselect

◆◆

◆Available in 300 and 400 mil Plastic SOJ.

Functional Block Diagram

Description

The IDT71024 is a 1,048,576-bit high-speed static RAM organized as

128K x 8. It is fabricated using IDT’s high-performance, high-reliability

CMOS technology. This state-of-the-art technology, combined with inno-

vative circuit design techniques, provides a cost-effective solution for high-

speed memory needs.

The IDT71024 has an output enable pin which operates as fast

as 6ns, with address access times as fast as 12ns available. All

bidirectional inputs and outputs of the IDT71024 are TTL-compat-

ible, and operation is from a single 5V supply. Fully static asynchro-

nous circuitry is used; no clocks or refreshes are required for

operation.

The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ and 32-

pin 400 mil Plastic SOJ.

CMOS Static RAM

1 Meg (128K x 8-Bit) IDT71024S/MS

6.42

2

IDT71024 CMOS Static RAM

1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges

NOTE:

1. This parameter is guaranteed by device characterization, but is not production tested.

Truth Table(1,3)

Absolute Maximum Ratings(1)

Pin Configuration

SOJ

Top View

Recommended Operating

Temperature and Supply Voltage

R ecommended D C Operating

Conditions

NOTES:

1. H = VIH, L = VIL, X = Don't care.

2. VLC = 0.2V, VHC = VCC –0.2V.

3. Other inputs ≥VHC or ≤VLC.

Inputs

I/O Function

WE CS

1

CS

2

OE

X H X X High-Z Deselected – Standby (I

SB

)

XV

HC

(2)

X X High-Z Deselected – Standby (I

SB1

)

X X L X High-Z Deselected – Standby (I

SB

)

XXV

LC

(2)

X High-Z Deselected – Standby (I

SB1

)

H L H H High-Z Outputs Disabled

HLHLDATA

OUT

Re ad Data

LLHXDATA

IN

Write Data

2964 tb l 01

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. VTERM must not exceed VCC + 0.5V.

Symbol Rating Value Unit

VTERM

(2)

Te rmi nal Vo ltag e with Re s pe ct to GND –0.5 to +7. 0 V

TBIAS Te mp e rature Unde r Bias –55 to + 125

o

C

TSTG Sto rage Te mp erature –55 to + 125

o

C

PTPo we r Dissipatio n 1.25 W

IOUT DC Outp ut Curre nt 50 mA

2964 tbl 02

Grade Temperature GND VCC

Co mme rcial 0°C to + 70°C 0V 5.0V ± 0. 5V

Industrial –40°C to + 85°C 0V 5.0V ± 0. 5V

2964 tbl 05

NOTE:

1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.

Symbol Parameter Min. Typ. Max. Unit

V

CC

Supp ly Voltage 4.5 5.0 5.5 V

GND Ground 0 0 0 V

V

IH

Input Hig h Vo l tag e 2. 2 ____ V

CC

+0.5 V

V

IL

Input Low Vo ltag e –0.5

(1)

____ 0.8 V

2964 tb l 04

Capacitance

(TA = +25°C, f = 1.0MHz, SOJ package)

Symbol Parameter

(1)

Conditions Max. Unit

CIN Inp ut Capac i tanc e V IN = 3dV 7 pF

CI/O I/ O Cap ac i tanc e V OUT = 3dV 8 pF

2964 tbl 03

6.42

IDT71024 CMOS Static RAM

1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges

3

DC Electrical Characteristics(1)

(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V)

DC Electrical Characteristics

(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)

Symbol Parameter Test Condition

IDT71024

Unit

Min. Max.

|I

LI

| Inp ut Le ak ag e Current V

CC

= Max., V

IN

= GND to V

CC

___ 5µA

|I

LO

| Output Le akag e Curre nt V

CC

= Max., CS

1

= V

IH

, V

OUT

= GND to V

CC

___ 5µA

V

OL

Outp ut Lo w Vo ltag e I

OL

= 8mA, V

CC

= Min. ___ 0.4 V

V

OH

Output Hig h Vo ltag e I

OH

= –4mA, V

CC

= Min. 2.4 ___ V

2964 tb l 06

NOTES:

1. All values are maximum guaranteed values.

2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address

input lines are changing.

71024S12 71024S15 71024S20

Symbol Parameters Com'l. Ind. Com'l. Ind. Com'l. Ind. Unit

I

CC

Dynamic Op e rating Curre nt,

CS

2

≥ V

IH

and CS

1

≤ V

IL

, Outputs Ope n,

V

CC

= Max., f = f

MAX

(2)

160 160 155 155 140 140 mA

I

SB

Stand b y P o we r Sup p ly Curre nt (TTL Le v el)

CS

1

≥ V

IH

or CS

2

≤ V

IL

, Outputs Ope n,

V

CC

= Max., f=f

MAX

(2)

40 40 40 40 40 40 mA

I

SB1

Ful l S tand b y Po we r Sup p ly Curre nt

(CMOS Le ve l), CS

1

≥ V

HC

or

CS

2

≤ V

LC

, Outp uts Ope n,

V

CC

= Max., f = 0

(2)

, V

IN

≤ V

LC

or V

IN

≥ V

HC

10 10 10 10 10 10 mA

2964 tb l 07

Figure 1. AC Test Load Figure 2. AC Test Load

(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)

*Including jig and scope capacitance.

2964 drw 03

480Ω

255Ω30pF

DATA

OUT

5V

2964 drw 04

480Ω

255Ω5pF*

DATA

OUT

5V

Input Pulse Lev els GND to 3.0V

Input Rise/Fall Tim es 3ns

Input Tim ing Reference Levels 1.5V

Out put Ref erence Levels 1.5V

AC Test Load See Figures 1 and 2

2964 t bl 08

AC Test Conditions

6.42

4

IDT71024 CMOS Static RAM

1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)

71024S12 71024S15 71024S20

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

Read Cycle

t

RC

Re ad Cyc le Time 12 — 15 — 20 — ns

t

AA

Address Access Time — 12 — 15 — 20 ns

t

ACS

Chip Select Access Time — 12 — 15 — 20 ns

t

CLZ

(1)

Chip S e l e c t to Outp u t i n Lo w-Z 3 — 3 — 3 — ns

t

CHZ

(1)

Chi p De s e le c t to Outp ut in Hig h-Z 0 6 0 7 0 8 ns

t

OE

Output E nab l e to O utput Val id — 6 — 7 — 8 ns

t

OLZ

(1)

Output E nab l e to Outp ut i n Low- Z 0 — 0 — 0 — ns

t

OHZ

(1)

Output Disable to Output in High-Z 0 5 0 5 0 7 ns

t

OH

Output Hold from Address Change 4 — 4 — 4 — ns

t

PU

(1)

Chip Se lect to Powe r-Up Time 0 — 0 — 0 — ns

t

PD

(1)

Chi p De s e le c t to Po we r-Do wn Tim e — 12 — 15 — 20 ns

Wr it e C y c l e

t

WC

Write Cycle Time 12 — 15 — 20 — ns

t

AW

Address Valid to End-of-Write 10 — 12 — 15 — ns

t

CW

Chip Se le ct to End-o f-Write 10 — 12 — 15 — ns

t

AS

Add ress Set-Up Time 0 — 0 — 0 — ns

t

WP

Write Pulse Wid th 8 — 12 — 15 — ns

t

WR

Write Reco very Time 0 — 0 — 0 — ns

t

DW

Data Val id to End -o f-Write 7 — 8 — 9 — ns

t

DH

Data Ho l d Ti me 0 — 0 — 0 — ns

t

OW

(1)

Ou tp ut A c ti ve from E nd -o f-Wri te 3 — 3 — 4 — ns

t

WHZ

(1)

Write Enable to Output in High-Z 050508ns

2964 tb l 09

NOTE:

1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.

6.42

IDT71024 CMOS Static RAM

1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges

5

NOTES:

1. WE is HIGH for Read Cycle.

2. Device is continuously selected, CS1 is LOW, CS2 is HIGH.

3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter.

4. OE is LOW.

5. Transition is measured ±200mV from steady state.

Timing Waveform of Read Cycle No. 1(1)

Timing Wavefor m of Read Cycle No. 2(1,2,4)

6.42

6

IDT71024 CMOS Static RAM

1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges

Timing Wavefor m of Write Cycle No. 1

(WE Controlled Timing)(1,4,6)

Timing Wavefor m of Write Cycle No. 2

(CS1 AND CS2 Controlled Timing)(1,4)

NOTES:

1. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE.

2. tWR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the CS1 LOW transition or the CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS1 and CS2 must

both be active during the tCW write period.

5. Transition is measured ±200mV from steady state.

6. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed

on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP.

6.42

IDT71024 CMOS Static RAM

1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges

7

Ordering Information

6.42

8

IDT71024 CMOS Static RAM

1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges

Datasheet Document History

9/30/99 Updated to new format

Pg. 1, 3, 4, 7 Added 12ns industrial speed grade offering

Pg. 1–4, 7 Removed military temperature offerings

Removed 17ns and 25ns speed grades

Pg. 3 Revised ICC and ISB1 for 15ns and 20ns industrial speed grades

Pg. 6 Removed Note 1, reordered notes and footnotes

Pg. 8 Added Datasheet Document History

1/6/2000 Pg. 4 Changed tWP(min) for 12ns speed grade from 10ns to 8ns.

2/18/00 Pg. 3 Revised Icc and ISB for Industrial Temperature offerings to meet commercial specifications

3/14/00 Pg. 3 Revised ISB to accomidate speed functionaility

08/09/00 Not recommended for new designs

02/01/01 Removed "Not recommended for new designs"

01/30/04 Pg. 7 Added "Restricted hazardous substance device" to the ordering information.

05/22/06 Pg.3 Added drawing Output Capacitive Derating drawing.

02/13/07 Pg.7 Added M generation die step to data sheet ordering information.

08/13/09 Pg.2 Corrected note reference.

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