UltraLogic™ 64-Macrocell Flash CPLD
CY7C373i
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Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-03030 Rev. *A Revised April 8, 2004
Features
• 64 macrocells in fou r logi c bl oc ks
• 64 I/O pins
• 5 dedicated inputs including 4 clock pins
• In-System Reprogramm able™ (ISR™) Flash
technology
—JTAG interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
•High speed
—f
MAX = 125 MHz
—t
PD = 10 ns
—t
S = 5.5 ns
—t
CO = 6.5 ns
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
• Available in 84-pin PLCC and 100-pin TQFP packages
• Pin compatible with the CY7C374i
Functional Description
The CY7C373i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C373i is
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic™ FLASH370i devices, the CY7C37 3i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins.The ISR interface is enabled
using the programming voltage pin (ISREN). Additionally,
because of the su perior routability of the FLASH370i devices,
ISR often allows users to change e xisting l ogic designs whi le
simultaneously fixing pinout assignments.
Logic Block Diagram
PIM
INPUT
MACROCELL
CLOCK
INPUTS
INPUT
LOGIC LOGIC
22
36
16 16
36
16 I/Os 16 I/Os
32 32
LOGIC
36
16 16
36
16 I/Os 16 I/Os
41
INPUT/CLOCK
MACROCELLS
I/O0-I/O15 LOGIC
I/O16-I/O31
I/O48−I/O63
I/O32−I/O47
BLOCK
A
BLOCK
BBLOCK
C
BLOCK
D
Selection Guide
7C373i–125 7C373i–100 7C373i–83 7C373iL-83 7C373i–66 7C373iL–66
Maximum Propagation Delay[1], tPD (ns) 10 12 15 15 20 20
Minimum Set-up, tS (ns) 5.5 6.0 8 8 10 10
Maximum Clock to Output[1], tCO (ns) 6.5 6.5 8 8 10 10
Typical Supply Current, ICC (mA) 75 75 75 45 75 45
Note:
1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V.
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Pin Configurations
Top View
TQFP
100 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
40
39
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
SDI
NC
VCCIO
I/O55
I/O54
I/O53
I/O52
CLK3/I4
I/O50
I/O48
GND
NC
I/O47
I/O46
I/O49
GND
SMODE
SCLK
GND
I/O8
I/O9
I/O10
I/O11
I/O15
VCCIO
GND
CLK1/I1
I/O15
I/O17
CLK0/I0
9091
I/O51
VCCIO
CLK2/I3
I/O14
N/C
I/O12
I/O13
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
GND
NC
GND
NC
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
VCCIO
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 48 49 50
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
VCCINT
VCCIO
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I2
NC
VCCIO
SDO
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
2
1
VCCINT
I/O0
VCCIO
NC
63
I/O62
61
60
59
58
57
56
VCCIO
I/O
I/O14
I/O15 I/O48
Top View
PLCC
98 6
7 5
13
14
12
11
4948
58
59
60
23
24
26
25
27
15
16
4746
43
28
33
20
21
19
18
17
22
34 35 3736 38 4241 43
40
66
65
63
64
62
61
7C373
67
68
69
74
72
73
71
70
84 8182 80
279
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O55
I/O54/SDI
I/O53
I/O52
I/O51
GND
I/O49
CLK3/I4
VCCIO
CLK2/I3
I/O45
I/O44
GND
I/O
I/O8
I/O9
I/O10/SCLK
I/O11
I/O12
I/O13
CLK0/I0
VCCIO
CLK1/I1
I/O16
I/O17
I/O18
I/O19
I/O20
535250
30
29
31
32
I/O
I/O
I/O
I/O
54
55
56
57 I/O43
I/O42
I/O41
I/O40
7778 76 75
I/O21
I/O22
I/O23
GND
I/O
I/O50
I/O47
I/O46
GND
24
I/O25
I/O26 I/O27
I/O28
I/O29
I/O30
I/O31
VCCINT
VCCIO
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38I/O39
GND
I2
7
6
5
4
3
2
1
VCCINT
I/O0
VCCIO
63
I/O62
61
60
59
58
57
56
ISREN
/SMODE
/SDO
ISREN
10
39 44
83
45 51
1
99
47
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Functional Description
The 64 macrocells in the CY7C37 3i are divid ed be tween fou r
logic blocks. Each logic block incl udes 16 macrocells, a 72 x
86 product term array , and an intelligent product term allocator.
The logic blocks in the FLASH370i architecture are connected
with an extreme ly fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Like all members of the FLASH370i family , the CY7C373i is rich
in I/O resources. Every macrocell in the device features an
associated I/O pin, resulting in 64 I/O pins on the CY7 C373i.
In addition, there is one dedicated input and four input/clock
pins.
Finally, the CY7C373i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used or the type of application, the timing param-
eters on the CY7C373i remain the same.
Logic Block
The number of logic blocks d istinguishes the membe rs of the
FLASH370i family. The CY7C373i includes four logic blocks.
Each logic block is constructed of a product term array, a
product term allocator, and 16 macrocells.
Product Term Array
The product term array in the FLASH370i logic block in cludes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in single
passes through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product term resources to macrocells that require
them. Any number of product terms between 0 and 16
inclusive can be assigned to any of the logic block macrocells
(this is called product term steering). Furthermore, product
terms can be shared among multiple macrocells. Th is mean s
that product terms that are common to more than one output
can be implemented in a single product term. Product term
steering and product term sharing help to increase the
effective density of the FLASH370i CPLDs. Note that the
product term allocator is handl ed by software and is invisible
to the user.
I/O Macrocell
Each of the macrocells on the CY7C373i has a separate I/O
pin associated with it. In oth er words, each I/O pin is shared
by two macrocells. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term
allocator. The macrocell includes a register that can be
optionally bypassed, polarity control over the input sum-term,
and two global clocks to trigger the register. The macrocell
also features a se parate feed b ac k path to the PIM so that the
register can be buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
four logic blocks on the CY7C373i to the inputs and to each
other. All inputs (including feedbacks) travel th rough the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the FLASH370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An
Introduction to In System Reprogramming with FLASH370i.”
PCI Compliance
The FLASH370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Speci fication publishe d by the PCI Special
Interest Group. The simple and predictable timing model of
FLASH370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
3.3V or 5.0V I/O operation
The FLASH370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of VCC pin s:
one set, VCCINT, for internal operation and input buffers, and
another set, VCCIO, for I/O output drivers. VCCINT pins must
always be connected to a 5.0V power supply. However, the
VCCIO pins may be connected to either a 3.3V or 5.0V powe r
supply, depending on the output requirements. When VCCIO
pins are connected to a 5.0V source, the I/O voltage levels are
compatible with 5.0V systems. When VCCIO pins are
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is
available in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability , a new feature called bus-hold has
been added to all FLASH370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor , is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus
reducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the de vice without cutting
trace connections to VCC or GND.
Design Tools
Development software for the CY7C371i is available from
Cypress’s Warp™, Warp Professional™, and Warp Enter-
prise™ software packages. Please refer to the data sheets on
these products for more details. Cypress also actively
supports almost all third-party design tools. Please refer to
third-party tool support for further information.
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Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ...............................................–0.5V to +7.0V
DC Input Voltage............................................–0.5V to +7.0V
DC Program Voltage.....................................................12.5V
Output Current into Output s................. .. .............. ... ... ..16 mA
Static Discharge Voltage............................................>2001V
(per MIL–STD–883, Method 3015)
Latch-Up Current................................... ... ... ............>200 mA
Operating Range
Range Ambient
Temperature VCC
VCCINT VCCIO
Commercial 0°C to +70°C5V ± 0.25V 5V ± 0.25V
OR
3.3V ± 0.3V
Industrial −40°C to +85°C5V ± 0.5V 5V ± 0.5V
OR
3.3V ± 0.3V
Electrical Characteristics Over the Operating Range[2]
Parameter Description Test Conditions Min. Typ. Max. Unit
VOH Output HIGH Voltage VCC = Min. IOH = –3.2 mA (Com’l/Ind)[3] 2.4 V
VOHZ Output HIGH Voltage
with Output Disabled[7] VCC = Max. IOH = 0 µA (Com’l/Ind)[3, 4] 4.0 V
IOH = –50 µA (Com’l/Ind)[3, 4] 3.6 V
VOL Output LOW Voltage VCC = Min. IOL = 16 mA (Com’l/Ind)[3] 0.5 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs[5] 2.0 7.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all In puts[5] –0.5 0.8 V
IIX Input Load Current VI = Internal GND, VI = VCC –10 +10 µA
IOZ Output Leakage Current VCC = Max., VO = GND or VO = VCC, Output Disabled –50 +50 µA
VCC = Max., VO = 3.3V, Output Disabled[4] 0–70 –125 µA
IOS Output Short
Circuit Current[6, 7] VCC = Max., VOUT = 0.5V –30 –160 mA
ICC Power Supply Current[8] VCC = Max., IOUT = 0 mA,
f = 1 MHz, VIN = GND, VCC Com’l/Ind. 75 125 mA
Com’l “L”, –66 45 75 mA
IBHL Input Bus Hold LOW
Sustaining Current VCC = Min., VIL = 0.8V +75 µA
IBHH Input Bus Hold HIGH
Sustaining Current VCC = Min., VIH = 2.0V –75 µA
IBHLO Input Bus Hold LOW
Overdrive Current VCC = Max. +500 µA
IBHHO Input Bus Hold HIGH
Overdrive Current VCC = Max. –500 µA
Notes:
2. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT.
3. IOH = –2 mA, IOL = 2 mA for SDO.
4. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly
by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note “Understanding Bus Hold” for additio nal
information.
5. These are absolute values with respect to device ground. All overshoots due to system or tester noi se are included.
6. Not more than one output should be te sted at a time. Duratio n of the short circuit should not exceed 1 seco nd. VOUT = 0.5V has been chose n to avoid test problems
caused by tester groun d degradation.
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Capacitance[7]
Parameter Description Test Conditions Min. Max. Unit
CIN[9] Input Capacitance VIN = 5.0V at f = 1 MHz 8 pF
CCLK Clock Signal Capa citance VIN = 5.0V at f = 1 MHz 5 12 pF
Inductance[7]
Parameter Description Test Conditions 100-Pin TQFP 84-Lead PLCC Unit
L Maximum Pin Inductance VIN = 5.0V at f = 1 MHz 8 8 nH
Endurance Characteristics[7]
Parameter Description Test Conditions Max. Unit
N Maximum Reprogramming Cycles Normal Programming Conditions 100 Cycles
AC Test Loads and Waveforms
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
<2ns <2ns
OUTPUT
238Ω(COM'L)
170Ω(COM'L)
236Ω(MIL)
99Ω(COM'L)
Equivalent to: THÉ VENIN EQUIVALENT
2.08V(COM'L)
238Ω(COM'L)
319Ω(MIL)
170Ω(COM'L)
(c)
Parameter[10] VxOutput Waveform–Measurement Level
tER(–) 1.5V
tER(+) 2.6V
tEA(+) 1.5V
tEA(–) Vthe
(d) Test W aveforms
Notes:
7. Tested initially and af ter any design or process changes t hat may affect these parameters.
8. Measured with 16-bit counter pr ogrammed into each logic block.
9. CI/O for dedicated Inputs, and I/Os with JTAG functionalit y i s 12 pF Max., and for ISREN is 15 pF Max.
10.tER measured wi th 5-pF AC Test Load and t EA measured with 35-pF AC Test Load.
VOH 0.5V VX
0.5V
VOL VX
0.5V
VXVOH
0.5V
VXVOL
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Switching Characteristics Over the Operating Range[11]
7C373i–125 7C373i–100 7C373i–83
7C373iL-83 7C373i–66
7C373iL–66
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
Combinatorial Mode Parameters
tPD Input to Combinatorial Output[1] 10 12 15 20 ns
tPDL Input to Output Through Transparent Input or
Output Latch[1] 13 15 18 22 ns
tPDLL Input to Output Through Transparent Input and
Output Latches[1] 15 16 19 24 ns
tEA Input to Output Enable[1] 14 16 19 24 ns
tER Input to Output Disable 14 16 19 24 ns
Input Registered/Latched Mode Parameters
tWL Clock or Latch Enable Input LOW Time[7] 3 3 4 5 ns
tWH Clock or Latch Enable Input HIGH Time[7] 3 3 4 5 ns
tIS Input Register or Latch Set-Up Time 2 2 3 4 ns
tIH Input Register or Latch Hold Time 2 2 3 4 ns
tICO Input Register Clock or Latch Enable to
Combinatorial Output[1] 14 16 19 24 ns
tICOL Input Register Clock or Latch Enable to
Output Through Transparent Output Latch[1] 16 18 21 26 ns
Output Registered/Latched Mode Parameters
tCO Clock or Latch Enable to Output[1] 6.5 6.5 810 ns
tSSet-Up Time from Input to Clock or Latch
Enable 5.5 6 8 10 ns
tHRegister or Latch Data Hold Time 0 0 0 0 ns
tCO2 Output Clock or Latch Enable to Output Delay
(Through Memory Array)[1] 14 16 19 24 ns
tSCS Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array) 810 12 15 ns
tSL Set-Up Time from Input Through T ransparent
Latch to Output Register Clock or Latch
Enable
10 12 15 20 ns
tHL Hold Time for Input Through Transparent Latch
from Output Register Clock or Latch Enable 0 0 0 0 ns
fMAX1 Maximum Frequency with Internal Feedback
(Least of 1/tSCS, 1/(tS + tH), or 1/tCO)[7] 125 100 83 66 MHz
fMAX2 Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(tWL +
tWH), 1/(tS + tH), or 1/tCO)[7]
153.8 153.8 125 100 MHz
fMAX3 Maximum Frequency of (2) CY7C373is with
External Feedback (Lesser of 1/(tCO + tS) and
1/(tWL + tWH)[7]
83.3 80 62.5 50 MHz
tOH–tIH
37x Output Data Stable from Output clock Minus
Input Register Hold Time for 7C37x[7, 12] 0 0 0 0 ns
Notes:
11.All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
12.This specification is intended to guarant ee interface comp atibility of the other members of the CY7C370i family with the CY7C37 3i. This specification is met for
the devices operating at the same ambient temperature and at the same power supply voltage.
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Pipelined Mod e Parameters
tICS Input Register Clock to Output Register Clock 810 12 15 ns
fMAX4 Maximum Frequency in Pipelined Mode (Least
of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + t IH), or
1/tSCS)[7]
125 83.3 66.6 50.0 MHz
Reset/Preset Parameters
tRW Asynchronous Reset Width[7] 10 12 15 20 ns
tRR Asynchronous Reset Recovery Time[7] 12 14 17 22 ns
tRO Asynchronous Reset to Output[1] 16 18 21 26 ns
tPW Asynchronous Preset Width[7] 10 12 15 20 ns
tPR Asynchronous Preset Recovery Time[7] 12 14 17 22 ns
tPO Asynchronous Preset to Output[1] 16 18 21 26 ns
Tap Controller Parameter
fTAP Tap Controller Frequency 500 500 500 500 kHz
3.3V I/O Mode Parameters
t3.3IO 3.3V I/O mode timing adder 1 1 1 1 ns
Switching Characteristics Over the Operating Range[11] (continued)
7C373i–125 7C373i–100 7C373i–83
7C373iL-83 7C373i–66
7C373iL–66
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
Switching Waveforms
Combinatorial Output
tPD
INPUT
COMBINATORIAL
OUTPUT
tS
INPUT
CLOCK tCO
REGISTERED
OUTPUT
tH
CLOCK
tWL
tWH
Registered Output
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Switching Waveforms (continued)
Latched Output
tS
INPUT
LATCH ENABLE
tCO
LATCHED
OUTPUT
tH
tPDL
Clock to Clock
REGISTERED
INPUT
INPUT REGISTER
CLOCK tICS
OUTPUT
REGISTER CLOCK
tSCS
Latched Input
tIS
LATCHED INPUT
LATCH ENABLE
tICO
COMBINATORIAL
OUTPUT
tIH
tPDL
LATCHENABLE
tWL
tWH
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Switching Waveforms (continued)
Latched Input and Output
tICS
LATCHED INPUT
OUTPUT LATCH
ENABLE
LATCHED
OUTPUT
tPDLL
LATCH ENABLE
tWL
tWH
tICOL
INPUT LATCH
ENABLE
tSL tHL
Asynchronous Reset
INPUT
tRO
REGISTERED
OUTPUT
CLOCK
tRR
tRW
Asynchronous Preset
INPUT
tPO
REGISTERED
OUTPUT
CLOCK
tPR
tPW
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Switching Waveforms (continued)
Output Enable/Disable
INPUT
tER
OUTPUTS
tEA
Ordering Information
Speed
(MHz) Ordering Code Package
Type Package
Type Operating
Range
125 CY7C373i–125AC A100 100-Pin Thin Quad Flatpack Commercial
CY7C373i–125JC J83 84-Lead Plastic Leaded Chip Carrier
100 CY7C373i–100AC A100 100-Pin Thin Quad Flatpack Commercial
CY7C373i–100JC J83 84-Lead Plastic Leaded Chip Carrier
CY7C373i–100AI A100 100-Pin Thin Quad Flatpack Industrial
CY7C373i–100JI J83 84-Lead Plastic Leaded Chip Carrier
83 CY7C373i–83AC A100 100-Pin Thin Quad Flatpack Commercial
CY7C373i–83JC J83 84-Lead Plastic Leaded Chip Carrier
CY7C373i–83AI A100 100-Pin Thin Quad Flatpack Industrial
CY7C373i–83JI J83 84-Lead Plastic Leaded Chip Carrier
CY7C373iL–83JC J83 84-Lead Plastic Leaded Chip Carrier Commercial
66 CY7C373i–66AC A100 100-Pin Thin Quad Flatpack Commercial
CY7C373i–66JC J83 84-Lead Plastic Leaded Chip Carrier
CY7C373i–66AI A100 100-Pin Thin Quad Flatpack Industrial
CY7C373i–66JI J83 84-Lead Plastic Leaded Chip Carrier
CY7C373iL–66JC J83 84-Lead Plastic Leaded Chip Carrier Commercial
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Document #: 38-03030 Rev. *A Page 11 of 12
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circ uitry other than cir cuitry embodied i n a Cypress Semi conductor product. Nor does it convey or imply any l icense under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor product s in life-support syste ms application implies th at th e manu fac turer assu mes all risk of such use and in doing so ind emnifie s Cypress Semicondu ctor ag ainst all charges.
Warp is a registered trademark and Ultra37000, FLASH370, FLASH370i, ISR, UltraLogic, Warp Professional, and Warp Enterprise
are trademarks of Cypress Semicon ductor Corporation. All produ cts and company names mentioned in this document may be
the trademarks of their respective holders.
Package Diagrams
100-Pin Thin Plastic Quad Flat Pack (TQFP) A10 0
51-85048-*B
84-Lead Plastic Leaded Chip Carrier J83
51-85006-*A
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CY7C373i
USE ULTRA37000TM FOR
ALL NEW DESIGNS
Document #: 38-03030 Rev. *A Page 12 of 12
Document History Page
Document Title: CY7C373i UltraLogic™ 64-Macrocell Flash CPLD
Document Number: 38-03030
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 106375 09/17/01 SZV Change from Spec number: 38-00495 to 38-03030
*A 213375 See ECN FSG Added note to title page: “Use Ultra37000 For All New Designs”
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